DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (10446638) in view of Moon et al. (11,696,470).
With regard to claim 25, Seo et al. disclose a display device (for example, see fig. 1) comprising:
a substrate (100) including a display area (an area including transistors T1, T2);
a driving transistor (T1) in the display area, the driving transistor including a first semiconductor layer (S1, C1, D1) having a first S-factor (for example, see column 4, lines 37 – 43);
a switching transistor (T2) in the display area, the switching transistor (T2) including a second semiconductor layer having a second S-factor (for example, see column 4, lines 37 – 43); and
a light emitting device (OLED) in the display area, wherein the first S-factor is greater than the second S-factor (for example, see column 4, lines 37 – 43 discloses the S-factor of the driving transistor T1 is relatively large, and the S-factor of the switching transistor T2 is relatively small. The differences in S-factors may be formed by implementing a difference in the surface roughness between the semiconductor layers of the driving transistor T1 and the switching transistor T2. Therefore, the first semiconductor layer of the driving transistor T1 inherently has a S-factor that is greater than a S-factor of the second semiconductor layer).
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Seo et al. do not clearly disclose the first and second semiconductor layers are oxide semiconductor layers.
However, Moon et al. disclose the first and second semiconductor layers (A1, A2) are oxide semiconductor layers (for example, see column 9, lines 41 – 49, fig. 10).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Seo et al.’s device to replace the first and second semiconductor layers are oxide semiconductor layers as taught by Moon et al. in order to enhance a high mobility efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
3. Claims 1 - 17 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a surface treating layer including a pattern of protrusions is on a surface of the first oxide semiconductor layer of the driving thin film transistor and the second oxide semiconductor layer of the switching thin film transistor lacks the surface treating layer on a surface of the second oxide semiconductor layer, and wherein the first oxide semiconductor layer has a S-factor that is greater than a S-factor of the second oxide semiconductor layer by the surface treating layer as recited in claim 1.
4. Claims 18, 21 - 24 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the first transistor including a first semiconductor layer with a pattern of protrusions on at least a portion of a surface of the first semiconductor layer; wherein the second semiconductor layer lacks the pattern of protrusions on any surface of the second semiconductor layer, and wherein the first semiconductor layer with the pattern of protrusions has a S-factor that is greater than a S-factor of the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are oxide semiconductor layers as recited in claim 18.
Response to Arguments
5. Applicant’s arguments filed 07/06/26 have been fully considered but they are not persuasive.
It is argued, at page of the remarks, that “there is no motivation for one of ordinary
skill to combine Seo and Moon and arrive at the claimed invention with reasonable expectation
of success”. However, in response to applicant's argument that there is no suggestion to combine the references, the examiner recognizes that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.d. 1071, 5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.d. 347, 21 USPQ2d 1941 (Fed. Cir. 1992). In this case, the applicant made the erroneous assumption that the motivation to combine must be expressly stated in the art of record. From MPEP § 2144:
"The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law. In re Fine, 837 F.d. 1071, 5 USPQ2d 1596 (Fed. Cir. 1988); In re Jones, 958 F.d. 347, 21 USPQ2d 1941 (Fed. Cir. 1992). See also In re Eli Lilly & Co., 902 F.d. 943, 14 USPQ2d 1741 (Fed. Cir. 1990) (discussion of reliance on legal precedent); In re Nilssen, 851 F.d. 1401, 1403, 7 USPQ2d 1500, 1502 (Fed. Cir. 1988) (references do not have to explicitly suggest combining teachings); Ex parte Clapp, 227 USPQ 972 (Bd. Pat. App. & Inter. 1985) (examiner must present convincing line of reasoning supporting rejection); and Ex parte Levengood, 28 USPQ2d 1300 (Bd. Pat. App. & Inter. 1993) (reliance on logic and sound scientific reasoning)." [Emphasis added]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Seo et al.’s device to replace the first and second semiconductor layers are oxide semiconductor layers as taught by Moon et al. in order to enhance a high mobility efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Thus, applicant’s claim 25 does not distinguish over cited references.
Conclusion
6. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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