CTFR 17/980,281 CTFR 84148 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments Applicant’s arguments filed 03/16/2026 addressing the amended claims are not persuasive as the Shih reference teaches non-uniform opposing outer sidewalls as discussed in the updated rejection below. See also the addition of the Lim reference as discussed below which is newly cited and relied upon as necessitated by Applicant’s claim amendments to show additional configurations of a non-uniform opposing outer sidewalls of a dielectric layer in a skip via. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication Number 2022/0392800 A1 to Lim et al, “Lim” . Regarding claim 1, Kim discloses a semiconductor structure (e.g. FIG. 7), comprising: a skip via (240t and 331t together, ¶ [0074]-[0075],[0079]) disposed on a metal line (140, ¶ [0018],[0019]) of a first metallization layer; and a dielectric layer (231 and 331, ¶ [0075],[0079]) disposed on vertical sidewalls of the skip via to define an opening; wherein the dielectric layer (231 and 331 together) has uniform sidewalls (inside sidewalls contacting 240 and 340) from an uppermost portion of the opening to a lowermost portion of the opening; and wherein an opposing vertical sidewall of the dielectric layer is a non-uniform sidewall (due to recesses 231r and 331r, ¶ [0074],[0113]) from an uppermost portion of the dielectric layer to a lowermost portion of the dielectric layer . 07-15 AIA Claim s 1,9-11,16 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by U.S. Patent Application Publication Number 2021/0249354 A1 to Shih, “Shih” . Regarding claim 1, Shih discloses a semiconductor structure (e.g. FIG. 10), comprising: a skip via (via with 125a on left, ¶ [0065]) disposed on a metal line (105, ¶ [0040],[0041]) of a first metallization layer; and a dielectric layer (123a and 143a together , ¶ [0064]) disposed on vertical sidewalls of the skip via to define an opening (filled with 125a); wherein the dielectric layer (123a and 143a together ) has uniform sidewalls (interior sidewalls facing 125a) from an uppermost portion of the opening to a lowermost portion of the opening, and wherein an opposing vertical sidewall of the dielectric layer is a non-uniform sidewall from an uppermost portion of the dielectric layer to a lowermost portion of the dielectric layer (see Examiner-annotated figure below): PNG media_image1.png 851 942 media_image1.png Greyscale Examiner’s Note: the term “non-uniform” is not expressly defined in Applicant’s specification and is therefore interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) as being generally not the same in all parts or areas. Since the vertical sidewalls of Shih are interrupted by a step, the vertical sidewalls of Shih would be considered non-uniform by one having ordinary skill in the art. Regarding claim 9, Shih discloses the semiconductor structure according to claim 1, and Shih further discloses comprising a conductive material (125a, ¶ [0065]) disposed in the opening; wherein the dielectric layer (123a and 143a together ) has a uniform flush surface (interior surface facing 125a) in contact with the conductive material (125a). Regarding claim 10, Shih discloses a semiconductor structure (e.g. FIG. 10), comprising: a skip via (via with 125a on left, ¶ [0065]) disposed on a metal line (105, ¶ [0040],[0041]) of a first metallization layer, the skip via comprising a first portion disposed in a first interlayer dielectric layer (e.g. portion within 107, ¶ [0041]), and a second portion disposed in a second interlayer dielectric layer (e.g. portion within 113, ¶ [0042]); and a dielectric layer (123a and 143a together , ¶ [0064]) disposed on vertical sidewalls of the first portion and the second portion of the skip via to define an opening, the dielectric layer having a varying thickness (due to additional thickness from 143a, see Examiner-annotated figure below); wherein the dielectric layer (123a and 143a together ) has uniform (interior) sidewalls from an uppermost portion of the opening to a lowermost portion of the opening (as pictured), wherein an opposing vertical sidewall of the dielectric layer is a non-uniform sidewall from an uppermost portion of the dielectric layer to a lowermost portion of the dielectric layer (see Examiner-annotated figure with claim 1 above): PNG media_image2.png 595 644 media_image2.png Greyscale Regarding claim 11, Shih discloses the semiconductor structure according to claim 10, and Shih further discloses wherein a conductive material (125a) is part of the skip via (as pictured). Regarding claim 16, Shih discloses an integrated circuit (e.g. FIG. 10), comprising: one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises: a skip via (via with 125a on left, ¶ [0065]) disposed on a metal line (105, ¶ [0040],[0041]) of a first metallization layer; and a dielectric layer (123a and 143a together , ¶ [0064]) disposed on vertical sidewalls of the skip via to define an opening; wherein the dielectric layer (123a and 143a together ) has uniform sidewalls (as pictured) from an uppermost portion of the opening to a lowermost portion of the opening, wherein an opposing vertical sidewall of the dielectric layer is a non-uniform sidewall from an uppermost portion of the dielectric layer to a lowermost portion of the dielectric layer (see Examiner-annotated figure with claim 1 above) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 2-6,12-15,17-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0249354 A1 to Shih, “Shih”, in view of U.S. Patent Application Publication Number 2019/0021176 A1 to Law et al., “Law” . Regarding claim 2, Shih discloses the semiconductor structure according to claim 1, and Shih further teaches: a first metal via (125b, ¶ [0042],[0043]) disposed on another metal line (109, ¶ [0041]); and a second metallization layer (e.g. 147b) disposed on the first metal via (125b). Shih fails to clearly teach wherein said another metal line (109) is of the first metallization layer (105) since they are at different heights. Law teaches (e.g. FIG. 3) a skip via (135, ¶ [0020]) and additionally a first metal via (V1 to the right) on another metal line (M1) of a first metallization layer; and a second metallization (M2) disposed on the first metal via (V1). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have applied the improved spacer material (dielectric layers 123a and 143a together) from Shih as applied to the skip via configuration of Law in order to desirably reduce the capacitive coupling between the conductive features of Law ( Shih ¶ [0001]-[0003],[0085],[0088]). Alternatively, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Shih using the configuration of a skip via combined with regular vias (V1, M1, M2) as taught by Law in order to incorporate an additional capping layer (115,115’’’) which improves the alignment of the skip via and achieve good gap fill alleviating minimum insulator concerns ( Law ¶ [0015],[0001]-[0004]). Regarding claim 3, Shih in view of Law yields the semiconductor structure according to claim 2, and Law further teaches wherein the first metal via (V1) and the second metallization layer (M2) are disposed in a first interlayer dielectric layer (105’). Regarding claim 4, Shih in view of Law yields the semiconductor structure according to claim 3, and Law further teaches wherein a portion of the skip via (135) is disposed in the first interlayer dielectric layer (105’). Regarding claim 5, Shih in view of Law yields the semiconductor structure according to claim 4, and Law further teaches (FIG. 6) a second metal via (V2) disposed on the second metallization layer (M2); and a third metallization layer (M3) comprising a plurality of metal lines (one above via V2, another above skip via 135), wherein a metal line of the plurality of metal lines is disposed on the second metal via (V2). Regarding claim 6, Shih in view of Law yields the semiconductor structure according to claim 5, and Law further teaches wherein the second metal via (V2) and the third metallization layer (M3) are disposed in a second interlayer dielectric layer (105’’). Regarding claim 12, Shih discloses the semiconductor structure according to claim 10, and Shih further discloses a first metal via (125b, ¶ [0042],[0043]) disposed on another metal line (109, ¶ [0041]); and a second metallization layer (e.g. 147b) disposed on the first metal via (125b). Shih fails to clearly teach wherein said another metal line (109) is of the first metallization layer (105) since they are at different heights. Law teaches (e.g. FIG. 3) a skip via (135, ¶ [0020]) and additionally a first metal via (V1 to the right) on another metal line (M1) of a first metallization layer; and a second metallization (M2) disposed on the first metal via (V1). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have applied the improved spacer material (dielectric layers 123a and 143a together) from Shih as applied to the skip via configuration of Law in order to desirably reduce the capacitive coupling between the conductive features of Law ( Shih ¶ [0001]-[0003],[0085],[0088]). Alternatively, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Shih using the configuration of a skip via combined with regular vias (V1, M1, M2) as taught by Law in order to incorporate an additional capping layer (115,115’’’) which improves the alignment of the skip via and achieve good gap fill alleviating minimum insulator concerns ( Law ¶ [0015],[0001]-[0004]). Regarding claim 13, Shih in view of Law yields the semiconductor structure according to claim 12, and Law further teaches wherein the first metal via (V1) and the second metallization layer (M2) are disposed in a first interlayer dielectric layer (105’). Regarding claim 14, Shih in view of Law yields the semiconductor structure according to claim 13, and Law further teaches (FIG. 6) a second metal via (V2) disposed on the second metallization layer (M2); and a third metallization layer (M3) comprising a plurality of metal lines (one above via V2, another above skip via 135), wherein a metal line of the plurality of metal lines is disposed on the second metal via (V2). Regarding claim 15, Shih in view of Law yields the semiconductor structure according to claim 14, and Law further teaches wherein the second metal via (V2) and the third metallization layer (M3) are disposed in a second interlayer dielectric layer (105’’). Regarding claim 17, Shih discloses the integrated circuit according to claim 16, and Shih further discloses wherein the at least one of the one or more semiconductor structures further comprises: a first metal via (125b, ¶ [0042],[0043]) disposed on another metal line (109, ¶ [0041]); and a second metallization layer (e.g. 147b) disposed on the first metal via (125b); Shih fails to clearly teach wherein said another metal line (109) is of the first metallization layer (105) since they are at different heights, wherein the first metal via and the second metallization layer are disposed in a first interlayer dielectric layer. Law teaches (e.g. FIG. 3) a skip via (135, ¶ [0020]) and additionally a first metal via (V1 to the right) on another metal line (M1) of a first metallization layer; and a second metallization (M2) disposed on the first metal via (V1), wherein the first metal via (V1) and the second metallization layer (M2) are disposed in a first interlayer dielectric layer (105’). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have applied the improved spacer material (dielectric layers 123a and 143a together) from Shih as applied to the skip via configuration of Law in order to desirably reduce the capacitive coupling between the conductive features of Law ( Shih ¶ [0001]-[0003],[0085],[0088]). Alternatively, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Shih using the configuration of a skip via combined with regular vias (V1, M1, M2) as taught by Law in order to incorporate an additional capping layer (115,115’’’) which improves the alignment of the skip via and achieve good gap fill alleviating minimum insulator concerns ( Law ¶ [0015],[0001]-[0004]). Regarding claim 18, Shih in view of Law yields the integrated circuit according to claim 17, and Law further teaches wherein a portion of the skip via (135) is disposed in the first interlayer dielectric layer (105’). Regarding claim 19, Shih in view of Law yields the integrated circuit according to claim 18, and Law further teaches (FIG. 6) wherein the at least one of the one or more semiconductor structures further comprises: a second metal via (V1) disposed on the second metallization layer (M2); and a third metallization layer (M3) comprising a plurality of metal lines (one above via V2, another above skip via 135), wherein a metal line of the plurality of metal lines is disposed on the second metal via; wherein the second metal via (V2) and the third metallization layer (M3) are disposed in a second interlayer dielectric layer (105’’) . 07-21-aia AIA Claim s 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0249354 A1 to Shih, “Shih”, in view of U.S. Patent Application Publication Number 2019/0021176 A1 to Law et al., “Law”, further in view of U.S. Patent Application Publication Number 2020/0388567 A1 to Mignot et al., “Mignot” . Regarding claims 7 and 20, although Shih in view of Law yields the semiconductor structure according to claims 6 and 19, Shih in view of Law fails to clearly teach wherein another portion of the skip via is disposed in the second interlayer dielectric layer. Mignot teaches (e.g. FIG. 8) wherein a skip via (super via 132) has a first portion within a first interlayer dielectric layer (114) and another portion disposed in a second interlayer dielectric layer (120, ¶ [0043]) It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Shih in view of Law with the skip via or super via passing through a plurality of interlayer dielectrics as exemplified by Mignot in order to achieve more efficient routing between the lower and upper metallization layers ( Mignot ¶ [0001],[0002]) which adds flexibility in integrated circuit designs while addressing capacitance and high aspect ratio concerns ( Mignot ¶ [0003],[0025],[0044]) . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0249354 A1 to Shih, “Shih”, in view of U.S. Patent Application Publication Number 2021/0193513 A1 to Tien et al., “Tien” . Regarding claim 8, Shih discloses the semiconductor structure according to claim 1, and although Shih discloses wherein the dielectric layer comprises a material (123a) having a dielectric constant higher than silicon oxide (i.e. silicon nitride) or other applicable material (¶ [0064]), Shih fails to clearly state wherein the dielectric layer comprises a high-k dielectric material. Tien teaches wherein a dielectric layer (120) may comprise a high-k material (e.g. aluminum oxide, ¶ [0018]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Shih with the dielectric material comprising aluminum oxide as taught by Tien in order to desirably add protection to the sidewalls of the via and reducing the critical dimension while also maintaining or increasing the reliability of the overall chip ( Tien Abstract, ¶ [0004],[0005],[0013]), and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp ., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin , 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Eric A. Ward/Primary Examiner, Art Unit 2891 Application/Control Number: 17/980,281 Page 2 Art Unit: 2891 Application/Control Number: 17/980,281 Page 3 Art Unit: 2891 Application/Control Number: 17/980,281 Page 4 Art Unit: 2891 Application/Control Number: 17/980,281 Page 5 Art Unit: 2891 Application/Control Number: 17/980,281 Page 6 Art Unit: 2891 Application/Control Number: 17/980,281 Page 7 Art Unit: 2891 Application/Control Number: 17/980,281 Page 8 Art Unit: 2891 Application/Control Number: 17/980,281 Page 9 Art Unit: 2891 Application/Control Number: 17/980,281 Page 10 Art Unit: 2891 Application/Control Number: 17/980,281 Page 11 Art Unit: 2891 Application/Control Number: 17/980,281 Page 12 Art Unit: 2891
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