Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-22 are pending.
-Claims 1, 8, 12, 17, 18, and 21 are amended.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 25, 2025 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Examiner noted in the previous Office Action, dated July 2, 2025, that in order to effectively benefit from the foreign priority date based on the application filed in the Republic of Korea on December 7, 2021, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented. The Applicant has not included these documents in the instant application. Therefore, the right to foreign priority under 35 U.S.C. 119 (a)-(d) is not considered perfected.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn.
Claim Rejections - 35 USC § 112
Acknowledgement is made of Applicant’s amendments to Claims 12, 17, and 21 as they relate to the 35 U.S.C. § 112 rejections in the Office Action dated July 2, 2025. The rejections under 35 U.S.C. § 112 are hereby withdrawn.
Response to Arguments
Applicant's amendments and arguments filed October 2, 2025 as they relate to the rejections under 35 U.S.C. § 103 have been fully considered but they are not persuasive.
In particular, the Applicant argues that the limitation “the subpixel comprising a capacitor overlapping with the low-level voltage power line in a plan view” of the newly amended Claims 1, 18, and 21 are not taught by the cited prior art. The Examiner disagrees and brings the Applicants attention to Figs. 1 and 2 and Paragraph [0064] of Kim et al. (U.S. 2018/0151120), hereinafter Kim. For ease of reference, Fig. 1 and an annotated version of Fig. 2 of Kim are reproduced below.
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Kim Paragraph [0064] states that “a light-shielding reflective layer (102) [is] disposed in the non-emission area”. This is apparent in the plan view of Fig. 1, wherein the entire substrate, minus the emission area (EA) of each sub-pixel, has the layer present. While the capacitor (Cst) of Kim is a mostly in the emission area (EA), it is plainly seen in Fig. 2 that the capacitor (Cst) extends beyond it, and the layer (102) in facts overlaps both upper (144) and lower (142) electrodes of the capacitor (Cst).
Moreover, the Examiner notes that by the incorporation of the teachings of Kim (regarding the light-shielding reflective layer (102)) into the device of Choi et al. (U.S. Pub. 2017/0317158), hereinafter Choi, the limitation would be present even if the capacitor (Cst) of Kim was located exclusively in the emission area (EA). This is because in Choi the capacitor (Cst) is a majority in the non-emission area (the area not covered by the (OLED)), thus with Kim (102) being incorporated into the device of Choi, the limitation “a capacitor overlapping with the low-level voltage power line in a plan view” is necessarily present. This is apparent in the annotated version of Fig. 6 of Choi following the incorporation of the teachings of Kim (Fig. A) which was provided in the initial Office Action dated July 2, 2025. This same Fig. A will be included below.
The rejections have been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13, 16, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (U.S. Pub. 2017/0317158), hereinafter Choi, in view of Kim et al. (U.S. Pub. 2018/0151120), hereinafter Kim. For clarity, an annotated version of Fig. 6 of Choi following the incorporation of the teachings of Kim, hereinafter ‘Fig. A’, is provided below.
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Regarding Claim 1, Choi teaches a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) comprising:
-a low-level voltage power line configured to transmit a low-level voltage; ((ELVSS); Fig. 2, Paragraph [0078])
-a data line configured to transmit a data voltage ((171); Fig. 2, Paragraph [0059]);
-a gate line configured to transmit a gate signal (‘scan line’ (151); Fig. 2, Paragraphs [0051] and [0052]), and
-a subpixel ((PX); Fig. 2, Paragraph [0049]) connected to the low-level voltage power line (ELVSS), the data line (171) and the gate line (151), the subpixel comprising a capacitor ((Cst); Fig. 2, Paragraph [0067])
Choi does not further elaborate on the positioning or structure of the low-level voltage power line, nor explicitly teaches:
-a capacitor overlapping with the low-level voltage power line in a plan view.
Kim teaches a display device wherein:
- a capacitor ((Cst); Fig. 2, Paragraph [0055]) overlapping with the low-level voltage power line (‘light-shielding reflective layer’ (102) carries a base voltage or low voltage VSS, which is equivalent to ELVSS of Choi; Fig. 2, Paragraph [0075]) in a plan view (As was addressed in the Response to Arguments section above, please see Figs. 1 and 2 of Kim).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teaching of Kim into the device of Choi such that it has a capacitor overlapping with the low-level voltage power line in a plan view. The Examiner notes that this would result in (ELVSS) being formed over the substrate (Choi, (110); Fig. 6, Paragraph [130]) in the pixel area as shown in the annotated Fig. A above. This would be motivated by the fact doing so would increase functionality by enabling the display to use a mirror mode (Kim, Paragraph [0064])
Regarding Claim 2, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, wherein:
-the subpixel (Choi, (PX)) further comprises a driving transistor (Choi, (T1); Fig. A, Paragraph [0068]) having a gate electrode (Choi, (155a1) the bottom portion of (155a); Fig. A, Paragraph [0104]) connected to a first electrode of the capacitor (Choi, (155a2) the top portion of (155a); Fig. A, Paragraph [0113]); and the driving transistor ((T1)) overlaps with the low-level voltage power line ((ELVSS) as in Fig. A).
Regarding Claim 3, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 2, wherein:
- the first electrode (Choi, (155a2)) and a second electrode (Choi, (178); Fig. A, Paragraph [0113]); of the capacitor (Cst) overlap with the low-level voltage power line ((ELVSS) as in Fig. A); and
-the gate electrode (Choi, (155a1)) and a channel region (Choi, (131a); Fig. A, Paragraph [0099]) of the driving transistor (T1) overlap with the low-level voltage power line ((ELVSS) as in Fig. A).
Regarding Claim 4, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 2, wherein:
- the subpixel (Choi, (PX)) further comprises a switching transistor (Choi, (T2); Fig. A, Paragraph [0068])) configured to transmit the data voltage to the gate electrode of the driving transistor and to the first electrode of the capacitor (Choi, Fig. 2, Paragraph [0071]); and the switching transistor (T2) overlaps with the gate line ((ELVSS) as in Fig. A).
Regarding Claim 5, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 4, wherein:
- the switching transistor (T2) has:
a gate electrode (Choi, (G2); Fig. 2, Paragraph [0071]) connected to the gate line (Choi, (151));
a first electrode (Choi, (S2); Fig. 2, Paragraph [0071]) connected to the data line (Choi, (171)); and
a second electrode (Choi, (D2); Fig. 2, Paragraph [0071]) connected to the gate electrode of the driving transistor (Choi, (155a1) also labeled (G1) in Fig. 2, Paragraph [0070]) and to the first electrode of the capacitor (Choi, (155a2) also labeled (Cst1) in Fig. 2, Paragraph [0070]).
Regarding Claim 6, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 2, wherein:
- the low-level voltage power line (ELVSS) extends in a first direction in a plane of the light emitting display device (e.g. along (Dr2) in Fig. 4 of Choi); and the gate line (Choi, (151)) extends in a second direction (e.g. along (Dr1) in Fig. 4 of Choi) which crosses the first direction and is parallel to the plane of the light emitting display device (As in Fig. 4 of Choi).
Regarding Claim 7, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 6, wherein:
-the capacitor (Choi, (Cst)) and the driving transistor (Choi, (T1)) are arranged along the first direction (Choi, (Dr2)) and each overlaps with the low-level voltage power line (ELVSS).
Regarding Claim 8, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 6, wherein:
-the subpixel (Choi, (PX)) further comprises an organic light emitting diode (Choi, (OLED); Fig. 2, Paragraph [0067]); and the organic light emitting diode (Choi, (OLED)) is located between the low-level voltage power line ((ELVSS), for example the portion on the right of Fig. A) and the data line (Choi, (171)) in plan view (This is understood being between the selected portion of ELVSS and (171) as in Fig. A, which if looking down in the plan view fulfills the limitation).
Regarding Claim 9, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, wherein:
-the subpixel (Choi, (PX)) comprises:
-a buffer layer (Choi, (120); Fig. A, Paragraph [0130]) disposed on the low-level voltage power line (ELVSS);
-a semiconductor layer (Choi, (130); Fig. A, Paragraph [0131]) disposed on the buffer layer (Choi, (120));
-a gate insulating layer (Choi, (160); Fig. A, Paragraph [0134]) disposed on the semiconductor layer (Choi, (130));
-a gate metal layer (Choi, (174); Fig. 7, Paragraph [104]) disposed on the gate insulating layer (Choi, (130);
-an interlayer of an insulating material (Choi, (180); Fig. 7, Paragraph [0141]) disposed on the gate metal layer (Choi, (174); and
-a pixel electrode layer (Choi, (191); Fig. A, Paragraph [0142]) disposed on the interlayer (Choi, (180)).
Regarding Claim 10, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 9, wherein:
- the semiconductor layer (Choi, (130) is selected as an oxide semiconductor (Choi, Paragraph [0098]) comprising a semiconductor region (Choi, ‘channel region’ comprising portions (131a), (131b), … (131g); Fig. A, Paragraph [0100]) and a metallized region (Choi, ‘conductive region’ of (130); Fig. A, Paragraph [0100]); and
-the semiconductor layer further comprises a metal layer (Choi, ‘connection member’ (179); Fig. A, Paragraph [0135]) disposed in the metallized region (e.g. the rightmost portion of (130); Fig. A).
Regarding Claim 11, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 10, wherein:
- the pixel electrode layer (Choi, (191)) contacts a portion of the metal layer (Choi, (179)) via a contact hole (Choi, comprising portions (81) and (66); Fig. A) provided at the interlayer (Choi, (180)) and the gate insulating layer (Choi, (160)), thereby being electrically connected to the metallized region (Choi, [0142]).
Regarding Claim 12, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 10, wherein:
the pixel electrode layer (Choi, (191)) is directly connected to the metallized region (e.g. the rightmost region of (130), Fig. A) via a contact hole (Choi, (81) and (66)) provided at the interlayer (Choi, (180)) and the gate insulating layer (Choi, (160)). (Examiner notes that as specified in the limitation of Claim 10, “the semiconductor layer further comprises a metal layer disposed in the metallized region” the metal layer is considered an element of the metallized region, thus by directly contacting the metal layer, the pixel electrode layer is “directly connected” to the metallized region).
Regarding Claim 13, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 8, wherein:
- the subpixel (Choi, (PX)) further comprises a compensation transistor (Choi, (T3); Fig. 2, Paragraph [0068]) configured to apply a compensation voltage (Choi, Paragraph [0072]) to the organic light emitting diode (Choi, (OLED)); and the compensation transistor overlaps with the gate line (Choi, (151)) (As in Fig. 4 of Choi).
Regarding Claim 16, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, wherein:
-the capacitor (Choi, (Cst) comprises a first electrode (Choi, (155a2) the top portion of (155a); Fig. A, Paragraph [0113]) disposed on a buffer layer (Choi, (120); Fig. A, Paragraph [0130]) covering the low-level voltage power line (ELVSS), and
-a second electrode (Choi, (178); Fig. A, Paragraph [0113]) disposed on a gate insulating layer (Choi, (160); Fig. A, Paragraph [0134]) covering the first electrode (Choi, (155a2)), and
-wherein the first electrode of the capacitor (Choi, (155a2)) comprises a metal (Choi, Paragraph [0132])
Choi as initially modified by Kim does not teach:
-the first electrode of the capacitor comprises a metallized oxide semiconductor layer.
-Kim further teaches:
- the first electrode of the capacitor (‘lower electrode’ (142); Fig. 2, Paragraphs [0053] and [0054]) comprises a metallized oxide semiconductor layer (Paragraph [0049])
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to modify the device of Choi and Kim by the further teachings of Kim such that the first electrode of the capacitor comprises a metallized oxide semiconductor layer. This is because to do so would produce a predictable result of having a first electrode made of a metallized oxide semiconductor rather than metal, which are equivalents in this context (acting as an electrode for a capacitor).
Regarding Claim 21, Choi teaches a manufacturing method of a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) comprising:
-forming a subpixel ((PX); Fig. 2, Paragraph [0049]) connected to a low-level voltage power line ((ELVSS); Fig. 2, Paragraph [0078]), a data line ((171); Fig. 2, Paragraph [0059]), a capacitor ((Cst); Fig. 2, Paragraph [0067]), and a gate line (‘scan line’ (151); Fig. 2, Paragraphs [0051] and [0052]); and
-encapsulating the subpixel formed on a substrate (Paragraph [0147])
Choi does not teach:
-wherein the capacitor has at least one electrode overlapping with the low-level voltage power line in a plan view.
Kim teaches a manufacturing method for a display device wherein:
-a capacitor ((Cst); Fig. 2, Paragraph [0055]) has at least one electrode (‘lower electrode’ (142); Fig. 2, Paragraphs [0053] and [0054]) overlapping with the low-level voltage power line (‘light-shielding reflective layer’ (102) carries a base voltage or low voltage VSS, which is equivalent to ELVSS of Choi; Fig. 2, Paragraph [0075]) in a plan view. (As was addressed in the Response to Arguments section above, please see Figs. 1 and 2 of Kim).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teaching of Kim into the method of manufacturing a device of Choi such that it the capacitor has at least one electrode overlapping with the low-level voltage power line in a plan view. This would be motivated by the fact doing so would increase functionality by enabling the display to use a mirror mode (Kim, Paragraph [0064])
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Kim, as supported by Takasugi et al. (U.S. Pub. 2010/0103081), hereinafter Takasugi.
Regarding Claim 14, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 13, wherein:
the compensation transistor (Choi, (T3)) has:
a gate (Choi, (G3); Fig. 2, Paragraph [0072]) connected to the gate line (Choi, (151));
a first electrode (Choi, (S3); Fig. 2, Paragraph [0072]) connected to an anode of the organic light emitting diode (Choi, (OLED)) and a first electrode (Choi, (D1); Fig. 2, Paragraph [0072]) of the driving transistor (Choi, (T1)); and
a second electrode (Choi, (D3); Fig. 2, Paragraph [0072]) connected to a compensation line (initialization voltage line (192) via initialization transistor (T4); Fig. 2, Paragraphs [0072] and [0073]).
Choi as modified by Kim does not teach:
-a first electrode connected to a cathode of the organic light emitting diode
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to modify the electrical connections of the light emitting display device of Choi as modified by Kim such that a compensation transistor has a first electrode connected to a cathode of the organic light emitting diode. This is because such a modification requires a switch of the voltage sources as they relate to the cathode and anode of the OLED and fundamentally is a design choice when designing the circuit. For example, for Choi, the anode of the OLED would need to now be connected to ELVDD, but then the cathode of the OLED would connect to a first electrode of the compensation transistor. This concept is well known in the art. For an example of this design, please see Takasugi, Fig. 1, Paragraph [0144].
Regarding Claim 15, Choi as modified by Kim and informed by Takasugi teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 14, wherein:
- the compensation line (Choi, (192)) is adjacent to the data line (Choi, (171)) (As clearly seen in Fig. A) and extends in the first direction (Choi, (Dr2))
Claims 17-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Kim, in further view of Winters (U.S. Patent 6771028), hereinafter Winters.
Regarding Claim 17, Choi as modified by Kim teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, comprising:
-a plurality of subpixels (Choi, (PX); Fig. 1, Paragraph [0049]), wherein each subpixel is connected to the low-level voltage power line (ELVSS), the data line (Choi, (171)) and the gate line (Choi, (151)), and wherein each subpixel comprises a capacitor (Choi, Cst) overlapping with the low-level voltage power line (ELVSS); (Choi, Paragraph [0050]) and
-a driver (Choi, e.g. ‘first driver’ (200); Fig. 1, Paragraph [0048]) configured to drive a display panel (Choi, (100); Fig. 1, Paragraph [0048]),
Neither Choi nor Kim teach:
-wherein the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group.
Winters teaches a light emitting display device wherein:
-wherein the subpixels (of a pixel (20); Fig. 1, Col. 3, Lines 44-47) comprise a first group (comprising a first subpixel (20a) and a second subpixel (20b); Fig. 1, Col. 3, Lines 47-52) and a second group (comprising a third subpixel (20c) and a fourth subpixel (20d); Fig. 1, Col. 3, Lines 47-52), wherein each group comprises two subpixels laterally symmetrical with each other ((20a) in relation to (20b) and (20c) in relation to (20d); Fig. 1), and wherein the subpixels of the first group ((20a) and (20b) are inverted relative to the subpixels of the second group ((20c) and (20d)) (See Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teachings of Winters into the light emitting display device of Choi as modified by Kim such that the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group. This is because doing so would reduce the surface area of circuit components and connections, thereby leading to an improved aperture ratio or a greater possible number of pixels per unit area (Winters, ‘Advantages’ section, Col. 2, Lines 46-52)
Regarding Claim 18, Choi teaches a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) comprising:
-a display panel ((100); Fig. 1, Paragraph [0048]), comprising subpixels ((PX); Fig. 1, Paragraph [0049]) each connected to a low-level voltage power line ((ELVSS); Fig. 2, Paragraph [0078]), a data line ((171); Fig. 2, Paragraph [0059]), and a gate line (‘scan line’ (151); Fig. 2, Paragraphs [0051] and [0052]),
-each of the subpixels comprising a capacitor ((Cst); Fig. 2, Paragraph [0067])
-a driver (e.g. ‘first driver’ (200); Fig. 1, Paragraph [0048]) configured to drive the display panel (100),
Choi does not further elaborate on the positioning or structure of the low-level voltage power line, nor explicitly teaches:
-a capacitor overlapping with the low-level voltage power line in a plan view.
Kim teaches a display device wherein:
- a capacitor ((Cst); Fig. 2, Paragraph [0055]) overlapping with the low-level voltage power line (‘light-shielding reflective layer’ (102) carries a base voltage or low voltage VSS, which is equivalent to ELVSS of Choi; Fig. 2, Paragraph [0075]) in a plan view. (As was addressed in the Response to Arguments section above, please see Figs. 1 and 2 of Kim).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teaching of Kim into the device of Choi such that it has a capacitor overlapping with the low-level voltage power line in a plan view. The Examiner notes that this would result in (ELVSS) being formed over the substrate (Choi, (110); Fig. 6, Paragraph [130]) in the pixel area as shown in the annotated Fig. A above. This would be motivated by the fact doing so would increase functionality by enabling the display to use a mirror mode (Kim, Paragraph [0064])
Neither Choi nor Kim teach:
-wherein the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group.
Winters teaches a light emitting display device wherein:
-wherein the subpixels (of a pixel (20); Fig. 1, Col. 3, Lines 44-47) comprise a first group (comprising a first subpixel (20a) and a second subpixel (20b); Fig. 1, Col. 3, Lines 47-52) and a second group (comprising a third subpixel (20c) and a fourth subpixel (20d); Fig. 1, Col. 3, Lines 47-52), wherein each group comprises two subpixels laterally symmetrical with each other ((20a) in relation to (20b) and (20c) in relation to (20d); Fig. 1), and wherein the subpixels of the first group ((20a) and (20b) are inverted relative to the subpixels of the second group ((20c) and (20d)) (See Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teachings of Winters into the light emitting display device of Choi as modified by Kim such that the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group. This is because doing so would reduce the surface area of circuit components and connections, thereby leading to an improved aperture ratio or a greater possible number of pixels per unit area (Winters, ‘Advantages’ section, Col. 2, Lines 46-52)
Regarding Claim 19, Choi as modified by Kim and Winters teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 18, wherein:
-each subpixel (Choi, (PX)) comprises a driving transistor (Choi, (T1); Fig. A, Paragraph [0068]) having a gate electrode (Choi, (155a1) the bottom portion of (155a); Fig. A, Paragraph [0104]) connected to a first electrode of the capacitor (Choi, (155a2) the top portion of (155a); Fig. A, Paragraph [0113]);
-the first electrode (Choi, (155a2)) and a second electrode (Choi, (178); Fig. A, Paragraph [0113]); of each capacitor (Cst) overlap with the low-level voltage power line ((ELVSS) as in Fig. A); and
-the gate electrode (Choi, (155a1)) and a channel region (Choi, (131a); Fig. A, Paragraph [0099]) of each driving transistor (T1) overlap with the low-level voltage power line ((ELVSS) as in Fig. A).
Regarding Claim 20, Choi as modified by Kim and Winters teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 18, wherein:
- a first subpixel (Choi, e.g. the (PX) on the left of Fig. 4) includes a first capacitor (Choi, e.g. the left (Cst) of Fig. 4) and a second subpixel (Choi, e.g. the (PX) on the right of Fig. 4) includes a second capacitor (Choi, e.g. the right (Cst) of Fig. 4), each of the first and second capacitors overlapping with the low-level voltage power line corresponding thereto ((ELVSS), as would be present with the incorporation of Kim into Choi), the first (Choi, left (PX) of Fig. 4) and second (Choi, right (PX) of Fig. 4) subpixels adjacent to each other and the first (Choi, left (Cst) of Fig. 4) and second capacitors (Choi, right (Cst) of Fig. 4) adjacent to each other.
Regarding Claim 22, Choi as modified by Kim teaches a manufacturing method of a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) of Claim 21, comprising:
-forming a display panel (Choi, (100); Fig. 1, Paragraph [0048]) that include a plurality of subpixels including the subpixel (Choi, (PX); Fig. 1, Paragraph [0049]); and
-forming a driver (Choi, e.g. ‘first driver’ (200); Fig. 1, Paragraph [0048]) configured to drive the display panel (Choi, (100))
Neither Choi nor Kim teach:
-the plurality of subpixels that comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group.
Winters teaches a method of manufacturing a light emitting display device wherein:
-wherein the plurality of subpixels (of a pixel (20); Fig. 1, Col. 3, Lines 44-47) that comprise a first group (comprising a first subpixel (20a) and a second subpixel (20b); Fig. 1, Col. 3, Lines 47-52) and a second group (comprising a third subpixel (20c) and a fourth subpixel (20d); Fig. 1, Col. 3, Lines 47-52), wherein each group comprises two subpixels laterally symmetrical with each other ((20a) in relation to (20b) and (20c) in relation to (20d); Fig. 1), and wherein the subpixels of the first group ((20a) and (20b) are inverted relative to the subpixels of the second group ((20c) and (20d)) (See Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teachings of Winters into the method of manufacturing a light emitting display device of Choi as modified by Kim such that it comprises the plurality of subpixels that comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group. This is because doing so would reduce the surface area of circuit components and connections, thereby leading to an improved aperture ratio or a greater possible number of pixels per unit area (Winters, ‘Advantages’ section, Col. 2, Lines 46-52)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.M./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812