Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 14, 2026 has been entered.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-6 and 8-22 are pending.
-Claim 7 is cancelled.
-Claims 1-2, 6, and 21 are amended.
Response to Arguments/Amendments
Applicant's arguments filed April 14, 2026 have been fully considered. In regards to the argument against the incorporation of the teachings of Kim (U.S. Pub. 2018/0151120) into the device of Choi (U.S. Pub. 20170317158), as it relates to a top emission vs bottom emission device, the argument is persuasive.
In regards to the argument that Winters (U.S. Patent 6,771,028) does not teach the pixel groups are laterally symmetrical, the argument is not persuasive and the Examiner disagrees. In particular, the Applicant seems to be referencing bilateral symmetry, but the claim limitation of laterally symmetrical is not as restrictive in terms of the structure referenced. That said, to advance prosecution, Examiner will reference Winters Fig. 4 as to the type of symmetry the Applicant seems to be referring to in the reply.
The rejection has been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (U.S. Pub. 2017/0317158), hereinafter Choi, in view of Yoon (U.S. Pub. 2015/0187959), hereinafter Yoon. For clarity, an annotated version of Fig. 6 of Choi following the incorporation of the teachings of Yoon, hereinafter ‘Fig. A_1’, is provided below.
PNG
media_image1.png
713
957
media_image1.png
Greyscale
Regarding Claim 1, Choi teaches a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) comprising:
-a low-level voltage power line configured to transmit a low-level voltage; ((ELVSS); Fig. 2, Paragraph [0078])
-a data line configured to transmit a data voltage ((171); Figs. 2 and 4, Paragraph [0059]);
-a gate line configured to transmit a gate signal (‘scan line’ (151); Figs. 2 and 4, Paragraphs [0051] and [0052]), and
-a subpixel ((PX); Fig. 2, Paragraph [0049]) connected to the low-level voltage power line (ELVSS), the data line (171) and the gate line (151), the subpixel comprising a capacitor ((Cst); Fig. 2, Paragraph [0067]) and a driving transistor ((T1); Fig. A, Paragraph [0068]),
-wherein both of the capacitor (Cst) and the driving transistor (T1) overlap in the plan view (Fig. 4 and vertically in Fig. 6), and
-wherein both the capacitor (Cst) and the driving transistor (T1) are disposed along a first direction (e.g. (Dr2)) parallel to a direction in which the data line (171) extend, in the plan view (Fig. 4).
Choi does not further elaborate on the positioning or structure of the low-level voltage power line, nor explicitly teaches:
-a data line disposed parallel to the low-voltage power line in a plan view.
-both of the capacitor and the driving transistor overlap with the low-level voltage power line.
-both of the capacitor and the driving transistor are disposed along a first direction parallel to a direction in which the low-voltage power line.
Yoon teaches a display device (Figs. 2 and 3, Paragraphs [0027] and [0028]) wherein:
-a data line disposed parallel to the low-voltage power line (comprising (103) and (AL); Fig. 2 and 3, Paragraphs [0040], [0041], and [0071]) in a plan view (‘parallel to and spaced apart from... the data line’; Paragraph [0040]).
-the driving transistor ((Tr); Fig. 3, Paragraph [0016]) overlaps with the low-level voltage power line ((103) and (AL))
The limitations “both of the capacitor and the driving transistor overlap with the low-level voltage power line” and “both of the capacitor and the driving transistor are disposed along a first direction parallel to a direction in which the low-voltage power line” are necessarily fulfilled by the incorporation of the low-voltage power line of Yoon ((103) and (AL)) into the device of Choi. The first is due to the positioning relative to other elements, as is illustrated in Fig. A_1. The second, Yoon teaches that the low-voltage power line (specifically portion (AL)) is ‘parallel to and spaced apart from... the data line’; Paragraph [0040])- thus in incorporation, the limitation is fulfilled.
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teaching of Yoon into the device of Choi such that it has a data line disposed parallel to the low-voltage power line in a plan view, both of the capacitor and the driving transistor overlap with the low-level voltage power line, and both of the capacitor and the driving transistor are disposed along a first direction parallel to a direction in which the low-voltage power line. This would be motivated by the fact doing so would increase transistor reliability while avoiding decreasing image qualities (Yoon, Paragraphs [0019], [0022], [0072], and [0073])
Regarding Claim 2, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, wherein:
-the driving transistor (Choi, (T1); Fig. A_1, Paragraph [0068]) has a gate electrode (Choi, (155a1) the bottom portion of (155a); Fig. A_1, Paragraph [0104]) connected to a first electrode of the capacitor (Choi, (155a2) the top portion of (155a); Fig. A_1, Paragraph [0113]).
Regarding Claim 3, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 2, wherein:
- the first electrode (Choi, (155a2)) and a second electrode (Choi, (178); Fig. A_1, Paragraph [0113]); of the capacitor (Cst) overlap with the low-level voltage power line ((Shield) as in Fig. A_1); and
-the gate electrode (Choi, (155a1)) and a channel region (Choi, (131a); Fig. A, Paragraph [0099]) of the driving transistor (T1) overlap with the low-level voltage power line ((Shield) as in Fig. A).
Regarding Claim 4, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 2, wherein:
- the subpixel (Choi, (PX)) further comprises a switching transistor (Choi, (T2); Fig. A_1, Paragraph [0068])) configured to transmit the data voltage to the gate electrode of the driving transistor and to the first electrode of the capacitor (Choi, Fig. 2, Paragraph [0071]); and the switching transistor (T2) overlaps with the gate line (Choi, (151) as in Figs. A_1 and 4).
Regarding Claim 5, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 4, wherein:
- the switching transistor (T2) has:
a gate electrode (Choi, (G2); Fig. 2, Paragraph [0071]) connected to the gate line (Choi, (151));
a first electrode (Choi, (S2); Fig. 2, Paragraph [0071]) connected to the data line (Choi, (171)); and
a second electrode (Choi, (D2); Fig. 2, Paragraph [0071]) connected to the gate electrode of the driving transistor (Choi, (155a1) also labeled (G1) in Fig. 2, Paragraph [0070]) and to the first electrode of the capacitor (Choi, (155a2) also labeled (Cst1) in Fig. 2, Paragraph [0070]).
Regarding Claim 6, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 2, wherein:
- the low-level voltage power line (Choi, (Shield) / Yoon, (103) and (AL)) extends in the first direction in a plane of the light emitting display device (e.g. along (Dr2) in Fig. 4 of Choi); and the gate line (Choi, (151)) extends in a second direction (e.g. along (Dr1) in Fig. 4 of Choi) which crosses the first direction and is parallel to the plane of the light emitting display device (As in Fig. 4 of Choi).
Regarding Claim 8, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 6, wherein:
-the subpixel (Choi, (PX)) further comprises an organic light emitting diode (Choi, (OLED); Fig. 2, Paragraph [0067]); and the organic light emitting diode (Choi, (OLED)) is located between the low-level voltage power line ((Shield), for example the portion on the right of Fig. A_1) and the data line (Choi, (171)) in plan view (This is understood being between the selected portion of (Shield) and (171) as in Fig. A_1, which if looking down in the plan view fulfills the limitation).
Regarding Claim 9, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, wherein:
-the subpixel (Choi, (PX)) comprises:
-a buffer layer (Choi, (120); Fig. A_1, Paragraph [0130]) disposed on the low-level voltage power line (ELVSS);
-a semiconductor layer (Choi, (130); Fig. A_1, Paragraph [0131]) disposed on the buffer layer (Choi, (120));
-a gate insulating layer (Choi, (160); Fig. A_1, Paragraph [0134]) disposed on the semiconductor layer (Choi, (130));
-a gate metal layer (Choi, (174); Fig. 7, Paragraph [104]) disposed on the gate insulating layer (Choi, (130);
-an interlayer of an insulating material (Choi, (180); Fig. 7, Paragraph [0141]) disposed on the gate metal layer (Choi, (174); and
-a pixel electrode layer (Choi, (191); Fig. A_1, Paragraph [0142]) disposed on the interlayer (Choi, (180)).
Regarding Claim 10, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 9, wherein:
- the semiconductor layer (Choi, (130) is selected as an oxide semiconductor (Choi, Paragraph [0098]) comprising a semiconductor region (Choi, ‘channel region’ comprising portions (131a), (131b), … (131g); Fig. A_1, Paragraph [0100]) and a metallized region (Choi, ‘conductive region’ of (130); Fig. A_1, Paragraph [0100]); and
-the semiconductor layer further comprises a metal layer (Choi, ‘connection member’ (179); Fig. A_1, Paragraph [0135]) disposed in the metallized region (e.g. the rightmost portion of (130); Fig. A_1).
Regarding Claim 11, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 10, wherein:
- the pixel electrode layer (Choi, (191)) contacts a portion of the metal layer (Choi, (179)) via a contact hole (Choi, comprising portions (81) and (66); Fig. A_1) provided at the interlayer (Choi, (180)) and the gate insulating layer (Choi, (160)), thereby being electrically connected to the metallized region (Choi, [0142]).
Regarding Claim 12, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 10, wherein:
the pixel electrode layer (Choi, (191)) is directly connected to the metallized region (e.g. the rightmost region of (130), Fig. A_1) via a contact hole (Choi, (81) and (66)) provided at the interlayer (Choi, (180)) and the gate insulating layer (Choi, (160)). (Examiner notes that as specified in the limitation of Claim 10, “the semiconductor layer further comprises a metal layer disposed in the metallized region” the metal layer is considered an element of the metallized region, thus by directly contacting the metal layer, the pixel electrode layer is “directly connected” to the metallized region).
Regarding Claim 13, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 8, wherein:
- the subpixel (Choi, (PX)) further comprises a compensation transistor (Choi, (T3); Fig. 2, Paragraph [0068]) configured to apply a compensation voltage (Choi, Paragraph [0072]) to the organic light emitting diode (Choi, (OLED)); and the compensation transistor overlaps with the gate line (Choi, (151)) (As in Fig. 4 of Choi).
Regarding Claim 21, Choi teaches a manufacturing method of a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) comprising:
-forming a subpixel ((PX); Fig. 2, Paragraph [0049]) connected to a low-level voltage power line ((ELVSS); Fig. 2, Paragraph [0078]), a data line ((171); Fig. 2, Paragraph [0059]), a capacitor ((Cst); Fig. 2, Paragraph [0067]), and a gate line (‘scan line’ (151); Fig. 2, Paragraphs [0051] and [0052]);
-encapsulating the subpixel formed on a substrate (Paragraph [0147]); wherein
-the subpixel comprises a capacitor ((Cst); Fig. 2, Paragraph [0067]) and a driving transistor ((T1); Fig. A, Paragraph [0068])
-wherein both of the capacitor (Cst) and the driving transistor (T1) overlap in the plan view (Fig. 4 and vertically in Fig. 6), and
-wherein both the capacitor (Cst) and the driving transistor (T1) are disposed along a first direction (e.g. (Dr2)) parallel to a direction in which the data line (171) extend, in the plan view (Fig. 4).
Choi does not further elaborate on the positioning or structure of the low-level voltage power line, nor explicitly teaches:
-the data line is disposed parallel to the low-voltage power line in a plan view.
-both of the capacitor and the driving transistor overlap with the low-level voltage power line.
-both of the capacitor and the driving transistor are disposed along a first direction parallel to a direction in which the low-voltage power line.
Yoon teaches a manufacturing method for a display device wherein:
-a data line disposed parallel to the low-voltage power line (comprising (103) and (AL); Fig. 2 and 3, Paragraphs [0040], [0041], and [0071]) in a plan view (‘parallel to and spaced apart from... the data line’; Paragraph [0040]).
-the driving transistor ((Tr); Fig. 3, Paragraph [0016]) overlaps with the low-level voltage power line ((103) and (AL))
The limitations “both of the capacitor and the driving transistor overlap with the low-level voltage power line” and “both of the capacitor and the driving transistor are disposed along a first direction parallel to a direction in which the low-voltage power line” are necessarily fulfilled by the incorporation of the low-voltage power line of Yoon ((103) and (AL)) into the method of Choi. The first is due to the positioning relative to other elements, as is illustrated in Fig. A_1. The second, Yoon teaches that the low-voltage power line (specifically portion (AL)) is ‘parallel to and spaced apart from... the data line’; Paragraph [0040])- thus in incorporation, the limitation is fulfilled.
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teaching of Yoon into the method of Choi such that it has a data line disposed parallel to the low-voltage power line in a plan view, both of the capacitor and the driving transistor overlap with the low-level voltage power line, and both of the capacitor and the driving transistor are disposed along a first direction parallel to a direction in which the low-voltage power line. This would be motivated by the fact doing so would result in a methodology with increased transistor reliability while avoiding decreasing image qualities (Yoon, Paragraphs [0019], [0022], [0072], and [0073])
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Yoon, as supported by Takasugi et al. (U.S. Pub. 2010/0103081), hereinafter Takasugi.
Regarding Claim 14, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 13, wherein:
the compensation transistor (Choi, (T3)) has:
a gate (Choi, (G3); Fig. 2, Paragraph [0072]) connected to the gate line (Choi, (151));
a first electrode (Choi, (S3); Fig. 2, Paragraph [0072]) connected to an anode of the organic light emitting diode (Choi, (OLED)) and a first electrode (Choi, (D1); Fig. 2, Paragraph [0072]) of the driving transistor (Choi, (T1)); and
a second electrode (Choi, (D3); Fig. 2, Paragraph [0072]) connected to a compensation line (initialization voltage line (192) via initialization transistor (T4); Fig. 2, Paragraphs [0072] and [0073]).
Choi as modified by Yoon does not teach:
-a first electrode connected to a cathode of the organic light emitting diode
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to modify the electrical connections of the light emitting display device of Choi as modified by Yoon such that a compensation transistor has a first electrode connected to a cathode of the organic light emitting diode. This is because such a modification requires a switch of the voltage sources as they relate to the cathode and anode of the OLED and fundamentally is a design choice when designing the circuit. For example, for Choi, the anode of the OLED would need to now be connected to ELVDD, but then the cathode of the OLED would connect to a first electrode of the compensation transistor. This concept is well known in the art. For an example of this design, please see Takasugi, Fig. 1, Paragraph [0144].
Regarding Claim 15, Choi as modified by Yoon and informed by Takasugi teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 14, wherein:
- the compensation line (Choi, (192)) is adjacent to the data line (Choi, (171)) (As clearly seen in Fig. A) and extends in the first direction (Choi, (Dr2))
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi and Yoon, in view of Kim et al. (U.S. Pub. 2018/0151120), hereinafter Kim.
Regarding Claim 16, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, wherein:
-the capacitor (Choi, (Cst) comprises a first electrode (Choi, (155a2) the top portion of (155a); Fig. A_1, Paragraph [0113]) disposed on a buffer layer (Choi, (120); Fig. A_1, Paragraph [0130]) covering the low-level voltage power line (Shield), and
-a second electrode (Choi, (178); Fig. A_1, Paragraph [0113]) disposed on a gate insulating layer (Choi, (160); Fig. A_1, Paragraph [0134]) covering the first electrode (Choi, (155a2)), and
-wherein the first electrode of the capacitor (Choi, (155a2)) comprises a metal (Choi, Paragraph [0132])
Choi and Yoon do not teach:
-the first electrode of the capacitor comprises a metallized oxide semiconductor layer.
-Kim teaches:
- the first electrode of the capacitor (‘lower electrode’ (142); Fig. 2, Paragraphs [0053] and [0054]) comprises a metallized oxide semiconductor layer (Paragraph [0049])
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to modify the device of Choi and Yoon by the teachings of Kim such that the first electrode of the capacitor comprises a metallized oxide semiconductor layer. This is because to do so would produce a predictable result of having a first electrode made of a metallized oxide semiconductor rather than metal, which are equivalents in this context (acting as an electrode for a capacitor).
Claims 17-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Yoon, in further view of Winters (U.S. Patent 6771028), hereinafter Winters.
Regarding Claim 17, Choi as modified by Yoon teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 1, comprising:
-a plurality of subpixels (Choi, (PX); Fig. 1, Paragraph [0049]), wherein each subpixel is connected to the low-level voltage power line (ELVSS), the data line (Choi, (171)) and the gate line (Choi, (151)), and wherein each subpixel comprises a capacitor (Choi, Cst) overlapping with the low-level voltage power line (ELVSS); (Choi, Paragraph [0050]) and
-a driver (Choi, e.g. ‘first driver’ (200); Fig. 1, Paragraph [0048]) configured to drive a display panel (Choi, (100); Fig. 1, Paragraph [0048]),
Neither Choi nor Yoon teach:
-wherein the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group.
Winters teaches a light emitting display device wherein:
-wherein the subpixels (of a pixel (20); Fig. 4, Col. 3, Lines 44-47) comprise a first group (comprising a first subpixel (20a) and a second subpixel (20b); Fig. 4, Col. 3, Lines 47-52) and a second group (comprising a third subpixel (20c) and a fourth subpixel (20d); Fig. 4, Col. 3, Lines 47-52), wherein each group comprises two subpixels laterally symmetrical with each other ((20a) in relation to (20b) and (20c) in relation to (20d); Fig. 4), and wherein the subpixels of the first group ((20a) and (20b) are inverted relative to the subpixels of the second group ((20c) and (20d)) (See Fig. 4).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teachings of Winters into the light emitting display device of Choi as modified by Kim such that the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group. This is because doing so would reduce the surface area of circuit components and connections, thereby leading to an improved aperture ratio or a greater possible number of pixels per unit area (Winters, ‘Advantages’ section, Col. 2, Lines 46-52)
Regarding Claim 18, Choi teaches a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) comprising:
-a display panel ((100); Fig. 1, Paragraph [0048]), comprising subpixels ((PX); Fig. 1, Paragraph [0049]) each connected to a low-level voltage power line ((ELVSS); Fig. 2, Paragraph [0078]), a data line ((171); Fig. 2, Paragraph [0059]), and a gate line (‘scan line’ (151); Fig. 2, Paragraphs [0051] and [0052]),
-each of the subpixels comprising a capacitor ((Cst); Fig. 2, Paragraph [0067])
-a driver (e.g. ‘first driver’ (200); Fig. 1, Paragraph [0048]) configured to drive the display panel (100),
Choi does not further elaborate on the positioning or structure of the low-level voltage power line, nor explicitly teaches:
-a capacitor overlapping with the low-level voltage power line in a plan view.
Yoon teaches a display device wherein:
-the driving transistor ((Tr); Fig. 3, Paragraph [0016]) overlaps with the low-level voltage power line (comprising (103) and (AL); Fig. 2 and 3, Paragraphs [0040], [0041], and [0071])
The limitation “a capacitor overlapping with the low-level voltage power line in a plan view.” is necessarily fulfilled by the incorporation of the low-voltage power line of Yoon ((103) and (AL)) into the device of Choi. This is due to the positioning relative to other elements, as is illustrated in Fig. A_1.
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teaching of Yoon into the device of Choi such that it a capacitor overlapping with the low-level voltage power line in a plan view. This would be motivated by the fact doing so would increase transistor reliability while avoiding decreasing image qualities (Yoon, Paragraphs [0019], [0022], [0072], and [0073])
Neither Choi nor Yoon teach:
-wherein the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group.
Winters teaches a light emitting display device wherein:
-wherein the subpixels (of a pixel (20); Fig. 4, Col. 3, Lines 44-47) comprise a first group (comprising a first subpixel (20a) and a second subpixel (20b); Fig. 4, Col. 3, Lines 47-52) and a second group (comprising a third subpixel (20c) and a fourth subpixel (20d); Fig. 4, Col. 3, Lines 47-52), wherein each group comprises two subpixels laterally symmetrical with each other ((20a) in relation to (20b) and (20c) in relation to (20d); Fig. 4), and wherein the subpixels of the first group ((20a) and (20b) are inverted relative to the subpixels of the second group ((20c) and (20d)) (See Fig. 4).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teachings of Winters into the light emitting display device of Choi as modified by Yoon such that the subpixels comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group. This is because doing so would reduce the surface area of circuit components and connections, thereby leading to an improved aperture ratio or a greater possible number of pixels per unit area (Winters, ‘Advantages’ section, Col. 2, Lines 46-52)
Regarding Claim 19, Choi as modified by Yoon and Winters teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 18, wherein:
-each subpixel (Choi, (PX)) comprises a driving transistor (Choi, (T1); Fig. A_1, Paragraph [0068]) having a gate electrode (Choi, (155a1) the bottom portion of (155a); Fig. A_1, Paragraph [0104]) connected to a first electrode of the capacitor (Choi, (155a2) the top portion of (155a); Fig. A_1, Paragraph [0113]);
-the first electrode (Choi, (155a2)) and a second electrode (Choi, (178); Fig. A_1, Paragraph [0113]); of each capacitor (Cst) overlap with the low-level voltage power line ((Shield) as in Fig. A_1); and
-the gate electrode (Choi, (155a1)) and a channel region (Choi, (131a); Fig. A_1, Paragraph [0099]) of each driving transistor (T1) overlap with the low-level voltage power line ((Shield) as in Fig. A_1).
Regarding Claim 20, Choi as modified by Yoon and Winters teaches the light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) according to claim 18, wherein:
- a first subpixel (Choi, e.g. the (PX) on the left of Fig. 4) includes a first capacitor (Choi, e.g. the left (Cst) of Fig. 4) and a second subpixel (Choi, e.g. the (PX) on the right of Fig. 4) includes a second capacitor (Choi, e.g. the right (Cst) of Fig. 4), each of the first and second capacitors overlapping with the low-level voltage power line corresponding thereto ((Shield), as would be present with the incorporation of Kim into Choi), the first (Choi, left (PX) of Fig. 4) and second (Choi, right (PX) of Fig. 4) subpixels adjacent to each other and the first (Choi, left (Cst) of Fig. 4) and second capacitors (Choi, right (Cst) of Fig. 4) adjacent to each other.
Regarding Claim 22, Choi as modified by Yoon teaches a manufacturing method of a light emitting display device ((1); of an exemplary embodiment, Figs. 1-11, Paragraph [0048]) of Claim 21, comprising:
-forming a display panel (Choi, (100); Fig. 1, Paragraph [0048]) that include a plurality of subpixels including the subpixel (Choi, (PX); Fig. 1, Paragraph [0049]); and
-forming a driver (Choi, e.g. ‘first driver’ (200); Fig. 1, Paragraph [0048]) configured to drive the display panel (Choi, (100))
Neither Choi nor Yoon teach:
-the plurality of subpixels that comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group.
Winters teaches a method of manufacturing a light emitting display device wherein:
-wherein the plurality of subpixels (of a pixel (20); Fig. 4, Col. 3, Lines 44-47) that comprise a first group (comprising a first subpixel (20a) and a second subpixel (20b); Fig. 4, Col. 3, Lines 47-52) and a second group (comprising a third subpixel (20c) and a fourth subpixel (20d); Fig. 4, Col. 3, Lines 47-52), wherein each group comprises two subpixels laterally symmetrical with each other ((20a) in relation to (20b) and (20c) in relation to (20d); Fig. 4), and wherein the subpixels of the first group ((20a) and (20b) are inverted relative to the subpixels of the second group ((20c) and (20d)) (See Fig. 4).
It would have been obvious to one of ordinary skill in the art at the time the claims were
effectively filed to incorporate the teachings of Winters into the method of manufacturing a light emitting display device of Choi as modified by Yoon such that it comprises the plurality of subpixels that comprise a first group and a second group, wherein each group comprises two subpixels laterally symmetrical with each other, and wherein the subpixels of the first group are inverted relative to the subpixels of the second group. This is because doing so would reduce the surface area of circuit components and connections, thereby leading to an improved aperture ratio or a greater possible number of pixels per unit area (Winters, ‘Advantages’ section, Col. 2, Lines 46-52)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DMITRI MIHALIOV/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights