Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/5/2026 has been entered.
Response to Arguments
Applicant's arguments directed to the newly amened claims filed 4/27/2026 have been fully considered but they are not persuasive.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 & 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tung (US 20160079173 A1).
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CLAIM 1. Tung discloses a semiconductor structure comprising:
a first level of interconnect wiring 22; and
a second level of interconnect wiring 34+36+38 comprising:
a bilayer metal (i.e. metal lines are commonly known to be “bilayer”, as secondary layers 34/38 are commonly used for barrier, adhesion, etc to provide known benefits. The Ta, Ti, TaN, TiN, CuMn, CoW, Co, or CoWP barrier layer in combination with the primary conductive material form a bilayer structure. ¶15, 18 ) arrangement comprising a first metal layer 34 or 36 (e.g. Ta 34 or Cu metal line 36– fig. 6) and a second metal layer 36 or 38 on top of the first metal layer, wherein the bilayer metal arrangement incorporating via elements (Plug/via/wiring/interconnect/pad/damascene), as a first layer and trench elements as a second layer that is disused directly above the first layer (Tung fig. 6), and
cap dielectric material 40 (¶19) wrapping around the fist metal layer, wherein the the second level of interconnect wiring electrically connected to the first level of interconnect wiring (Tung fig. 6).
CLAIM 8. Tung disclose a semiconductor structure comprising:
a first level 22 of interconnect wiring (Tung fig. 6); and
a second level 36 of interconnect wiring (Tung fig. 6) comprising:
a bilayer metal 34+36+38 arrangement comprising a first metal layer 34 or 36 and a second metal layer 36 or 38 on top of the first metal layer, and wherein the bilayer metal arrangement incorporating via elements (Fig. 6) and a cap dielectric material 40 disposed directly above the via elements, the cap dielectric material 40 having lateral edges that extend beyond a width of the via elements, and the cap dielectric material wrapping around the first metal layer, wherein the second level 22 of interconnect wiring electrically connected to the first level 36 of interconnect wiring (Tung fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-7, 9, 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung (US 20160079173 A1) in view of Kang et al. (US 20230019790 A1).
CLAIM 2. Tung disclose a semiconductor structure of claim 1, however may not explicitly depict wherein the bilayer metal arrangement of the second level of interconnect wiring includes a first row of bilayer metals and a second row of bilayer metals disposed over the first row of bilayer metals. It is at least obvious if not implicitly understood, a second level may include a second or more rows. Wiring layers are understood in the art to be complex and include numerous rows and shapes. For support see Kang et al. figure 15 below.
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A person of ordinary skill in the art (POSITA), upon reviewing Kang et al., would have found it obvious to modify the structures of Tung to include varying patterns or numbers of rows in the metal levels because these are recognized in the art as mere design choices or routine optimizations. The prior art (Kang et al. and Tung collectively shows that integrated circuits can be fabricated with various metal layer configurations. MPEP § 2144.04 provides guidance that such modifications are considered obvious if the general conditions are disclosed in the prior art and the selection involves only routine experimentation to find the optimal or workable parameters, such as specific dimensions or arrangements, without producing unexpected results or a different function. Therefore, a POSITA would have been motivated to implement different numbers of rows as a straightforward matter of design discretion to achieve desired performance characteristics (e.g., routing, density, speed, power consumption) without any undue experimentation or inventive effort.
CLAIM 3. Tung in view of Kang et al. disclose a semiconductor structure of claim 2, wherein the second row of bilayer metals directly contacts the first row of bilayer metals (Tung Fig. 6 & Kang fig. 15- Note: the language does not exclude the use of the via for a direct electrical contact as understood from the language of the parent claim. ).
CLAIM 4. Tung in view of Kang et al. disclose a semiconductor structure of claim 2, wherein spacers are formed adjacent the first row of bilayer metals (Tung Fig. 6 – Metal lines/vias may have adjacent sidewall spacers, as the dielectric material directly adjacent the conductive structures spaces any adjacent conductive structures as demonstrated in Kang Fig. 15.).
CLAIM 5. Tung in view of Kang et al. disclose a semiconductor structure of claim 2, Tung. is silent upon wherein a first metal layer of the first and second rows of bilayer metals includes ruthenium (Ru), however Kang et al. teaches Ru is a known metal for the purpose, and further is commonly used with the same barrier layer material (Ti/TaN) as used in Tung. As such, Ru would be a obvious material for selection in the device of Tung as a functional equivalent known for the purpose. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select RU, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
CLAIM 6. Tung in view of Kang et al. disclose a semiconductor structure of claim 5, wherein a second metal layer of the first and second rows of bilayer metals includes tantalum nitride (TaN) or titanium nitride (TiN) (Both Tung and Kang et al. TaN and TiN [Ti/TaN] are a conventional barrier metal used when forming metallization levels in semiconductor devices.).
CLAIM 7. Tung in view of Kang et al. disclose a semiconductor structure of claim 1, wherein the first level of interconnect wiring has a first pattern and the second level of interconnect wiring has a second pattern, the first and second patterns being different from each other (Tung fig. 6 and Kang et al. fig. 15 – Both references depict “different” patterns. Further, a simple change in the shape or patterning of features constitutes an obvious modification for a person of ordinary skill in the art (POSITA), provided no unexpected results are achieved. MPEP § 2144.04 guidance supports this, stating that routine modifications like altering the shape or proportions of a prior art device are considered obvious design choices unless they produce a new or unexpected function or benefit not previously disclosed.)
CLAIM 9. Tung. in view of Kang et al. disclose a semiconductor structure of claim 8, wherein the cap dielectric material isolates a first bilayer metal from a second bilayer metal (Tung fig. 6 – The dielectric cap 18 on the lower level in the cross sectional view is located between the upper bilayer and lower bilayer thus meets the implied structure of the functional language of the claim. Additionally, should there be adjacent wiring levels as demonstrated in Kang, the upper dielectric cap 40 would be recognized to separate and isolate adjacent metallization structures.).
CLAIM 11. Tung in view of Kang et al. disclose a semiconductor structure of claim 8, wherein spacers are formed adjacent a first metal layer and a second metal layer of the bilayer metal arrangement (Tung et al. fig. 6 – Metal lines/vias may have adjacent sidewall spacers (e.g. dielectric material)).
CLAIM 12. Tung. in view of Kang et al. disclose a semiconductor structure of claim 11, Tung is silent upon wherein the first metal layer of the bilayer metal arrangement includes ruthenium (Ru), however Kang et al. teaches Ru is a known metal for the purpose, and further is commonly used with the same barrier layer material (Ti/TaN) as used in Tung. As such, Ru would be a obvious material for selection in the device of Tung. as a functional equivalent known for the purpose. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select RU, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
CLAIM 13. Tung et al. in view of Kang et al. disclose a semiconductor structure of claim 12, wherein the second metal layer of the bilayer metal arrangement includes tantalum nitride (TaN) or titanium nitride (TiN) (Both Tung and Kang et al. TaN and TiN [Ti/TaN] are a conventional barrier metal used when forming metallization levels in semiconductor devices.).
CLAIM 14. Tung in view of Kang et al. disclose a semiconductor structure of claim 8, wherein the first level of interconnect wiring has a first pattern and the second level of interconnect wiring has a second pattern, the first and second patterns being different from each other (Tungfig. 6 and Kang et al. fig. 15 – Both references depict “different” patterns. Further, a simple change in the shape or patterning of features constitutes an obvious modification for a person of ordinary skill in the art (POSITA), provided no unexpected results are achieved. MPEP § 2144.04 guidance supports this, stating that routine modifications like altering the shape or proportions of a prior art device are considered obvious design choices unless they produce a new or unexpected function or benefit not previously disclosed.)
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung in view of Kang et al. (US 20230019790 A1) in view of Tandon et al. (US 20170338105 A1).
CLAIM 10. Tung in view of Kang et al. disclose a semiconductor structure of claim 8, however may be silent upon explicitly stating wherein the second level of interconnect wiring further includes a metal bridge (Figure 6 of Tung explicitly discloses a structure capable of forming "bridge" wiring. It is well-recognized in the art that damascene metallization provides conductive “bridges” between metallization levels, structures, and devices. This is visually supported by Tandon et al., which demonstrates conventional, analogous damascene metallization similar to Tung and Kang (Fig. 9A), and further illustrates, from an alternative perspective, the metallization forming “bridges” that connect via portions of the damascene structure (Fig. 12).
It would be obvious to a person of ordinary skill in the art (POSITA) to implement a bridge shape or pattern in the metallization level, as altering the shape of a structure is a matter of mere design choice. See MPEP § 2144.04 (holding that routine modifications, such as altering shape or proportions, are obvious unless they produce new or unexpected results). Because implementing a bridge pattern is a predictable application of known techniques, it falls squarely within the scope of routine design choices available to a POSITA.)
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung in in view of Tandon et al. (US 20170338105 A1).
CLAIM 15. Tung teaches a semiconductor structure comprising:
a first level 22of interconnect wiring (Tung – Fig. 6); and
a second level 36 of interconnect wiring comprising:
a bilayer metal arrangement 34+36+38 comprising a first metal layer and a second metal layer on top of the first metal layer, and wherein the bilayer metal arrangement incorporating adjacent via elements (Tung Fig. 6); and
wherein the second level of interconnect wiring is electrically connected to the first level of interconnect wiring (Tung Fig. 6).
Tung may be silent upon the metallization levels comprising a metal bridge, of the second level of interconnect wiring, disposed between the adjacent via elements, the metal bridge having lateral edges that extend into top portions of the adjacent via elements to form a T-shaped structure between the adjacent via elements (Figure 6 of Tung explicitly discloses a structure capable of forming "bridge" wiring. It is well-recognized in the art that damascene metallization provides conductive “bridges” between metallization levels, structures, and devices. This is visually supported by Tandon et al., which demonstrates conventional, analogous damascene metallization similar to Tung (Tandon -Fig. 9A), and further illustrates, from an alternative perspective, the metallization forming “bridges” that connect via portions of the damascene structure (Tandon Fig. 12).
It would be obvious to a person of ordinary skill in the art (POSITA) to implement a bridge shape or pattern in the metallization level, as altering the shape of a structure is a matter of mere design choice. See MPEP § 2144.04 (holding that routine modifications, such as altering shape or proportions, are obvious unless they produce new or unexpected results). Because implementing a bridge pattern is a predictable application of known techniques, it falls squarely within the scope of routine design choices available to a POSITA.),
CLAIM 16. Tung in view of Kang et al. disclose a semiconductor structure of claim 15, wherein the metal bridge directly contacts the bilayer metal arrangement (Tung Fig. 6 as modified by Tandon – Fig. 12 – A PHOSITA would have found the claimed bridge structures obvious. Modifying Tung (Fig. 6) to include the damascene bridging taught in Tandon (Fig. 12) is a straightforward application of standard techniques to improve wiring density, producing only expected results.).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung in view of Tandon et al. (US 20170338105 A1) in view of Kang et al. (US 20230019790 A1).
CLAIM 17. Tung in view of Tandon disclose a semiconductor structure of claim 15, Tung is silent upon wherein the first metal layer of the bilayer metal arrangement includes ruthenium (Ru), however Kang et al. teaches Ru is a known metal for the purpose, and further is commonly used with the same barrier layer material (Ti/TaN) as used in Tung. As such, Ru would be a obvious material for selection in the device of Tung as a functional equivalent known for the purpose. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select RU, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
CLAIM 18. Tung in view of Tandon in view of Kang et al. disclose a semiconductor structure of claim 17, wherein a second metal layer of the bilayer metal arrangement includes tantalum nitride (TaN) or titanium nitride (TiN) (Both Tung et al. and Kang et al. TaN and TiN [Ti/TaN] are a conventional barrier metal used when forming metallization levels in semiconductor devices.).
CLAIM 19. Tung in view of Tandon in view of Kang et al. disclose a semiconductor structure of claim 15, wherein the first level of interconnect wiring has a first pattern and the second level of interconnect wiring has a second pattern, the first and second patterns being different from each other (Tung fig. 6, Tandon Fig. 12 and Kang et al. fig. 15 – The cited references depict “different” patterns. Further, a simple change in the shape or patterning of features constitutes an obvious modification for a person of ordinary skill in the art (POSITA), provided no unexpected results are achieved. MPEP § 2144.04 guidance supports this, stating that routine modifications like altering the shape or proportions of a prior art device are considered obvious design choices unless they produce a new or unexpected function or benefit not previously disclosed.)
CLAIM 20. Tung in view of Tandon in view of Kang et al. disclose a semiconductor structure of claim 15, wherein the metal bridge extends from the first level of interconnect wiring to the second level of interconnect wiring (Figure 6 of Tung explicitly discloses a structure capable of forming "bridge" wiring. It is well-recognized in the art that damascene metallization provides conductive “bridges” between metallization levels, structures, and devices. This is visually supported by Tandon et al., which demonstrates conventional, analogous damascene metallization similar to Tung (Tandon -Fig. 9A), and further illustrates, from an alternative perspective, the metallization forming “bridges” that connect via portions of the damascene structure (Tandon Fig. 12).
It would be obvious to a person of ordinary skill in the art (POSITA) to implement a bridge shape or pattern in the metallization level, as altering the shape of a structure is a matter of mere design choice. See MPEP § 2144.04 (holding that routine modifications, such as altering shape or proportions, are obvious unless they produce new or unexpected results). Because implementing a bridge pattern is a predictable application of known techniques, it falls squarely within the scope of routine design choices available to a POSITA.),
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
5/11/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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