DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15-16 are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Liu et a. (US20190123061A1 hereinafter Liu’061).
Regarding claim 15, Fig.6L of Liu’061 teaches a semiconductor memory device, comprising:
a stacked structure 10 (Fig.6C, para.0079) including insulating layers 100 (para.0079) and conductive layers 101 (para.0079) that are alternately disposed in a vertical direction;
a first structure (see annotated Fig.6L) including a first channel pattern 22 (para.0084) that passes through the stacked structure 10 and a first memory pattern 20/21 (para.0084) between the first channel pattern 22 and the stacked structure 10;
second structures 23/24 (para.0096) passing through the stacked structure 10 and neighboring each other with the first structure (see annotated Fig.6L) interposed therebetween; and
a third structure (see annotated Fig.6L) facing the first structure between the second structures 23/24 and including a second channel pattern 22 (para.0084) that passes through the stacked structure 10 and a second memory pattern 20/21 (para.0084) between the second channel pattern 22 and the stacked structure 10,
wherein each of the second structures 23/24 includes a qate pattern 24 (para.0096) and an insulating pattern 23 (para.0096) disposed between the gate pattern 24 and the stacked structure 10, wherein the insulating pattern 23 has a tubular shape (para.0093, wherein inner dielectric layer 23 is formed inside each tube-shaped stacked layer), and
wherein the second structures 23/24 are in contact with a side surface of the first structure and a side surface of the third structure (see annotated Fig.6L).
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Regarding claim 16, Liu’061 further teaches the semiconductor memory device of claim 15, wherein: the first structure includes a first curved portion that contacts the stacked structure;
the third structure includes a second curved portion that contacts the stacked structure; and
each of the second structures includes a third curved portion that is coupled to the first curved portion and the second curved portion and that contacts the first structure and the third structure (see annotated Fig.6L, para.0087, wherein the outermost ferroelectric layer 20 and the outer dielectric layer 21 are formed inside each tube-shaped stacked layer and wherein the side contacting dielectric layer is generally straight but the side contacting the stacked layer 10 is curved).
Regarding claim 17, Liu’061 further teaches the semiconductor memory device of claim 15, wherein the gate pattern 24 (para.0096) of each of the second structures 23/24 (para.0096) has substantially a cylindrical shape.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et a. (US20190123061A1; hereinafter Liu’061) in view of Liu et al. (US9245901B1; hereinafter Liu’901).
Regarding claim 1, Fig.6L of Liu’061 teaches a semiconductor memory device, comprising:
a stacked structure 10 (Fig.6C, para.0079) including insulating layers 100 (para.0079) and conductive layers 101 (para.0079) that are alternately disposed in a vertical direction;
a first structure (see annotated Fig.6L) including a channel layer 22 (para.0084) that passes through the stacked structure 10 and a memory pattern 20/21 (para.0084) between the channel layer 22 and the stacked structure 10; and a second structure 23/24 (para.0096) including an insulating pattern 23 (para.0096) that is formed along a sidewall of the stacked structure 10 and a gate pattern 24 (para.0096) that is formed on a sidewall of the insulating pattern 23,
wherein the second structure 23/24 is in contact with a side surface of the first structure.
Liu’061 does not teach wherein the insulating pattern of the second structure includes a first oxide layer, a nitride layer, and a second oxide layer.
Fig.2E of Liu’901 teaches gate pillar structures 108 that includes charge storage layer 110 and the conductive pillar 112 which serves as a control gate; and wherein a charge storage material layer may include a composite layer such as an oxide/nitride/oxide (ONO) layer, an oxide/nitride/oxide/nitride (ONON) layer (col.6, lines 25-28, col.7, lines 48-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date to the claimed invention to include layer 110 of Liu’901 in the teachings of Liu’061 in order to provide better electrical isolation (col.7, lines 52-54).
Regarding claim 2, Liu’061 further teaches the semiconductor memory device of claim 1, wherein the first structure (see annotated Fig.6L) includes a curved portion and a straight portion (para.0087, wherein the outermost ferroelectric layer 20 and the outer dielectric layer 21 are formed inside each tube-shaped stacked layer), wherein the curved portion contacts the sidewall of the stacked structure 10 (Fig.6C, para.0079), and wherein the straight portion contacts a sidewall of the second structure 23/24 (para.0096).
Regarding claim 3, Liu’061 further teaches the semiconductor memory device of claim 2, wherein the channel layer 22 (para.0084) has edges that are formed at intersections of the curved portion and the straight portion (para.0087, wherein the outermost ferroelectric layer 20 and the outer dielectric layer 21 are formed inside each tube-shaped stacked layer).
Regarding claim 4, Liu’061 further teaches the semiconductor memory device of claim 1, wherein the insulating pattern 23 (para.0053) of the second structure 23/24 (para.0096) includes the same material as the memory pattern of the first structure (para.0053, wherein each of the materials of the inner dielectric layer 23 and the outer dielectric layer 21 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and any combination thereof).
Regarding claim 5, Liu’061 further teaches the semiconductor memory device of claim 1, wherein the insulating pattern 23 (para.0096) is disposed between the stacked structure 10 (Fig.6C, para.0079) and the gate pattern 24 (para.0096) and extends between the first structure (see annotated Fig.6L) and the gate pattern 24.
Regarding claim 6, Liu’061 further teaches the semiconductor memory device of claim 1, wherein the second structure 23/24 (Figs.1 and 2, para.0040, wherein gate columns 24 and dielectric layers 23 have rectangular shapes which make them have a linear shape extending in a direction parallel to world lines and insulating layers) has a linear shape extending in a horizontal direction substantially parallel to each of the insulating layers 100 (para.0079) and the conductive layers 101 (para.0079).
Regarding claim 7, Liu’061 further teaches the semiconductor memory device of claim 1, wherein the first structure (see annotated Fig.6L, para.0087, wherein the outermost ferroelectric layer 20 and the outer dielectric layer 21 are formed inside each tube-shaped stacked layer; wherein the side contacting dielectric layer is generally straight but the side contacting the stacked layer is curved) has substantially a semicircular shape.
Regarding claim 8, Fig.6L of Liu’061 teaches a semiconductor memory device, comprising:
a first stacked structure (see annotated Fig.6L) and a second stacked structure (see annotated Fig.6L) that are spaced apart from each other, each of the first and second stacked structures (see annotated Fig.6L) including conductive layers 101 (para.0079) that are stacked in a vertical direction;
a first structure (see annotated Fig.6L) including a first channel pattern 22 (para.0084) that passes through the conductive layers 101 of the first stacked structure and a first memory pattern 20/21 (para.0084) between the first channel pattern 22 and the first stacked structure;
a second structure 23/24 (para.0096) disposed between the first stacked structure and the second stacked structure; and
a third structure (see annotated Fig.6L) including a second channel pattern 22 (para.0084) that passes through the conductive layers of the second stacked structure (see annotated Fig.6L) and a second memory pattern 20/21 (para.0084) between the second channel pattern and the second stacked structure,
wherein the second structure 23/24 (para.0096) includes a gate pattern 23/24 (para.0096) between the first structure and the third structure (see annotated Fig.6L), wherein the second structure 23/24 includes insulating patterns 23/24 (para.0096) at opposite sides of the gate pattern 24, and
wherein the second structure 23/24 (para.0096) is in contact with a side surface of the first structure and a side surface of the third structure (see annotated Fig.6L).
Liu’061 does not teach wherein each of the insulating patterns of the second structure includes a first oxide layer, a nitride layer, and a second oxide layer.
Fig.2E of Liu’901 teaches gate pillar structures 108 that includes charge storage layer 110 and the conductive pillar 112 which serves as a control gate; and wherein a charge storage material layer may include a composite layer such as an oxide/nitride/oxide (ONO) layer, an oxide/nitride/oxide/nitride (ONON) layer (col.6, lines 25-28, col.7, lines 48-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date to the claimed invention to include layer 110 of Liu’901 in the teachings of Liu’061 in order to provide better electrical isolation (col.7, lines 52-54).
Regarding claim 9, Liu’061 further teaches the semiconductor memory device of claim 8, wherein each of the insulating patterns 23 (para.0096) extends to contact the first stacked structure and the first structure or extends to contact the second stacked structure and the third structure (see annotated Fig.6L).
Regarding claim 10, Liu’061 further teaches the semiconductor memory device of claim 8, wherein the first structure (see annotated Fig.6L) comprises:
a first curved portion contacting the first stacked structure (see annotated Fig.6L, para.0087, wherein the outermost ferroelectric layer 20 and the outer dielectric layer 21 are formed inside each tube-shaped stacked layer and wherein the side contacting dielectric layer is generally straight but the side contacting the stacked layer is curved); and
a first straight portion contacting one of the insulating patterns 23 (para.0096), and
wherein the third structure comprises:
a second curved portion contacting the second stacked structure (see annotated Fig.6L, wherein the side contacting dielectric layer is generally straight but the side contacting the stacked layer is curved); and a second straight portion contacting another of the insulating patterns 23 (para.0096).
Regarding claim 11, Liu’061 further teaches the semiconductor memory device of claim 8, wherein the first structure and the third structure (see annotated Fig.6L) are substantially symmetrical with respect to the second structure 23/24 (para.0096).
Regarding claim 12, Liu’061 further teaches the semiconductor memory device of claim 8, wherein each of the insulating patterns 23 (para.0096) of the second structure 23/24 (para.0096) includes the same material as the first and second memory patterns (para.0053, wherein each of the materials of the inner dielectric layer 23 and the outer dielectric layer 21 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and any combination thereof).
Regarding claim 13, Liu’061 further teaches the semiconductor memory device of claim 8, wherein the second structure 23/24 (Figs.1 and 2, para.0040, wherein gate columns 24 and dielectric layers 23 have rectangular shapes which make them have a linear shape extending in a direction parallel to world lines and insulating layers) has a linear shape extending in a horizontal direction substantially parallel to each of the conductive layers 101 (para.0079).
Regarding claim 14, Liu’061 further teaches the semiconductor memory device of claim 8, wherein each of the first channel pattern 22 (see annotated Fig.6L, para.0084) and the second channel pattern 22 (see annotated Fig.6L, para.0084) has an edge adjacent to the gate pattern 24 (para.0096).
Regarding claim 18, Liu’061 does not teach wherein the insulating pattern of the second structure includes a first oxide layer, a nitride layer, and a second oxide layer.
Fig.2E of Liu’901 teaches gate pillar structures 108 that includes charge storage layer 110 and the conductive pillar 112 which serves as a control gate; and wherein a charge storage material layer may include a composite layer such as an oxide/nitride/oxide (ONO) layer, an oxide/nitride/oxide/nitride (ONON) layer (col.6, lines 25-28, col.7, lines 48-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date to the claimed invention to include layer 110 of Liu’901 in the teachings of Liu’061 in order to provide better electrical isolation (col.7, lines 52-54).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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