Prosecution Insights
Last updated: April 19, 2026
Application No. 17/981,921

COMPOSITE CATHODE CONTACT WITH SPACER LAYER FOR MONOLITHICALLY INTEGRATED MICRO-LEDS, MINI-LEDS, AND LED ARRAYS

Non-Final OA §102§103§112
Filed
Nov 07, 2022
Examiner
GREWAL, HEIM KIRIN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lumileds LLC
OA Round
2 (Non-Final)
92%
Grant Probability
Favorable
2-3
OA Rounds
3y 4m
To Grant
93%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
23 granted / 25 resolved
+24.0% vs TC avg
Minimal +1% lift
Without
With
+0.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
29 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
54.1%
+14.1% vs TC avg
§102
29.4%
-10.6% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 25 resolved cases

Office Action

§102 §103 §112
Detailed Notice Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims The following in response to the communication filed 12/17/2025. Claims 1-20 are currently pending. Claims 1, 11, and 19 have been amended. Claims 11-18 have been withdrawn. Claims 1-10 and 19-20 have been examined. Information Disclosure Statement The information disclosure statements (IDS) submitted on 12/18/2025, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Response to Arguments The previous drawing objections are withdrawn in light of the new drawings submitted. New drawing objections are noted below. The previous rejection under §112 is withdrawn in light of the amendments made to claim 1 and 19. New §112 rejections are noted below. Applicant's arguments filed 12/17/2025, with regards to §102 and 103, starting on page 9 of the Remarks, have been fully considered but they are not persuasive. In particular, the distributed Bragg reflector (DBR) of Tan is considered to be on the sidewall of the trench and not directly the bottom surface of the trench as it is on the transparent conductive layer 1362. See below for more detail. Examiner recognized upon review that the Tan reference does not qualify as prior art as a 102(a)(1) reference. Therefore, the previous 102(a)(1) rejection is hereby withdrawn. However a new rejection under 102(a)(2) is presented below. Claim Rejections - 35 USC § 112 112(a) REJECTION The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-10, 19, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 1 and 19, the limitation “not on the bottom surface of the trench” is not properly supported in the written description of the specification. Applicant shows in Fig. 3 and 4 that the DBR is not “directly” on the bottom surface of the trench. Furthermore, the term “on” is defined by the Applicant in the Specification at [0157] that it could mean either directly on or indirectly on, unless the word “directly” is used. Thus, there is no support in the specification that the DBR is neither directly nor indirectly on the bottom surface of the trench. Claims 2-10 and 20 are rejected based on their dependence to claim 1 and 19 respectively. 112(b) REJECTION The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-10, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 and 19, recite the limitation “not on the bottom surface of the trench.” As discussed above, in Figs. 3 and 4, the DBR is indirectly “on” the bottom surface of the trench. In view of this, Examiner feels that applicant intended to amend the claims to read as “not directly on the bottom surface of the trench.” Therefore, for purposes of examination, the claims will be considered to read as “not directly on the bottom surface of the trench.” Claims 2-10 and 20 are rejected based on their dependence to claim 1 and 19 respectively. Drawing Objection The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the DBR being "not on the bottom surface of the trench" as currently the DBR is shown as indirectly on the bottom surface of the trench. must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, 2, 4, 6, 7, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tan et al. U.S. 20220384516A1 (hereinafter Tan). Regarding Claim 1, Tan discloses: A light emitting diode (LED) (LED device including micro-LEDs 1300 in FIG. 13, [0148]) device comprising: a mesa (Fig. 13, lefthand mesa 1305]) comprising semiconductor layers, the semiconductor layers including an N-type layer (first semiconductor material 1310, [0149] may be an n-doped layer), an active layer (active layer 1320), and a P-type layer (second semiconductor material 1330, [0149] may be p-type), the mesa having a top surface (mesa structures inherently have a top surface)and at least one side wall (sidewalls 1306), the at least one side wall defining a trench having a bottom surface; (where the trench includes dead zone 1382 a trench having the side surfaces of the mesa structure and the bottom surface as defined by the substrate between two mesa structures) a transparent conductive layer on the at least one side wall on the bottom surface of the trench; (low index conductive material 1362 is on the sidewall 1306 and on the bottom surface of the trench, which is related to low index conductive material 1162 which may be a transparent conductive oxide such as a zinc oxide [0132]) a distributed Bragg reflector (DBR) (DBR, 1365) on the transparent conductive layer on the at least one sidewall of the trench and not on the bottom surface of the trench; ([0136] DBR is formed between the low index conductive material layer and metal layer and is on the low index conductive material 1362) a cathode layer (metal layer 1370, related to 1170 which is metal layer an n-type contact [0135] an n-type contact is understood to be a cathode layer contact) in the trench and on the distributed Bragg reflector (DBR); and (See Fig. 13, metal layer 1370 is on the DBR1365) a p-type contact (contact layer 1340, [0150] is a p-type contact layer) on the top surface of the mesa. (see Fig. 13) Regarding Claim 2, Tan discloses all the elements of claim 1 above and further discloses: wherein the transparent conductive layer comprises zinc oxide. (the low index conductive material 1362 may be another transparent conductive oxide (TCO) such as indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), [0132]). Regarding Claim 4, Tan discloses all the elements of claim 1 above and further discloses: wherein the distributed Bragg reflector (DBR) (DBR, 1365) comprises silicon oxide ([0136], DBR layer includes material like SiO2.) Regarding Claim 6, Tan discloses all the elements of claim 1 above and further discloses: comprising a dielectric layer (dielectric layer 1360, [0151]]) on a portion of the mesa. (Fig. 13, [0151], dielectric layer 1360 is formed on the sidewalls of the active layer.) Regarding Claim 7, Tan discloses all the elements of claim 6 above and further discloses: wherein the dielectric layer comprises a material selected from the group consisting of silicon nitride (SiN), titanium oxide (TiOx), niobium oxide (NbOx), aluminum oxide (AIOx), hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum nitride (AIN), silicon oxide (SiOx), and hafnium-doped silicon dioxide (HfSiOx). ([0151], the dielectric layer 1360 includes SiN.) Regarding Claim 9, Tan discloses all the elements of claim 1 above. Tan further discloses: wherein the cathode layer comprises one or more of silver (Ag) and aluminum (Al). ([0154], metal layer1 370 is aluminum (Al), silver (Ag) or an alloy material contain such.) Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 19 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tan. Regarding Claim 19, Tan discloses: A light emitting diode (LED) (LED device including micro-LEDs 1300 in FIG. 13, [0148]) device comprising: a mesa (Fig. 13, lefthand mesa 1305]) comprising semiconductor layers, the semiconductor layers including an N-type layer (first semiconductor material 1310, [0149] may be an n-doped layer), an active layer (active layer 1320), and a P-type layer (second semiconductor material 1330, [0149] may be p-type), the P-type layer having a top surface and at least one side surface, (See Fig. 13, 1330) the active layer having a top surface and at least one side surface, (See Fig. 13, 1320) and the N-type layer having a top surface and at least one side surface, (See Fig. 13, 1310) the mesa having a mesa top surface (mesa structures inherently have a top surface) and at least one side wall (sidewalls 1306), the at least one side wall formed by the N-type layer, the active layer, and the P-type layer (See, Fig. 13) and defining a trench having a bottom surface; (where the trench includes dead zone 1382 a trench having the side surfaces of the mesa structure and the bottom surface as defined by the substrate between two mesa structures) a dielectric layer (dielectric layer 1360 and mask layer 1355, [0150-0151] both the 1355 and 1360 may be SiN) disposed along the side surface of the P-type layer, the side surface of the active layer, (See. Fig. 13, dielectric layer 1360 is on a portion of the mesa and the sidewalls of the p-type layer and active layer.)) … and on the mesa top surface (See Fig. 13, the mask layer is a dielectric SiN [0150] and is on the top surface of the mesa.) a zinc oxide layer on the dielectric layer, (low index conductive material 1362 which is related to low index conductive material 1162 which may be a transparent conductive oxide such as a zinc oxide [0132]) and is on the dielectric layer1360 and 1355) on a second portion of the side surface the N-type layer (See Fig. 13) and on the bottom surface of the trench, (Fig. 13) the dielectric layer disposed between the zinc oxide layer and the side surface of the P-type layer, the side surface of the active layer, and the first portion of the side surface of the N-type layer; (Fig. 13, low index conductive material 1362 is on the sidewall 1306 and in the trench, which is related to low index conductive material 1162 which may be a transparent conductive oxide such as a zinc oxide [0132]) a distributed Bragg reflector (DBR) (DBR 1365) on the zinc oxide layer (the low index conductive material 1362, which may be a zinc oxide [0132]) on at least one side wall of the trench and not on the bottom surface of the trench; (See Fig. 13, [0136] DBR is formed between the low index conductive material layer and metal layer and is on the low index conductive material 1362 and not touching the substrate) a cathode layer in the trench (See Fig. 13 and metal layer 1370, related to 1170 which is metal layer an n-type contact [0135] an n-type contact is understood to be a cathode layer contact) on the distributed Bragg reflector (DBR) (1365) and on the zinc oxide layer (1362) on the bottom surface of the trench; and (See Fig. 13) a p-type contact (contact layer 1340, [0150] is a p-type contact layer) on the mesa top surface. (see Fig. 13) The embodiment of shown in Fig. 13 does not appear to show that the dielectric layer is disposed along “a first portion of the side surface of the N-type layer”. However, the embodiment of Fig. 7A in discloses and N-type layer 720 (Tan, Fig. 7A [0098]) which has a passivation layer 770 ([0099], which can be oxide therefor is a dielectric layer) on a first portion of the N-type layer 720 and not a second portion of the layer 720. Therefore, Tan teaches a dielectric layer disposed along “a first portion of the side surface of the N-type layer”. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tan, embodiment of Fig. 13 to have a dielectric on the first portion of the N-type layer as taught by Tan, embodiment of Fig. 7A, for purposes of acting as a reflector to reflect emitted light out of the LED. (Tan, [0099].) Furthermore, combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009). Regarding Claim 20, Tan discloses all the elements of claim 19 above. Tan further discloses: wherein the cathode layer comprises one or more of silver (Ag) and aluminum (Al). ([0154], metal layer1 370 is aluminum (Al), silver (Ag) or an alloy material contain such.) Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tan as applied to claim 2, and further in view of Jung et al. US 20160005917 (hereinafter Jung). Regarding Claims 3, Tan discloses all the elements of claim 2 above. Tan does not explicitly disclose wherein the transparent conductive layer has a thickness in a range of from 10 nm to 500 nm. However, in a similar field of endeavor, Jung teaches that wherein the first electrode (Fig. 2, ohmic contact 151) includes a first ohmic contact layer contacting the first semiconductor layer and formed of a transparent conductive oxide and a first reflective layer disposed on the first ohmic contact layer, [0022]. Jung further teaches the thickness of the ohmic contact layer (151) could be 60nm (Jung [0022], [0113]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tan to have the transparent conductive layer has a thickness in a range of from 10 nm to 500 nm as taught by Jung for purposes of improve light reflectance and light extraction efficiency. (Jung, [0077].) Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tan as applied to claim 1 above, and further in view of Iou et al. US 20060227531 A1 (hereinafter Iou). Regarding Claim 8, Tan discloses all the elements of claim 1 above. Tan does not explicitly disclose wherein the transparent conductive layer is a CVD transparent conductive layer or a sputtered transparent conductive layer. However, in a similar field of endeavor, Iou, which teaches an organic light emitting diode display (Iou, Abstract) discloses: wherein the transparent conductive layer is a CVD transparent conductive layer or a sputtered transparent conductive layer. (Iou, [0018], the first electrode 212 which is a transparent electrode can be made by CVD.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit the indium zinc oxide or aluminum doped zinc oxide by sputtering or chemical vapor deposition to form since this would have been obvious to try as both are solutions out of a finite number of solutions identified by Iou for depositing these materials and this would have had a reasonable expectation of success. As a result, transparent conductive layer would be a deposited as a CVD transparent conductive layer or a sputtered transparent conductive layer. Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tan as applied to claim 1 and claim 4 above, and further in view of Danesh et al. US 20190088820 A1. (Hereinafter Danesh) Regarding claim 5, Tan discloses all the elements of claim 4 above and further discloses, “the thicknesses and/or materials in the layers of a DBR structure may be selected to cause constructive interference between light reflected at the interfaces between the layers of the DBR to achieve high reflectivity for a particular wavelength band and/or other optical properties,” [0154]. However, Tan does not disclose specifically that the distributed Bragg reflector (DBR) has a thickness of at least 0.2 microns. Danesh, which teaches method of forming light emitting devices (Danesh, Abstract), discloses: wherein the distributed Bragg reflector (DBR) has a thickness of at least 0.2 microns. (Danesh, Fig. 25, reflector layer 70 which is a DBR, [0110], has thickness of at least 500nm (.5 microns) and can be between 2-6 microns, [0209]. See also [0010].) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tan to have wherein the distributed Bragg reflector (DBR) has a thickness of at least 0.2 microns as taught by Danesh for purposes of absorbing mechanical shocks as well providing good reflectance. (Danesh, [0209].) Regarding claim 10, Tan discloses all the elements of claim 1 above. Tan further discloses wherein the semiconductor layers are epitaxial semiconductor layers. (Tan, [0139]). However, Tan does not explicitly disclose that the semiconductor layers have a thickness at least 1 micron. Danesh, which teaches method of forming light emitting devices (Danesh, Abstract), discloses: wherein the semiconductor layers are epitaxial semiconductor layers having a thickness at least 1 micron. (Danesh, Fig. 7, [0077], mesa portion 32 (n-doped region) with a height range of 250 nm to 5 microns. Therefore based on the based on the height of the n-type layer along the total height of the epitaxial grown semiconductor layers has a range that cover the thickness being at least 1 micron.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tan to have the semiconductor layers are epitaxial semiconductor layers having a thickness at least 1 micron as taught by Danesh for purposes of growth as single crystalline doped compound of a controlled thickness. (Danesh, [0077].) Prior Art Made of Record The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zheng et al. US 20110297914 A1- Fig. 6 and Fig. 8, a light emitting diode with a distributed Bragg reflector and a metal reflective layer on its side. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HEIM KIRIN GREWAL/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Nov 07, 2022
Application Filed
Sep 29, 2025
Non-Final Rejection — §102, §103, §112
Dec 17, 2025
Response Filed
Feb 03, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

2-3
Expected OA Rounds
92%
Grant Probability
93%
With Interview (+0.6%)
3y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 25 resolved cases by this examiner. Grant probability derived from career allow rate.

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