DETAILED ACTION
Claims 1-18 and 20-27 are amended. Claim 30 is new. Claims 1-30 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/09/2025 has been entered.
Examiner’s Notes
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Response to Amendment
Amendments to claims 6-9 and 11-18 are fully considered and are satisfactory to overcome the corresponding rejections under 35 U.S.C. §112(b) presented in the previous Office Action.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it is not within the range of 50 to 150 words in length. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4, 6-10, 15-20, 25, 26, and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Yildiz et al. (US 2011/0078691 A1; hereinafter Yildiz) in view of Asthana (US 11,055,812 B1).
With respect to claim 1, Yildiz teaches: A [Graphics] Processing Unit (see e.g. Yildiz, paragraph 44: “processing units 104A-104D”; and Fig. 1)…, comprising:
one or more circuits (see e.g. Yildiz, paragraph 44: “Multi-core processor 104 includes processing units 104A-104D”; and paragraph 31: “computer hardware, including processors”) that cause
launch at least two graphs (see e.g. Yildiz, paragraph 25: “Execution of a task included in task hierarchy is initiated… A plurality of concurrently executable sub-tasks are spawned during the time the task is executing”; paragraph 48: “FIG. 3 illustrates an example task hierarchy 300. Task hierarchy 200 depicts a two level task hierarchy. A parent task spawns N child tasks at various points in the parent task delegate's execution (where N represents some integer) and its second child task then spawns further children tasks at various points in the second child task delegate's execution”; and Fig. 3)…, the at least two graphs comprising one or more operations (see e.g. Yildiz, paragraph 37: “a "task" is defined as a work item that represents a small portion of the processing that the application needs to perform. A task can include a sub-routine (aka "task delegate") and state variables that the sub-routine utilizes to execute”; and Fig. 3); and
perform the one or more operations (see e.g. Yildiz, paragraph 25: “code is executing in accordance with a task hierarchy that divides processing into tasks”; and paragraph 27: “Each of the plurality of concurrently executable sub-tasks is concurrently executed to perform the indicated portions of work related to the task”).
Yildiz discloses a hardware multi-core processor 104 comprising processing units 104A-104D, which inherently discloses corresponding processing circuitry, to start execution of a task hierarchy 300 (i.e. a first graph; see e.g. Yildiz, Fig. 3) comprising at least one Child/Sub-Child Task hierarchy (i.e. a second graph; see e.g. Yildiz, Fig. 3: “Child Task 311B”, “Sub Child Task 321A”, “Sub Child Task 321B”) comprising tasks and sub-tasks to perform work items (i.e. operations).
On the other hand, even though Yildiz discloses processing units 104A-D launching and executing at least two graphs, Yildiz does not explicitly disclose these processing units being “graphics” processing units executing graphs “instantiated by a host processor”.
However, Asthana teaches:
GPU (see e.g. Asthana, column 1, line 21: “graphic processing units (GPUs)”)
a hardware accelerator comprising… the GPU to (see e.g. Asthana, column 1, lines 18-26: “programmable processors that are used for specialized processing of various types, such as processors for graphic processing operations, which are typically called graphic processing units (GPUs). GPUs generally comprise multiple cores, each designed for executing the same instruction or types of instructions on parallel data streams, making them more effective than general-purpose CPUs for algorithms in which processing of large blocks of data is done in parallel”):
instantiated by a host processor (see e.g. Asthana, column 1, lines 26-29: “a CPU functions as the “host” entity, handing off more specialized processing tasks (e.g., parallelized graphics tasks) to the GPU”; column 5, lines 28-30: “host CPU may then perform a dependency analysis to encode the dependencies for dependency graph generation”; column 5, lines 44-63: “host CPU (or GPU firmware, in some implementations) may add the determined dependency information based on the above-described dependency analysis for each incoming command into a data structure and use the information in the data structure to construct and maintain an execution graph indicating an execution order of the commands… the host CPU is generating the execution graph, the background execution thread on the GPU firmware may fetch only the actual commands to launch on GPU, e.g., in graph walk-order, from graph data structure of the execution graph”),
Yildiz and Asthana are analogous art because they are in the same field of endeavor: managing various processing units to perform operations defined by graphs. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Yildiz with the teachings of Asthana. The motivation/suggestion would be to improve resource utilization efficiency (see e.g. Asthana, column 1, lines 15-40).
With respect to claim 4, Yildiz as modified teaches: The GPU of claim 1, wherein the at least two graphs are to cause the GPU to launch another instance of a first graph (see e.g. Yildiz, paragraph 48: “A parent task spawns N child tasks at various points in the parent task delegate's execution (where N represents some integer) and its second child task then spawns further children tasks at various points in the second child task delegate's execution”; and paragraph 51: “sub child tasks 321A and/or 321B are parent tasks to one or more further child tasks. Any of the one or more further child tasks can also be parent tasks additional child tasks, etc.”).
With respect to claim 6, Yildiz as modified teaches: The GPU of claim 1, wherein the one or more circuits perform instructions that implement an application programing interface (“API”) that is to cause the GPU to launch the at least two graphs (see e.g. Yildiz, paragraph 50: “Task parentTask301 = Task.Factory.StartNew(()=>”, “Task child311B = StartNewTask(()=>”, “Task subChild321A = StartNewTask(()=>”).
With respect to claim 7, Yildiz as modified teaches: The GPU of claim 1, wherein the one or more circuits execute one or more applications that are to cause the GPU to launch the at least two graphs (see e.g. Yildiz, paragraph 37: “a "task" is defined as a work item that represents a small portion of the processing that the application needs to perform”; and paragraph 83: “an initial task spawned by an application”).
With respect to claim 8, Yildiz as modified teaches: The GPU of claim 1, wherein the at least two graphs include a first graph and a second graph (see e.g. Yildiz, paragraph 25: “A plurality of concurrently executable sub-tasks are spawned during the time the task is executing”; paragraph 48: “FIG. 3 illustrates an example task hierarchy 300… second child task then spawns further children tasks at various points in the second child task delegate's execution”),
the GPU launches the first graph in response to a launch instruction from a central processing unit (“CPU”) (see e.g. Yildiz, Fig. 1: “Multi-Core Processor 104”; paragraph 43: “computer architecture 100 can be used to facilitate parallel execution of tasks for a program. For example, a run command can cause program 111 to be executed. During execution, program 111 can spawn various tasks, such as, for example, tasks 121, 131, 132, 141, and 142, during execution. Tasks can be spawned, perform specified operations”; paragraphs 44-45; and Fig. 1), and
the first graph is to cause the GPU to launch the second graph (see e.g. Yildiz, paragraph 48: “A parent task spawns N child tasks at various points in the parent task delegate's execution (where N represents some integer) and its second child task then spawns further children tasks at various points in the second child task delegate's execution. As depicted, task hierarchy 300 includes parent task 301, child tasks 311A, 311B, 311C through 311N, and sub child tasks 321A and 321B”).
With respect to claim 9, Yildiz as modified teaches: The GPU of claim 1, further comprising:
memory (see e.g. Yildiz, Fig. 1: “System Memory 103”) accessible by the one or more circuits (see e.g. Yildiz, paragraph 42: “computer system 101, which further includes storage media 102, system memory 103, multi-core processor 104”; and Fig. 1), the one or more circuits cause a central processing unit (“CPU”) (see e.g. Yildiz, Fig. 1: “Multi-Core Processor 104”) to store the at least two graphs using the memory (see e.g. Yildiz, paragraph 43: “computer architecture 100 can be used to facilitate parallel execution of tasks for a program. For example, a run command can cause program 111 to be executed. During execution, program 111 can spawn various tasks, such as, for example, tasks 121, 131, 132, 141, and 142, during execution. Tasks can be spawned, perform specified operations, and then complete and go away. Each task that is spawned can be executed in its own thread. For example, task 121 can be executed in thread 122, task 131 can be executed in thread 133, task 132 can be executed in thread 134, task 141 can be executed in thread 143, task 142 can be executed in thread 144, etc.”; and Fig. 1).
With respect to claims 10 and 15-18: Claims 10 and 15-18 are directed to a system comprising one or more processors comprising at least one Graphics Processing Unit (“GPU”) corresponding to the GPU disclosed in claims 1 and 6-9, respectively; please see the rejections directed to claims 1 and 6-9 above which also cover the limitations recited in claims 10 and 15-18. Note that, Yildiz as modified also discloses a system 101 comprising a processor 104 with processing units 104A-D corresponding to the GPU disclosed in claims 1 and 6-9.
With respect to claim 19, Yildiz as modified teaches: The system of claim 10, wherein the system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a perception system for an autonomous or semi-autonomous machine;
a first system for performing simulation operations;
a second system for performing digital twin operations;
a third system for performing light transport simulation;
a fourth system for performing collaborative content creation for 3D assets;
a fifth system for performing deep learning operations;
a sixth system implemented using an edge device;
a seventh system implemented using a robot;
an eighth system for performing conversational Artificial Intelligence operations;
a ninth system for generating synthetic data;
a tenth system incorporating one or more virtual machines (VMs);
an eleventh system implemented at least partially in a data center;
a twelfth system implemented at least partially using cloud computing resources;
a thirteenth system for implementing a web-hosted service for detecting program workload inefficiencies; or
an application as an application programming interface (“API”) (see e.g. Yildiz, paragraph 37: “a "task" is defined as a work item that represents a small portion of the processing that the application needs to perform”; paragraph 83: “an initial task spawned by an application”; and paragraph 50: “Task parentTask301 = Task.Factory.StartNew(()=>”, “Task child311B = StartNewTask(()=>”, “Task subChild321A = StartNewTask(()=>”).
With respect to claim 20: Claim 20 is directed to a method corresponding to the active functions implemented by the GPU disclosed in claim 1; please see the rejection directed to claim 1 above which also covers the limitations recited in claims 20.
With respect to claim 25, Yildiz as modified teaches: The method of claim 20, wherein a first graph of the at least two graphs is launched in response to a communication from at least one processor other than the GPU (see e.g. Yildiz, Fig. 1: “Multi-Core Processor 104”; paragraph 43: “computer architecture 100 can be used to facilitate parallel execution of tasks for a program. For example, a run command can cause program 111 to be executed. During execution, program 111 can spawn various tasks, such as, for example, tasks 121, 131, 132, 141, and 142, during execution. Tasks can be spawned, perform specified operations”; paragraphs 44-45; and Fig. 1); and
the first graph uses the GPU to launch a second graph of the at least two graphs (see e.g. Yildiz, paragraph 48: “A parent task spawns N child tasks at various points in the parent task delegate's execution (where N represents some integer) and its second child task then spawns further children tasks at various points in the second child task delegate's execution”; and paragraph 51: “sub child tasks 321A and/or 321B are parent tasks to one or more further child tasks. Any of the one or more further child tasks can also be parent tasks additional child tasks, etc.”).
With respect to claim 26, Yildiz as modified teaches: The method of claim 25, wherein executing at least one operation of the one or more operations corresponding to the second graph (see e.g. Yildiz, paragraph 25: “Execution of a task included in task hierarchy is initiated… A plurality of concurrently executable sub-tasks are spawned during the time the task is executing”) causes the GPU to launch of a third graph (see e.g. Yildiz, paragraph 48: “A parent task spawns N child tasks at various points in the parent task delegate's execution (where N represents some integer) and its second child task then spawns further children tasks at various points in the second child task delegate's execution”; and paragraph 51: “a task hierarchy can include an arbitrary number of levels (as configured in the code that is executing). For example, it may be that sub child tasks 321A and/or 321B are parent tasks to one or more further child tasks. Any of the one or more further child tasks can also be parent tasks additional child tasks, etc.”).
With respect to claims 28 and 29: Claims 28 and 29 are directed to a method corresponding to the active functions implemented by the GPU disclosed in claims 6 and 7, respectively; please see the rejections directed to claims 6 and 7 above which also cover the limitations recited in claims 28 and 29.
With respect to claim 30, Yildiz as modified teaches: The CPU of claim 1,wherein launching the at least two graphs comprises launching a first graph of the at least two graphs (see e.g. Yildiz, paragraph 83: “an initial task spawned by an application”), and launching a second graph of the at least two graphs based at least on at least one dependency of the first graph (see e.g. Yildiz, paragraph 48: “A parent task spawns N child tasks at various points in the parent task delegate's execution (where N represents some integer) and its second child task then spawns further children tasks at various points in the second child task delegate's execution. As depicted, task hierarchy 300 includes parent task 301, child tasks 311A, 311B, 311C through 311N, and sub child tasks 321A and 321B”; and Fig. 3).
Claims 5, 13, 14, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Yildiz in view of Asthana as applied to claims 4, 10, and 20 above, and further in view of Ferdinand et al. (US 2013/0346274 A1; hereinafter Ferdinand).
With respect to claim 5, Yildiz as modified teaches: The GPU of claim 4, wherein the at least two graphs are to cause the GPU to launch the another instance of the first graph (see e.g. Yildiz, paragraph 48: “A parent task spawns N child tasks at various points in the parent task delegate's execution (where N represents some integer) and its second child task then spawns further children tasks at various points in the second child task delegate's execution”; and paragraph 51: “sub child tasks 321A and/or 321B are parent tasks to one or more further child tasks. Any of the one or more further child tasks can also be parent tasks additional child tasks, etc.”)
Even though Yildiz discloses monitoring completion of task executions within the parent task, child task, and sub-task hierarchies (see e.g. Yildiz, paragraph ), Yildiz does not explicitly disclose launching a task hierarchy when another task hierarchy completes.
However, Ferdinand teaches:
after the GPU have completed performing the one or more operations of the first graph (see e.g. Ferdinand, paragraph 24: “ dependency graph may include multiple nodes, each node corresponding to a different set of processes to be executed, in which the order of the nodes is non-cyclical, and in which execution of a set of processes represented by a first node in the graph begins after completion of a set of processes represented by a second node”).
Yildiz and Ferdinand are analogous art because they are in the same field of endeavor: managing graph executions. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Yildiz with the teachings of Ferdinand. The motivation/suggestion would be to improve graph processing efficiency.
With respect to claim 13, Yildiz as modified teaches: The system of claim 10, wherein the at least two graphs comprise a first graph (see e.g. Yildiz, paragraph 48: “FIG. 3 illustrates an example task hierarchy 300. Task hierarchy 200 depicts a two level task hierarchy”; and Fig. 3) and
Yildiz does not but Ferdinand teaches:
a condition (see e.g. Ferdinand, paragraph 24: “ completion of a set of processes”), and
the at least one GPU further launches another instance of the first graph based at least in part on whether the condition is satisfied (see e.g. Ferdinand, paragraph 24: “ dependency graph may include multiple nodes, each node corresponding to a different set of processes to be executed, in which the order of the nodes is non-cyclical, and in which execution of a set of processes represented by a first node in the graph begins after completion of a set of processes represented by a second node”).
Yildiz and Ferdinand are analogous art because they are in the same field of endeavor: managing graph executions. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Yildiz with the teachings of Ferdinand. The motivation/suggestion would be to improve graph processing efficiency.
With respect to claim 14: Claim 14 is directed to a system comprising one or more processors comprising at least one Graphics Processing Unit (“GPU”) corresponding to the GPU disclosed in claim 5; please see the rejection directed to claim 5 above which also covers the limitations recited in claim 14.
With respect to claim 27: Claim 27 is directed to a method corresponding to the active functions implemented by the GPU disclosed in claim 13; please see the rejection directed to claim 13 above which also covers the limitations recited in claim 27.
Response to Arguments
Applicant's arguments filed 12/09/2025 have been fully considered but they are not persuasive. In detail:
(i) Regarding Applicant’s arguments with respect to the objections directed to the abstract (Remarks, pages 8-9), note that MPEP §608.01(b) states:
The abstract should be in narrative form and generally limited to a single paragraph preferably within the range of 50 to 150 words in length. The abstract should not exceed 15 lines of text. Abstracts exceeding 15 lines of text or 150 words should be checked to see that they are as concise as the disclosure permits.
As such, the Examiner maintains the objections directed to the abstract of the disclosure. For more details, please see the Specification section above.
Applicant’s arguments with respect to claim(s) 1, 4-10, 13-20, and 25-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
More specifically, even though Yildiz discloses processing units 104A-D launching and executing at least two graphs (see e.g. Yildiz, paragraphs 25, 48; Fig. 3), Yildiz does not explicitly disclose these processing units being “graphics” processing units and the graphs being “instantiated by a host processor”.
However, Asthana discloses a GPU launching and executing graphs constructed/instantiated by a host CPU (see e.g. Asthana, column 5, lines 28-63).
As such, claims are rejected under 35 USC §103 as being obvious over Yildiz in view of Asthana. For more details, please see the corresponding rejections above.
Allowable Subject Matter
Claims 2-3, 11-12, and 21-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art references do not explicitly disclose a first graph causing a GPU to launch a second graph without any actions to launch the second graph to be initiated by a host processor as recited in claims 2, 11, and 21.
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Rao et al. (US 2016/0093012 A1) discloses graph processing between parent and child kernels of a GPU without any intervention from a host (see paragraphs 111-112).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Umut Onat whose telephone number is (571)270-1735. The examiner can normally be reached M-Th 9:00-7:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin L Young can be reached at (571) 270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/UMUT ONAT/Primary Examiner, Art Unit 2194