DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 11/07/2022. Claims 1-20 are currently pending, of which claims 1-20 are currently rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations “a first group of buffers coupled to the systolic array, wherein the first group comprises one or more first buffers; a second group of buffers coupled to the systolic array, wherein the second group comprises one or more second buffers; … a third group of buffers coupled to the accumulator, wherein the third group comprises one or more third buffers.” It is unclear how a group of buffers can comprise only one buffer. For purposes of prior art rejection, it will be interpreted as more than one buffer.
Claims 2-17 inherit the same deficiency by reason of dependence. They are rejected for the same reason as claim 1.
Claim 18 recites the same limitation as claim 1, and is rejected for the same reason as claim 1.
Claim 19 inherits the same deficiency by reason of dependence. It is rejected for the same reason as claim 18.
Claim 20 recites the same limitation as claim 1, and is rejected for the same reason as claim 1.
Additionally, Claim 6 recites the limitation “the second plurality of buffers are individually coupled to the second side or third side”. It is unclear how the second plurality of buffers can be coupled to both second or third side. For purposes of prior art rejections, Examiner interprets the second plurality of buffers to one of the second side or the third side.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (U.S. Patent Application Publication No.: US 20220138563 A1), hereinafter “Kwon”, in view of Zhang et al. (U.S. Patent Application Publication No.: US 20180314671 A1), hereinafter “Zhang”, further in view of Shin et al. (U.S. Patent Application Publication No.: US 20220317973 A1), hereinafter “Shin”, further in view of Lo et al. (U.S. Patent Application No.: US 20210382690 A1), hereinafter “Lo”.
Regarding Claim 1, Kwon teaches:
A processor (Abstract), comprising:
a systolic array of processing elements (Fig. 4, e.g., shows array of PEs);
a [global buffer] coupled to the systolic array (Fig. 4, e.g., shows global buffer 415 coupled to PE array), … ;
a [weight buffer] coupled to the systolic array (Fig. 4, e.g., shows weight buffer 425 coupled to PE array), … ;
an accumulator coupled to the systolic array (Fig. 4, e.g., shows output accumulators 440); …
Kwon does not teach:
a first group of buffers coupled to the systolic array, wherein the first group comprises one or more first buffers;
a second group of buffers coupled to the systolic array, wherein the second group comprises one or more second buffers;
a third group of buffers coupled to the accumulator, wherein the third group comprises one or more third buffers.
However, Zhang teaches:
a first group of buffers coupled to the systolic array, wherein the first group comprises one or more first buffers (Fig. 2, e.g., shows input buffers 202, 204, 206, 208);
a second group of buffers coupled to the systolic array, wherein the second group comprises one or more second buffers (Fig. 2, e.g., shows weight buffers 218, 228, 238, 248);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the input buffers and weight buffers as taught by Zhang with Global Buffer and Weight buffer as taught by Kwon, respectively. One would have been motivated to combine these references because both references disclose using buffers for inputs for a systolic array, and Zhang enhances the model of Kwon by allowing for each input value to be stored in a respective buffer. Zhang explains “Once a data block is fetched from off-chip memory, it is stored in input buffers such as input buffer 202, and weight buffers such as weight buffer 218, for data reuse.” (Zhang: ¶0048)
Kwon in view of Zhang do not teach:
a third group of buffers coupled to the accumulator, wherein the third group comprises one or more third buffers.
However, Shin teaches:
a third group of [storage elements] coupled to the accumulator (Fig. 6, e.g., shows accumulator coupled to storage elements), wherein the third group comprises one or more [storage elements] (Fig. 7, e.g., shows storage elements receiving output from accumulators).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the output accumulators 440 as taught by Kwon in view of Zhang with the accumulators including output storage elements and accumulators as taught by Shin. One would have been motivated to combine these references because both references disclose using output buffers for multiply-accumulate operations, and Shin enhances the model of Kwon in view of Zhang by allowing for output storage elements to store respective accumulated outputs.
Shin does not explicitly teach these storage elements functioning as buffers. However, Lo teaches using accumulator buffers to obtain a sum, and feed back the sum to a summer (accumulator). Lo explains “the pipeline 210 may include a multiplier 212 that multiplies the arguments 206, 208 to produce a product and a summer 214 that adds the product to contents of an accumulation buffer 216 to obtain a sum and writes the sum to the accumulation buffer 216.” See Lo: ¶0030 and Fig. 2.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the storage elements as taught by Shin with the accumulation buffers as taught by Lo. One would have been motivated to combine these references because both references disclose multiply-accumulate computations using storage elements, and Lo enhances the model of Kwon in view of Zhang in view of Shin by allowing for buffers to temporarily store accumulated outputs before being fed back to accumulators.
Regarding Claim 2, Kwon in view of Zhang in view of Shin in view of Lo teach:
The processor of claim 1, wherein the processor is a central processing unit (CPU) (Kwon: ¶0091).
Regarding Claim 3, Kwon in view of Zhang in view of Shin in view of Lo teach:
The processor of claim 1, wherein:
the first group comprises two buffers (Zhang: Fig. 2, e.g., shows input buffers 202, 204, 206, 208), the second group comprises two buffers (Zhang: Fig. 2, e.g., shows weight buffers 218, 228, 238, 248), and the third group comprises four buffers (Shin: Fig. 7, e.g., shows four storage elements; Lo: Fig. 2, e.g., buffers are used to store accumulated values).
The motivation to combine provided with respect to claim 1 applies equally to claim 3.
Regarding Claim 4, Kwon in view of Zhang in view of Shin in view of Lo teach:
The processor of claim 1, wherein:
the first group comprises a first plurality of buffers individually coupled to the systolic array (Zhang: Fig. 2, e.g., shows input buffers 202, 204, 206, 208 individually coupled to each Processing Element); and
the second group comprises a second plurality of buffers individually coupled to the systolic array (Zhang: Fig. 2, e.g., shows weight buffers 218, 228, 238, 248 individually coupled to each Processing Element).
The motivation to combine provided with respect to claim 1 applies equally to claim 4.
Regarding Claim 5, Kwon in view of Zhang in view of Shin in view of Lo teach:
The processor of claim 4, wherein:
the systolic array is a two-dimensional array (Kwon: ¶0078, e.g., PEs are two-dimensionally arranged);
the two-dimensional array corresponds to a first side, a second side, a third side opposite to the first side, and a fourth side opposite to the second side (Kwon: Fig. 4, e.g., shows left side of PE array (first side), upper side of PE array (second side), Right side of PE array (third side), and lower side of PE array (fourth side)); and
the first plurality of buffers are individually coupled to the first side and not coupled to the second side, the third side, and the fourth side (Kwon: Fig. 4, e.g., Global buffer is coupled to the right side (first side); Zhang: Fig. 2, e.g., shows input buffers 202, 204, 206, 208 individually coupled to each Processing Element).
The motivation to combine provided with respect to claim 1 applies equally to claim 5.
Regarding Claim 6, Kwon in view of Zhang in view of Shin in view of Lo teach:
The processor of claim 5, wherein:
the second plurality of buffers are individually coupled to the second side or third side and not coupled to the first side and the fourth side (Kwon: Fig. 4, e.g., upper side of PE array (second side) is coupled to weight buffer; Zhang: Fig. 2, e.g., shows weight buffers 218, 228, 238, 248 individually coupled to each Processing Element).
The motivation to combine provided with respect to claim 1 applies equally to claim 6.
Regarding Claim 7, Kwon in view of Zhang in view of Shin in view of Lo teach:
The processor of claim 5, wherein:
the accumulator is coupled to the fourth side and not coupled to the first side, the second side, and the third side (Kwon: Fig. 4, e.g., shows output accumulators coupled to the lower side of PE array (fourth side)).
Regarding Claim 18, Kwon in view of Zhang in view of Shin in view of Lo teach:
A computing device, comprising a memory and a processor coupled to the memory, wherein the processor comprises:
a systolic array of processing elements (Kwon: Fig. 4, e.g., shows systolic array 430);
a first group of buffers coupled to the systolic array, wherein the first group comprises one or more first buffers configured to pipeline first input data into the systolic array (Kwon: Fig. 4, e.g., shows Global buffer coupled to systolic array; Zhang: Fig. 2, e.g., shows input buffers 202, 204, 206, 208 individually coupled to each Processing Element; Zhang: ¶0070, e.g., systolic array is fully pipelined);
a second group of buffers coupled to the systolic array, wherein the second group comprises one or more second buffers configured to broadcast weight data into the systolic array (Kwon: Fig. 4, e.g., shows weight buffer coupled to systolic array; Zhang: Fig. 2, e.g., shows weight buffers 218, 228, 238, 248 individually coupled to each Processing Element);
an accumulator coupled to the systolic array and configured to receive output data from the systolic array (Kwon: Fig. 4, e.g., shows output accumulators 440 receiving outputs from systolic array); and
a third group of buffers comprising one or more third buffers configured to transmit second input data to the accumulator via a first pathway of a data transmission loop and receive results from the accumulator via a second pathway of the data transmission loop (Shin: Fig. 6, e.g., shows storage elements receiving data from accumulators (first pathway), and storage elements inputting data to accumulators (second pathway); Lo: Fig. 2, e.g., buffers are used to store accumulated values).
The motivation to combine provided with respect to claim 1 applies equally to claim 18.
With regards to Claim 20, this is a method version of the claimed processor above (claim 1), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Claims 8-12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Zhang in view of Shin in view of Lo, further in view of Wang et al. (U.S. Patent Application Publication No.: US 20210334142 A1), hereinafter “Wang”.
Regarding Claim 8, Kwon in view of Zhang in view of Shin in view of Lo teach:
The processor of claim 4, wherein:
the first plurality of buffers are individually coupled to one or more (main memory) of the processor (Kwon: Fig. 4, e.g., shows Global buffer coupled to main memory; Zhang: Fig. 2, e.g., shows input buffers; Kwon in view of Zhang would cause for the input buffers to be coupled to main memory); and
the second plurality of buffers are individually coupled to the one or more (main memory) of the processor (Kwon: Fig. 4, e.g., shows Weight buffer coupled to main memory; Zhang: Fig. 2, e.g., shows weight buffers; Kwon in view of Zhang would cause for the weight buffers to be coupled to main memory).
Kwon in view of Zhang in view of Shin in view of Lo do not teach:
the first plurality of buffers are individually coupled to one or more caches of the processor; and
the second plurality of buffers are individually coupled to the one or more caches of the processor.
However, in the same field of endeavor, Wang teaches how a host memory can act as a higher-level cache. Wang explains “Host memory 221 can be configured to store a large amount of data with slower access speed, compared to the on-chip memory integrated within accelerator chip, acting as a higher-level cache.” (Wang: ¶0040)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the main memory as taught by Kwon in view of Zhang in view of Shin in view of Lo to act as a higher-level cache as taught by Wang. One would have been motivated to combine these references because both references disclose using a main memory with systolic arrays, and Wang enhances the model of Kwon in view of Zhang in view of Shin in view of Lo by allowing for the main memory to act as a higher-level cache for faster processing.
Regarding Claim 9, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang teach:
The processor of claim 8, wherein:
the first plurality of buffers are configured to obtain first input data from the one or more caches of the processor and to transmit the first input data to the systolic array (Kwon: Fig. 4, e.g., Global Buffer receives data from Main Memory and is inputted to PE array; Zhang: Fig. 2, e.g., shows input buffers; Wang: ¶0040, e.g., Host memory can act as a higher-level cache); and
the first plurality of buffers are configured to, in parallel and staggered in time, each transmit a portion of the first input data the systolic array (Kwon: Fig. 4, e.g., each PE is coupled in parallel to lines transmitting input data; ¶0093, e.g., systolic array receives inputs based on clock signals; Zhang: Fig. 2, e.g., input buffers are connected to each PE in parallel).
The motivation to combine provided with respect to claim 8 applies equally to claim 9.
Regarding Claim 10, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang teach:
The processor of claim 9, wherein:
the second plurality of buffers are configured to obtain weight data from the one or more caches of the processor and to [load] the weight data into the systolic array (Kwon: Fig. 4, e.g., Weight buffer receives data from Main Memory and is inputted to PE array; Zhang: Fig. 2, e.g., shows weight buffers; Wang: ¶0040, e.g., Host memory can act as a higher-level cache).
Wang further teaches:
and to preload the weight data into the systolic array (Wang: ¶0068, e.g., weights are preloaded into the array)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the loading of weight data into the systolic array as taught by Kwon in view of Zhang in view of Shin in view of Lo in view of Wang to pre load weight data into the systolic array as taught by Wang. One would have been motivated perform this modification using these references because both references disclose loading data into systolic arrays, and Wang enhances the model of Kwon in view of Zhang in view of Shin in view of Lo in view of Wang by allowing for the weight memory to remain stationary throughout the computation. See Wang: ¶0068
Regarding Claim 11, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang teach:
The processor of claim 10, wherein:
the systolic array is configured to compute based on the first input data and the weight data and to, in parallel and staggered in time, transmit output data to the accumulator (Kwon: Fig. 4, e.g., each PE is coupled in parallel to lines transmitting input data and weight data. Systolic array outputs data to output accumulators; ¶0093, e.g., systolic array receives inputs based on clock signals; Zhang: Fig. 2, e.g., input buffers and weight buffers transmit data to each PE in parallel).
The motivation to combine provided with respect to claim 8 applies equally to claim 11.
Regarding Claim 12, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang teach:
The processor of claim 4, wherein:
the third group comprises a third plurality of buffers coupled to (i) the accumulator and (ii) one or more caches of the processor (Kwon: Fig. 4, e.g., Output accumulators are coupled to main memory; Wang: ¶0040, e.g., Host memory can act as a higher-level cache; Shin: Fig. 6, e.g., shows storage elements coupled to accumulators; Lo: Fig. 2, e.g., buffers are used to store accumulated values).
The motivation to combine provided with respect to claim 8 applies equally to claim 12.
Regarding Claim 19, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang teach:
The computing device of claim 18, wherein the third group of buffers are coupled to a cache of the processor (Kwon: Fig. 4, e.g., shows output accumulators coupled to main memory; Wang: ¶0040, e.g., Host memory can act as a higher-level cache).
Claims 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Zhang in view of Shin in view of Lo in view of Wang, further in view of Stratify Labs in NPL: “A FIFO Buffer Implementation” (blog.stratifylabs.dev/device/2013-10-02-A-FIFO-Buffer-Implementation/), hereinafter “Labs”
Regarding Claim 13, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang teach:
The processor of claim 12, wherein:
the first plurality of buffers are coupled in parallel to the systolic array (Kwon: Fig. 4, e.g., each PE is coupled in parallel to lines transmitting input data from global buffer; Zhang: Fig. 2, e.g., input buffers are coupled to each PE in parallel);
the second plurality of buffers are coupled in parallel to the systolic array (Kwon: Fig. 4, e.g., each PE is coupled in parallel to lines transmitting weight data from weight buffer; Zhang: Fig. 2, e.g., weight buffers are coupled to each PE in parallel);
the third plurality of buffers … (Shin: Fig. 6, e.g., shows storage elements storing accumulated data; Lo: Fig. 2, e.g., buffers are used to store accumulated values); and
the third plurality of buffers and the accumulator form a loop (Shin: Fig. 6, e.g., Outputs from storage elements are fed back to accumulators; Lo: Fig. 2, e.g., buffers are used to store accumulated values).
The motivation to combine provided with respect to claim 1 applies equally to claim 13.
Kwon in view of Zhang in view of Shin in view of Lo in view of Wang do not teach:
the third plurality of buffers are connected in series within the third group;
However, Labs teaches a FIFO Buffer that uses an array of contiguous memory to store data. Labs explains “A FIFO buffer is a type of data storage that operates on a first-in, first-out basis. It typically uses an array of contiguous memory to store data” (Labs: Second paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the accumulator buffer as taught by Lo to be a FIFO buffer including a serial storage of data as taught by Labs. One would have been motivated to combine these references because both references disclose buffering of data, and Labs enhances the model of Kwon in view of Zhang in view of Shin in view of Lo in view of Wang because “A FIFO buffer is a useful way to store data that arrives at a microcontroller peripheral asynchronously but cannot be read immediately.” (Labs: First paragraph).
Regarding Claim 17, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang teach:
The processor of claim 13, wherein:
the first plurality of buffers are configured to obtain a first matrix A and feed the first matrix A to the systolic array (Kwon: Fig. 1C, e.g., input data is represented by a matrix; Fig. 4, e.g., input data is fed to the systolic array from the global buffer; Zhang: Fig. 2, e.g., input buffers are coupled to each PE);
the second plurality of buffers are configured to obtain a second matrix B and feed the second matrix B to the systolic array (Kwon: Fig. 1C, e.g., weight data is represented by a matrix; Fig. 4, e.g., weight data is fed to the systolic array from the global buffer; Zhang: Fig. 2, e.g., weight buffers are coupled to each PE);
the systolic array is configured to multiply the first matrix A and the second matrix B to output A*B to the accumulator (Kwon: ¶0068, e.g., PEs perform multiplication operation);
the accumulator is configured to obtain a third matrix C from the third plurality of buffers and generate a result of A*B + C through a plurality of loops of recursive calculations (Kwon: Fig. 4, e.g., outputs of the systolic array are fed to output accumulators; Shin: Fig. 6, e.g., storage element outputs are fed back to accumulators; Lo: Fig. 2, e.g., buffers are used to store accumulated values); and
the third plurality of buffers are configured to obtain and output the result of A*B + C (Shin: Fig. 6, e.g., storage elements obtain multiplied-accumulated outputs; Lo: Fig. 2, e.g., buffers are used to store accumulated values).
The motivation to combine provided with respect to claim 1 applies equally to claim 17.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Zhang in view of Shin in view of Lo in view of Wang in view of Labs, further in view of Kim et al. (U.S. Patent Application Publication No.: US 20180129935 A1), hereinafter “Kim”.
Regarding Claim 14, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang in view of Labs teach:
The processor of claim 13, wherein:
the third plurality of buffers are configured to:
obtain second input data from [the accumulators] (Shin: Fig. 6, e.g., storage elements storing accumulated data), and
transmit the second input data to the accumulator (Shin: Fig. 6, e.g., Outputs from storage elements are fed back to accumulators); and
the accumulator is configured to:
recursively generate an intermediary result based on output data from the systolic array and the second input data (Shin: Fig. 6, e.g., Outputs from storage elements are fed back to accumulators and added with systolic array outputs), and
transmit the intermediary result to the third plurality of buffers (Shin: Fig. 6, e.g., Outputs from accumulators (intermediary result) are stored in storage elements).
Kwon in view of Zhang in view of Shin in view of Wang in view of Labs do not teach:
the third plurality of buffers are configured to:
obtain second input data from the one or more caches of the processor,
However, in the same field of endeavor, Kim teaches using an external memory to store output data from output buffers, and is also configured to load output data Dout_T back to output buffers to update results from convolution computations. Kim explains “The output buffer device 130 may load the part Dout_T of the output data of the convolution computation or pooling operation executed by the MAC computator 120. The part Dout_T of the output data, which is loaded to the output buffer device 130, may be updated according to an execution result of each convolution computation loop by the plurality of kernels.” Kim: ¶0069.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the main memory acting as a higher-level cache as taught by Kwon in view of Zhang in view of Shin in view of Lo in view of Wang in view of Labs to also provide output data back to output buffers as taught by Kim. One would have been motivated to perform this modification using these references because both references disclose performing multiply-accumulate operations using output buffers for accumulation, and Kim enhances the model of Kwon in view of Zhang in view of Shin in view of Lo in view of Wang in view of Labs by allowing for results to be updated based on pervious output data. See Kim: ¶0069
Regarding Claim 15, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang in view of Labs in view of Kim teach:
The processor of claim 14, wherein:
the third plurality of buffers are configured to feedback the intermediary result to the accumulator (Shin: Fig. 6, e.g., Outputs from accumulators (intermediary result) are stored in storage elements; Lo: Fig. 2, e.g., buffers are used to store accumulated values); and
the accumulator is configured to recursively update the intermediary result based on the output data and the feedback intermediary result and transmit the updated intermediary result to the third plurality of buffers (Shin: Fig. 6, e.g., Outputs from storage elements are fed back to accumulators and added with systolic array outputs (updated); Lo: Fig. 2, e.g., buffers are used to store accumulated values).
The motivation to combine provided with respect to claim 14 applies equally to claim 15.
Regarding Claim 16, Kwon in view of Zhang in view of Shin in view of Lo in view of Wang in view of Labs in view of Kim teach:
The processor of claim 15, wherein the third plurality of buffers are configured to:
each store a last updated intermediary result (Shin: Fig. 6, e.g., storage elements store results from accumulators; Lo: Fig. 2, e.g., buffers are used to store accumulated values); and
output a final result comprising the last updated intermediary results to the one or more caches of the processor (Kwon: Fig. 4, e.g., output accumulators output results to main memory; Wang: ¶0040, e.g., memory can act as a higher-level cache).
The motivation to combine provided with respect to claim 14 applies equally to claim 16.
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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