DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 12/22/2025. Claims 1-20 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 11/08/2022 is acceptable.
Election/Restrictions
Applicant’s election, without traverse species I, (claims 1-8, 10, 12-14 and 18-20), in the “Response to Election / Restriction Filed” filed on 04/28/2025 is acknowledged. This office action considers claims 1-20 are thus pending for prosecution of which, non-elected claims 9, 11 and 15-17 are withdrawn, and elected claims 1-8, 10, 12-14 and 18-20 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 7-8, 10, 12-14, 18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhu et al (US 2023/0062141 A1; hereafter Zhu).
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Zhu Fig. [6A].
Regarding claim 1. Zhu discloses a semiconductor structure comprising:
a dynamic random access memory (DRAM) cell (Fig. [6A], DRAM cells 624, Para [ 0084]) comprising a plurality of field effect transistors (FETs) (Fig. [6A], gate 636, Para [ 0082, 0094]) and a plurality of DRAM capacitors (capacitors 628, Para [ 0088, 0094]); and at least one bitline (Fig 6A, bit line 623, Para [ 0078, 0107]) composed of an electrically conductive metal-containing material (Fig 6A, bit line 623, Para [ 0078]) located on a backside of the DRAM cell (Fig. [6], DRAM cells 624, Para [ 0084]).
Regarding claim 3. Zhu discloses the semiconductor structure of Claim 1, Zhu further discloses wherein each DRAM capacitor of the plurality of DRAM capacitors is a stacked capacitor (capacitors 628, Para [ 0088, 0094]).
Regarding claim 4. Zhu discloses the semiconductor structure of Claim 1, Zhu further discloses further comprising:
a backside back-end-of-the-line (BEOL) structure (bit line contacts 625, Para [ 0078]) contacting the at least one bitline (Fig 6, bit line 623, Para [ 0078]), wherein the backside BEOL structure is a backside power distribution network (Para [ 0078, 0227]).
Regarding claim 5. Zhu discloses the semiconductor structure of Claim 1, Zhu further discloses wherein each FET of the plurality of FETs is a vertical FET (Fig. [6A], gate 636, Para [ 0073, 0082, 0094]) comprising a vertical semiconductor channel material structure ( semiconductor body 630, Para [ 0081]), a gate structure (gate structure 636, Para [ 0081]) located on each side of the vertical semiconductor channel material structure ( semiconductor body 630, Para [ 0081]), a first source/drain region (source and drain 638, Para [ 0082]) located at a first end of the vertical semiconductor channel material structure ( semiconductor body 630, Para [ 0081]) and a second source/drain region (source and drain 638, Para [ 0082]) located at a second end of the vertical semiconductor channel material structure which is opposite the first end of the vertical semiconductor channel material structure ( semiconductor body 630, Para [ 0081]).
Regarding claim 7. Zhu discloses the semiconductor structure of Claim 5, Zhu further discloses further comprising:
a frontside source/drain contact (capacitor contact 642, Para [ 0087]) structure contacting the first source/drain region (source and drain 638, Para [ 0082]), and connecting the first source/drain region to one DRAM capacitor (capacitor 628, Para [ 0087]) of the plurality of DRAM capacitors (capacitors 628, Para [ 0087]).
Regarding claim 8. Zhu discloses the semiconductor structure of Claim 7, Zhu further discloses wherein the at least one bitline is in direct contact with the second source/drain region (Para [ 0082] discloses “one of source and drain 638 (e.g., at the upper end in FIG. 6A) is coupled to capacitor 628, and the other one of source and drain 638 (e.g., at the lower end in FIG. 6A) is coupled to bit line 623 (e.g., through bit line contact 625 or directly).
Regarding claim 10. Zhu discloses the semiconductor structure of Claim 5, Zhu further discloses wherein both the first source/drain region (Fig 6A, source and drain 638, Para [ 0081-0083]) and the second source/drain region have a non-faceted surface (source and drain 638, Para [ 0081-0083]), the non-faceted surface is opposite a surface of the first source/drain region (source and drain 638, Para [ 0082-0083]) and the second source/drain region (source and drain 638, Para [ 0082-0083]) that contacts the vertical semiconductor channel material structure ( semiconductor body 630, Para [ 0081-0083]).
Regarding claim 12. Zhu discloses the semiconductor structure of Claim 1, Zhu further discloses wherein each DRAM capacitor of the plurality of DRAM capacitors (capacitors 628, Para [ 0087-0088]) is embedded in a frontside back-end-of-the-line (BEOL) structure (Fig. [6], DRAM cells 624, Para [ 0084]).
Regarding claim 13. Zhu discloses the semiconductor structure of Claim 12, Zhu further discloses further comprising: a carrier wafer (substrate 648, Para [ 0091]) located on the frontside back-end-of-the-line (BEOL) structure (Fig. [6], DRAM cells 624, Para [ 0084]).
Regarding claim 14. Zhu discloses the semiconductor structure of Claim 13, Zhu further discloses wherein the carrier wafer (substrate 648, Para [ 0091]) is spaced apart from each DRAM capacitor (capacitors 628, Para [ 0087-0088]) of the plurality of DRAM capacitors (capacitors 628, Para [ 0087-0088]) by a portion of the frontside BEOL structure (Fig. [6A], DRAM cells 624, Para [ 0084]).
Regarding claim 18. Zhu discloses the semiconductor structure of Claim 1, Zhu further discloses wherein each FET comprises a gate structure (gate structure 636, Para [ 0094]) located on each side of a vertical semiconductor channel material structure ( semiconductor body 630, Para [ 0081]), wherein the gate structure comprises a gate dielectric material layer (gate dielectric 632, Para [ 0081]) in direct contact with a sidewall of the vertical semiconductor channel material structure ( semiconductor body 630, Para [ 0081]), and a gate electrode located laterally adjacent to the gate dielectric material layer, wherein the gate electrode (gate electrode 634, Para [ 0081]) comprises at least a work function metal layer (Para [ 0084]).
Regarding claim 20. Zhu discloses the semiconductor structure of Claim 18, Zhu further discloses further comprising: a first dielectric spacer located on a surface of the gate structure and contacting the sidewall of the vertical semiconductor channel material structure (Para [ 0087] discloses “ ILD layer in which capacitors 628 are formed has the same dielectric material as the two ILD layers into which semiconductor body 630 extends, such as silicon oxide”), and a second dielectric spacer located on another surface of the gate structure and contacting the sidewall of the vertical semiconductor channel material structure (region 622, Para [ 0078]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al (US 2023/0062141 A1; hereafter Zhu) as applied claims above and further in view of Uchiyama et al (US 2010/0237397 A1; hereafter Uchiyama).
Regarding claim 2. Zhu discloses the semiconductor structure of Claim 1, But, Zhu does not disclose explicitly wherein the DRAM cell has a unit cell area defined as 4F2, wherein F is equal to a gate half pitch.
In a similar field of endeavor, Uchiyama discloses wherein the DRAM cell has a unit cell area defined as 4F2, wherein F is equal to a gate half pitch (Para [0006, 0010, 0059]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Zhu in light of Uchiyama teaching “wherein the DRAM cell has a unit cell area defined as 4F2, wherein F is equal to a gate half pitch (Para [0006, 0010, 0059])” for further advantage such as cell area of 4F.sup.2 at minimum can be achieved, and to achieve further downscaling.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al (US 2023/0062141 A1; hereafter Zhu) as applied claims above and further in view of TSAI et al (US 2022/0068924 A1; hereafter TSAI).
Regarding claim 6. Zhu discloses the semiconductor structure of Claim 5, But, Zhu does not disclose explicitly wherein the vertical semiconductor channel material structure, the first source/drain region and the second source/drain region are of unitary construction and are composed of a same semiconductor material.
In a similar field of endeavor, Uchiyama discloses wherein the vertical semiconductor channel material structure, the first source/drain region and the second source/drain region are of unitary construction and are composed of a same semiconductor material (Para [0063] discloses “the first source/drain region 142, the second source/drain region 144, and the channel 146 include the same material”, Fig 1).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Zhu in light of Uchiyama teaching “wherein the DRAM cell has a unit cell area defined as 4F2, wherein F is equal to a gate half pitch (Para [0006, 0010, 0059], Fig 1)” for further advantage such as electrically connect the source/drain regions to one another through the channel.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al (US 2023/0062141 A1; hereafter Zhu) as applied claims above and further in view of Yang (US 2004/0061190 A1; hereafter Yang).
Regarding claim 19. Zhu discloses the semiconductor structure of Claim 18, But, Zhu does not disclose explicitly further comprising:
a gate polysilicon layer positioned between the gate dielectric material layer and the gate electrode.
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In a similar field of endeavor, Yang discloses a gate polysilicon layer positioned between the gate dielectric material layer and the gate electrode (Fig 1, Para [0011]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Zhu in light of Yang teaching “a gate polysilicon layer positioned between the gate dielectric material layer and the gate electrode (Fig 1, Para [0011])” for further advantage such as to improve device performance and reduce oxidation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898