Prosecution Insights
Last updated: July 17, 2026
Application No. 17/983,226

BARRIER ENABLED CUF AND MOLD PROCESS FOR MULTI-CHIP PACKAGING

Final Rejection §103
Filed
Nov 08, 2022
Examiner
FOX, BRANDON C
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
698 granted / 812 resolved
+18.0% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
834
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
84.3%
+44.3% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 812 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a Final Office action based on application 17/983,226 in response to reply filed March 31, 2026. Claims 1-27 are currently pending and have been considered below. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 8-10, & 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu (Pre-Grant Publication 2014/0160688) in view of Lin (Pre-Grant Publication 2018/0342466). Regarding claim 1, Lu disclose an electronic package comprising: a die (Fig. 3, 131); an array of pillars (Fig. 2c, 1131/1132) adjacent to the die wherein pillars (1131/1132) can be formed around the die as discontinuous segments such as shown in Fig. 2b (Paragraph [0040]); and an underfill (123) under the die, wherein an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die (Fig. 3), and wherein the edge of the underfill has a height that is less than a maximum height of the underfill (Fig. 3). Lu does not disclose the edge of the underfill is spaced apart from the inner column of pillars. However Lin discloses a semiconductor device comprising: A under fill (Fig. 4b, 26) formed under and around a semiconductor die (21) wherein the underfill is spaced away from a inner pillar (30) (Paragraph [0027]). It would have been obvious to those having ordinary skill in the art at the time of invention to form the underfill spaced apart from the pillar because it will serve to alleviate warpage in the substrate, reduced underfill crack, and alleviate cold joint or bump crack of conductors (Paragraph [0027]). Regarding claim 2, Lu further discloses: the edge of the underfill has a height that is less than a height of the array of pillars (Fig. 3). Regarding claim 8, Lu further discloses: Connector (139) can be used to connect electronic package (200) to a board/PCB to form a computing system (Paragraph [0036]). Regarding claim 9, Lu discloses a electronics package comprising: a package substrate (Fig. 3, 100); a first die (131) on the package substrate; an array of pillars (1131/1132) adjacent to the first die wherein pillars (1131/1132) can be formed around the die as discontinuous segments such as shown in Fig. 2b (Paragraph [0040]); a second die (306) over the pillars and the first die; and an underfill (123) between the first die and the array of pillars, wherein the underfill has a non-vertical sidewall (Fig. 3), and wherein the sidewall has a height that is less than a maximum height of the underfill (Fig. 3). Lu does not disclose the edge of the underfill is spaced apart from the inner column of pillars. However Lin discloses a semiconductor device comprising: A under fill (Fig. 4b, 26) formed under and around a semiconductor die (21) wherein the underfill is spaced away from a inner pillar (30) (Paragraph [0027]). It would have been obvious to those having ordinary skill in the art at the time of invention to form the underfill spaced apart from the pillar because it will serve to alleviate warpage in the substrate, reduced underfill crack, and alleviate cold joint or bump crack of conductors (Paragraph [0027]). Regarding claim 10, Lu further discloses: The underfill is at a bottom of the first die (Fig. 3). Regarding claim 23, Lu discloses a electronics package comprising: a board/PCB (Paragraph [0036]); a package substrate (100) coupled to the board; and a multi-die module coupled to the package substrate, wherein the multi-die module comprises: a first die (131); an array of columns (1131/1132) adjacent to the first die wherein pillars (1131/1132) can be formed around the die as discontinuous segments such as shown in Fig. 2b (Paragraph [0040]); a second die (306) over the first die; and an underfill (123), wherein an edge of the underfill is provided between the first die and the array of columns (Fig. 3), and wherein the edge of the underfill is non-vertical and wherein the edge of the underfill has a height that is less than a maximum height of the underfill (Fig. 3). Lu does not disclose the edge of the underfill is spaced apart from the inner column of pillars. However Lin discloses a semiconductor device comprising: A under fill (Fig. 4b, 26) formed under and around a semiconductor die (21) wherein the underfill is spaced away from a inner pillar (30) (Paragraph [0027]). It would have been obvious to those having ordinary skill in the art at the time of invention to form the underfill spaced apart from the pillar because it will serve to alleviate warpage in the substrate, reduced underfill crack, and alleviate cold joint or bump crack of conductors (Paragraph [0027]). Allowable Subject Matter Claims 19-22 & 26-27 are allowed. The following is an examiner’s statement of reasons for allowance: Claim 19 is allowed because none of the prior art either alone or in combination discloses a die; an array of pillars adjacent to the die; a barrier layer set into the array of pillars; and an underfill between the die and the barrier layer, wherein the underfill conforms to the shape of the barrier layer. Claims 20-22 are also allowed based on their dependency from claim 19. Claim 26 is allowed because none of the prior art either alone or in combination discloses an electronic package comprising: a die; an array of pillars adjacent to the die; and an underfill under the die, wherein an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, wherein the edge of the underfill has a height that is less than a maximum height of the underfill, and wherein the edge of the underfill undercuts a top surface of the underfill. Claim 27 is allowed because none of the prior art either alone or in combination discloses an electronic package comprising: a die; an array of pillars adjacent to the die; an underfill under the die, wherein an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and wherein the edge of the underfill has a height that is less than a maximum height of the underfill; and a barrier provided in the array of pillars, wherein the underfill contacts the barrier. Claims 3-7, 11-18, & 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 3 is considered allowable because none of the prior art either alone or in combination discloses the edge of the underfill undercuts a top surface of the underfill. Claim 4 is considered allowable because none of the prior art either alone or in combination discloses a barrier provided in the array of pillars, wherein the underfill contacts the barrier. Claims 5-7 are also allowable based on their dependency from claim 4. Claim 11 is considered allowable because none of the prior art either alone or in combination discloses the underfill is at a top of the first die, and wherein the underfill contacts the second die. Claim 12 is considered allowable because none of the prior art either alone or in combination discloses the non-vertical sidewall undercuts a bottom surface and/or a top surface of the underfill. Claim 13 is considered allowable because none of the prior art either alone or in combination discloses a barrier layer in the array of pillars. Claims 14-18 are also allowable based on their dependency from claim 13. Claim 24 is considered allowable because none of the prior art either alone or in combination discloses the edge of the underfill undercuts a top surface and/or a bottom surface of the underfill. Claim 25 is considered allowable because none of the prior art either alone or in combination discloses the underfill contacts the second die. Response to Arguments Applicant’s arguments with respect to claim(s) 1, 9 & 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRANDON C FOX/Examiner, Art Unit 2818 /DAVID VU/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Nov 08, 2022
Application Filed
Jul 25, 2023
Response after Non-Final Action
Dec 31, 2025
Non-Final Rejection mailed — §103
Mar 31, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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METHOD FOR MANUFACTURING, BY DIFFERENTIATED ELECTROCHEMICAL POROSIFICATION, A GROWTH SUBSTRATE INCLUDING MESAS HAVING VARIOUS POROSIFICATION LEVELS
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Patent 12652885
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
96%
With Interview (+9.7%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 812 resolved cases by this examiner. Grant probability derived from career allowance rate.

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