DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the REPUBLIC OF TAIWAN on 06/09/2022.
Election/Restrictions
Applicant’s election without traverse of “Species D - Claims 1-6 and 10” in the reply filed on Jul 7, 2025, is acknowledged. Claims 7-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2015/0349495 A1; Kinugawa et al.; 12/2015; (“495”).
Regarding Claim 1. 495 teaches in Fig. 2A about a manufacturing method of a semiconductor device, comprising:
providing a semiconductor stack layer (item 15), wherein the semiconductor stack layer comprises a first type semiconductor layer (item 7), a quantum well layer (item 10b), and a second type semiconductor layer (item 12) stacked in sequence;
growing an aluminum nitride layer (item 16, “depositing a dielectric film made of …
AlNx, … on the topmost surface of the semiconductor layer structure before the annealing”, [0395], Ln. 7-12) on the second type semiconductor layer; and
annealing ([0395], Ln. 12) the aluminum nitride layer to achieve quantum well intermixing (“a semiconductor layer structure with different degrees of disordering may also be achieved by uniformly depositing a dielectric film made of … AlNx”, [0395], Ln. 5-8, disordering is a broader term encompassing any process that disrupts an ordered quantum well structure, in this claimed invention thermal interdiffusion or mixing occurs due to the annealing process; therefore, quantum well intermixing is achieved).
Regarding Claim 2. 495 teaches in Fig. 2A about a manufacturing method of a semiconductor device, wherein the semiconductor stack layer further comprises:
a first waveguide layer (item 8), disposed between the quantum well layer and the first type semiconductor layer; and
a second waveguide layer (item 11), disposed between the quantum well layer and the second type semiconductor layer, wherein the semiconductor stack layer forms a semiconductor laser structure (“FIG. 2A is a cross-sectional view along the x-y plane in the semiconductor laser element illustrated in FIG. 1”, [0142], Ln. 1-2).
Regarding Claim 3. 495 teaches in Figs. 1, 2A, and 2B about a manufacturing method of a semiconductor device, wherein the quantum well layer comprises a light-exiting side (Fig. 2B, item 2) and a reflecting side (Fig. 2B, item 3) opposite to each other (Fig. 2B, items 2 and 3 are opposite to each other), and an arrangement direction of the light-exiting side and the reflecting side (Fig.1, arrangement of items 2 and 3 is in the z-direction) is perpendicular to a stacking direction of the semiconductor stack layer (Figs. 2A or 2B, semiconductor stack is arranged in the y-direction).
Regarding Claim 6. 495 teaches in Fig. 1 about a manufacturing method of a semiconductor device, further comprising:
forming a reflective coating (item 3) on a first side of the semiconductor stack layer, wherein the reflecting side is located on the first side (item L, does not exit from side item 3); and
forming an anti-reflection coating (item 2) on a second side of the semiconductor stack layer, wherein the light-exiting side is located on the second side (item L, does exit from side item 2).
Regarding Claim 10. 495 teaches in Fig. 2A about a manufacturing method of a semiconductor device, further comprising:
forming a first electrode (lower electrode, item 4), wherein the first electrode is electrically connected (electrically connected through layer items 5 and 6) to the first type semiconductor layer; and
forming a second electrode (upper electrode, item 17) on the aluminum nitride layer, and electrically connecting the second electrode to the second type semiconductor layer (electrically connected through aluminum nitride layer item 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being obvious over 2015/0349495 A1; Kinugawa et al.; 12/2015; (“495”) in view of 2017/0062652 A1; Imai; 03/2017; (“652”).
Regarding Claim 4. 495 teaches in Fig. 25 about a manufacturing method of a semiconductor device, wherein the annealing the aluminum nitride layer comprises:
differences between the degrees of disordering and between the band gap energies in the non-window region 15a and the window region 15b are increased, and as a result, a smaller amount of laser light is absorbed at the facet, and the risk of COD is reduced ([0191], Ln. 7-12).
495 does not teach about a manufacturing method of a semiconductor device, wherein the annealing the aluminum nitride layer comprises:
heating a portion of the aluminum nitride layer located above the light-exiting side with a laser beam.
652 teaches in [0089] about a manufacturing method of a semiconductor device, wherein “laser annealing is a technology that allows local annealing on the basis of a thermal effect provided by laser irradiation. A desired area can be annealed by scanning the area with a laser beam” ([0089], Ln 1-4).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the method that allows local annealing on the basis of a thermal effect provided by laser irradiation of 652 for the method of reducing the amount of laser light that is absorbed at the facet in 495 in order to locally “suppress reabsorption of the light in the quantum well (active layer 106), whereby COD damage at the first end surface 162 (light-exiting side) of the optical waveguide 160 can be suppressed.” as taught by 652 in Figs. 1-3, [0058], Ln. 3-6.
Regarding Claim 5. 652 teaches in Fig. 25 about a manufacturing method of a semiconductor device, wherein when a portion of the aluminum nitride layer located above the light-exiting side is heated by the laser beam, a band gap of the portion of the quantum well layer at the light-exiting side increases (“the band gap of the window section 4 can be wider than the band gap of the active layer 106”, Fig. 2, [0059], Ln. 10-12), to form a non-absorbing mirror structure (“window section 4 can therefore suppress reabsorption of the light in the quantum well (active layer 106), whereby COD damage at the first end surface 162 of the optical waveguide 160 can be suppressed”). Non-absorbing mirror structures are a theoretical idea; therefore, a light-exiting side with an increased band gap compared to the band gap of the laser resonant cavity is considered a non-absorbing mirror for the purposes of claim examination.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897