DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 01/29/2026 is acknowledged.
Claims 3-4 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II-VI, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/29/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5-7, and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim 5 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim 5 recites “first to third terminals” is indefinite and unclear whether there is a terminal is included or not included. As best understood, the examine will interpret as “first, second, and third terminals”.
Claim 6 recites “first to third terminals” is indefinite and unclear whether there is a terminal is included or not included. As best understood, the examine will interpret as “first, second, and third terminals”.
Claim 7 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim 10 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim 17 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim 18 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim 19 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim 19 recites “first to third terminals” is indefinite and unclear whether there is a terminal is included or not included. As best understood, the examine will interpret as “first, second, and third terminals”.
Claim 20 recites “the first to third spiral-shaped coil patterns” is indefinite and unclear whether the second spiral-shaped coil pattern is included or not included. As best understood, the examine will interpret as “the first, second, and third spiral-shaped coil patterns”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-7, and 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. [KR 10-1216946 B1].
Regarding Claim 1 (1st interpretation), Kim et al. shows an on-chip inductor (Figs. 1-4), comprising:
a semiconductor substrate (110);
a plurality of insulating layers (130, 140, 150) stacked over the semiconductor substrate (see Figs. 1-4);
first (PSI2), second (PSI3) and third (PSI4) spiral-shaped coil patterns inductively coupled to each other (see Figs. 1-4, elements PSI2, PSI3, and PSI4 inductively coupled to each other) and sequentially disposed on respective layers among the plurality of insulating layers (see Figs. 1-4), wherein the first, second and third spiral-shaped coil patterns have respective first ends (inner ends of elements PSI2, PSI3, and PSI4) overlapping each other (see Figs. 1-4, inner ends of elements PSI2, PSI3, and PSI4 are overlapping each other at elements 134, 144 and/or element IVV);
a first via (134) connecting the respective first ends of the first and second spiral-shaped coil patterns to each other (see Figs. 1-4, element 134 connecting inner ends of elements PSI2 and PSI3); and
a second via (144) connecting the respective first ends of the second and third spiral-shaped coil patterns to each other (see Figs. 1-4, element 144 connecting inner ends of elements PSI3 and PSI4),
wherein the first and second vias overlap each other (see Figs. 1-4, elements 134, 144 overlap each other).
Regarding Claim 2, Kim et al. shows the first to third spiral-shaped coil patterns spiral outwardly from the respective first ends (see Figs. 1-4, elements PSI2, PSI3, and PSI4 spiral outwardly from the respective inner ends).
Regarding Claim 5, Kim et al. shows respective second ends (outer ends of elements PSI2, PSI3, and PSI4) of the first to third spiral-shaped coil patterns form first to third terminals (see Figs. 1-4, outer ends of elements PSI2, PSI3, and PSI4 form first, second, and third terminals which will connect to element OVV).
Regarding Claim 6, Kim et al. shows the first to third terminals do not overlap each other (see Figs. 1-4, first, second, and third terminals of respective elements PSI2, PSI3, and PSI4 do not overlap each other in the left-right direction or x-axis direction).
Regarding Claim 7, Kim et al. shows each of the first to third spiral-shaped coil patterns is a spiral inductor (see Figs. 1-4, each of elements PSI2, PSI3, and PSI4 is a spiral inductor).
Regarding Claim 10, Kim et al. shows the first (134) and second (144) vias form a common node for connecting the respective first ends of the first to third spiral-shaped coil patterns in common (see Fig. 1-4, elements 134, 144 form a common node for connecting the respective inner ends of elements PSI2, PSI3, and PSI4 in common, Paragraph [0008], claim 1).
Regarding Claim 11, Kim et al. shows the semiconductor substrate is a silicon on insulator (SOI) substrate (Paragraph [0006]).
Regarding Claim 12, Kim et al. shows an on-chip inductor (Figs. 1-4), comprising:
a plurality of insulating layers (130, 140, 150, 132, 142);
at least three spiral-shaped coil patterns (PSI2, PSI3, and PSI4) inductively coupled to each other (see Figs. 1-4, elements PSI2, PSI3, and PSI4 inductively coupled to each other) and respectively disposed on the plurality of insulating layers (see Figs. 1-4), wherein the at least three spiral-shaped coil patterns have respective first ends (inner ends of elements PSI2, PSI3, and PSI4) aligned with each other in a vertical direction (see Figs. 1-4, inner ends of elements PSI2, PSI3, and PSI4 aligned with each other in a vertical direction at elements 134, 144 and/or element IVV); and
vias (134, 144) penetrating through at least one insulating layer (132, 142) among the plurality of insulating layers to connect the respective first ends of the at least three spiral-shaped coil patterns and disposed to overlap each other (see Figs. 1-4, elements 134, 144 connect respective inner ends of elements PSI2, PSI3, and PSI4 and disposed to overlap each other).
Regarding Claim 13, Kim et al. shows the at least three spiral-shaped coil patterns spiral outwardly from the respective first ends (see Figs. 1-4, elements PSI2, PSI3, and PSI4 spiral outwardly from the respective inner ends).
Regarding Claim 14, Kim et al. shows the plurality of insulating layers comprise at least three insulating layers (130, 140, 150, 132, 142).
Regarding Claim 15, Kim et al. shows the plurality of insulating layers (130, 140, 150, 132, 142) are stacked on a silicon on insulator (SOI) substrate (Paragraph [0006]).
Regarding Claim 16, Kim et al. shows the vias (134, 144) form a common node for connecting the respective first ends of the at least three spiral-shaped coil patterns in common (see Fig. 1-4, elements 134, 144 form a common node for connecting the respective inner ends of elements PSI2, PSI3, and PSI4 in common, Paragraph [0008], claim 1).
Regarding Claim 17, Kim et al. shows an on-chip inductor (Figs. 1-4), comprising:
a semiconductor substrate (110);
a multilayer interconnection layer (130, 140, 150) stacked on the semiconductor substrate (see Figs. 1-4) in one direction (top-bottom direction or y-axis direction);
first (PSI2), second (PSI3) and third (PSI4) spiral-shaped coil patterns inductively coupled to each other (see Figs. 1-4, elements PSI2, PSI3, and PSI4 inductively coupled to each other) and sequentially disposed on respective layers of the multilayer interconnection layer (see Figs. 1-4), wherein the first, second and third spiral-shaped coil patterns have respective first ends (inner ends of elements PSI2, PSI3, and PSI4) overlapping in the one direction (see Figs. 1-4, inner ends of elements PSI2, PSI3, and PSI4 are overlapping in top-bottom direction or y-axis direction at elements 134, 144 and/or element IVV);
a first via (134) connecting the respective first ends of the first and second spiral-shaped coil patterns to each other (see Figs. 1-4, element 134 connecting inner ends of elements PSI2 and PSI3); and
a second via (144) connecting the respective first ends of the second and third spiral-shaped coil patterns to each other (see Figs. 1-4, element 144 connecting inner ends of elements PSI3 and PSI4),
wherein the first and second vias are disposed to overlap in the one direction (see Figs. 1-4, elements 134, 144 overlap in top-bottom direction or y-axis direction), and form a common node electrically connecting the respective first ends of the first to third spiral-shaped coil patterns in common (see Fig. 1-4, elements 134, 144 form a common node for connecting the respective inner ends of elements PSI2, PSI3, and PSI4 in common, Paragraph [0008], claim 1).
Regarding Claim 18, Kim et al. shows the first to third spiral-shaped coil patterns spiral outwardly from the respective first ends (see Figs. 1-4, elements PSI2, PSI3, and PSI4 spiral outwardly from the respective inner ends).
Regarding Claim 19, Kim et al. shows respective second ends (outer ends of elements PSI2, PSI3, and PSI4) of the first to third spiral-shaped coil patterns form first to third terminals (see Figs. 1-4, outer ends of elements PSI2, PSI3, and PSI4 form first, second, and third terminals which will connect to element OVV), the first to third terminals not overlapping each other (see Figs. 1-4, first, second, and third terminals of respective elements PSI2, PSI3, and PSI4 do not overlap each other in the left-right direction or x-axis direction).
Regarding Claim 20, Kim et al. shows each of the first to third spiral-shaped coil patterns is a spiral inductor (see Figs. 1-4, each of elements PSI2, PSI3, and PSI4 is a spiral inductor).
Claim(s) 1-2, 5-8, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. [10-1216946 B1] (another interpretation).
Regarding Claim 1 (2nd interpretation), Kim et al. shows an on-chip inductor (Figs. 1-4), comprising:
a semiconductor substrate (110);
a plurality of insulating layers (150, 140, 130) stacked over the semiconductor substrate (see Figs. 1-4);
first (PSI4), second (PSI3) and third (PSI2) spiral-shaped coil patterns inductively coupled to each other (see Figs. 1-4, elements PSI4, PSI3, and PSI2 inductively coupled to each other) and sequentially disposed on respective layers among the plurality of insulating layers (see Figs. 1-4), wherein the first, second and third spiral-shaped coil patterns have respective first ends (inner ends of elements PSI4, PSI3, and PSI2) overlapping each other (see Figs. 1-4, inner ends of elements PSI4, PSI3, and PSI2 are overlapping each other at elements 144, 134 and/or element IVV);
a first via (144) connecting the respective first ends of the first and second spiral-shaped coil patterns to each other (see Figs. 1-4, element 144 connecting inner ends of elements PSI4 and PSI3); and
a second via (134) connecting the respective first ends of the second and third spiral-shaped coil patterns to each other (see Figs. 1-4, element 134 connecting inner ends of elements PSI3 and PSI2),
wherein the first and second vias overlap each other (see Figs. 1-4, elements 144, 134 overlap each other).
Regarding Claim 2, Kim et al. shows the first to third spiral-shaped coil patterns spiral outwardly from the respective first ends (see Figs. 1-4, elements PSI4, PSI3, and PSI2 spiral outwardly from the respective inner ends).
Regarding Claim 5, Kim et al. shows respective second ends (outer ends of elements PSI4, PSI3, and PSI2) of the first to third spiral-shaped coil patterns form first to third terminals (see Figs. 1-4, outer ends of elements PSI4, PSI3, and PSI2 form first, second, and third terminals which will connect to element OVV).
Regarding Claim 6, Kim et al. shows the first to third terminals do not overlap each other (see Figs. 1-4, first, second, and third terminals of respective elements PSI4, PSI3, and PSI2 do not overlap each other in the left-right direction or x-axis direction).
Regarding Claim 7, Kim et al. shows each of the first to third spiral-shaped coil patterns is a spiral inductor (see Figs. 1-4, each of elements PSI4, PSI3, and PSI2 is a spiral inductor).
Regarding Claim 8, Kim et al. shows the third spiral-shaped coil pattern (PSI2) is disposed at a level higher than that of the first (PSI4) and second (PSI3) spiral-shaped coil patterns (see Figs. 1-4, element PSI2 is disposed at a level higher than elements PSI4, PSI3), and a line width (W2) of the third spiral-shaped coil pattern (PSI2) is greater than a line width (W4) of the first spiral-shaped coil pattern (PSI4) and a line width (W3) of the second spiral-shaped coil pattern (PSI3, see Figs. 1-4, Paragraph [0037], claim 1).
Regarding Claim 10, Kim et al. shows the first (144) and second (134) vias form a common node for connecting the respective first ends of the first to third spiral-shaped coil patterns in common (see Fig. 1-4, elements 144, 134 form a common node for connecting the respective inner ends of elements PSI4, PSI3, and PSI2 in common, Paragraph [0008], claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Yamauchi et al. [U.S. Pub. No. 2015/0028988].
Regarding Claim 8, Kim et al. in the 1st interpretation shows the claimed invention as applied above but does not show the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern.
Yamauchi et al. shows an inductor (Fig. 5) teaching and suggesting the third spiral-shaped coil pattern (32a) is disposed at a level higher than that of the first (32c) and second (32b) spiral-shaped coil patterns (see Fig. 5), and a line width of the third spiral-shaped coil pattern (32a) is greater than a line width of the first spiral-shaped coil pattern (32c) and a line width of the second spiral-shaped coil pattern (32b, see Fig. 5, a line width of element 32a is greater than a line width of element 32c and a line width of element 32b, Paragraphs [0044]-[0045]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern as taught by Yamauchi et al. for the inductor as disclosed by Kim et al. to facilitate mechanical stability and reliability such as the stress applied to the insulating layers can be more weakened and risk of delamination can be diminished (Paragraph [0045]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Lee [U.S. Patent No. 7,317,354].
Regarding Claim 8, Kim et al. in the 1st interpretation shows the claimed invention as applied above but does not show the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern.
Lee shows an inductor (Figs. 7-15) teaching and suggesting the third spiral-shaped coil pattern (54 or 63) is disposed at a level higher than that of the first (52 or 61) and second (53 or 62) spiral-shaped coil patterns (see Figs. 7-15), and a line width of the third spiral-shaped coil pattern (54 or 63) is greater than a line width of the first spiral-shaped coil pattern (52 or 61) and a line width of the second spiral-shaped coil pattern (53 or 62, see Figs. 7-15, a line width of element 54 or 63 is greater than a line width of element 52 or 61 and a line width of element 53 or 62).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern as taught by Lee for the inductor as disclosed by Kim et al. to provide an inductor with high quality factor to reduce the influence of eddy current of the substrate and parasitic capacitance between the inductor and the substrate on the quality factor, and improve efficiency and quality (Col. 1, Lines 40-45).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Maruyama [U.S. Patent No. 7,126,451].
Regarding Claim 9, Kim et al. shows the claimed invention as applied above but does not show the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a thickness of the third spiral-shaped coil pattern is greater than a thickness of the first spiral-shaped coil pattern and a thickness of the second spiral-shaped coil pattern.
Maruyama shows a coil device (Figs. 8-9) teaching and suggesting the third spiral-shaped coil pattern (21-7) is disposed at a level higher than that of the first (21-5) and second (21-6) spiral-shaped coil patterns, and a thickness of the third spiral-shaped coil pattern (21-7) is greater than a thickness of the first spiral-shaped coil pattern (21-5) and a thickness of the second spiral-shaped coil pattern (21-6, see Figs. 8-9, a thickness of element 21-7 is greater than a thickness of element 21-5 and a thickness of element 21-6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a thickness of the third spiral-shaped coil pattern is greater than a thickness of the first spiral-shaped coil pattern and a thickness of the second spiral-shaped coil pattern as taught by Maruyama for the inductor as disclosed by Kim et al. to have the coil be enhanced in the processing properties and precision of processing and further yield of material of the conductive flat plate is enhanced, resulting in improvement of conductivity and reduction of manufacturing cost (Col. 10, Lines 23-35).
Claim(s) 11 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Barry et al. [U.S. Pub. No. 2015/0028979].
Regarding Claim 11, Kim et al. shows the claimed invention as applied above.
Barry et al. shows a device (Figs. 5 or 9) teaching and suggesting the semiconductor substrate (110) is a silicon on insulator (SOI) substrate (Paragraphs [0051], [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the semiconductor substrate is a silicon on insulator (SOI) substrate as taught by Barry et al. for the inductor as disclosed by Kim et al. to offer less capacitance to structures formed thereon and permits use of lower metal layers for use in inductors to achieve desirable operating characteristics (Paragraphs [0051], [0057]).
Regarding Claim 15, Kim et al. shows the claimed invention as applied above.
Barry et al. shows a device (Figs. 5 or 9) teaching and suggesting the plurality of insulating layers are stacked on a silicon on insulator (SOI) substrate (Paragraphs [0051], [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of insulating layers are stacked on a silicon on insulator (SOI) substrate as taught by Barry et al. for the inductor as disclosed by Kim et al. to offer less capacitance to structures formed thereon and permits use of lower metal layers for use in inductors to achieve desirable operating characteristics (Paragraphs [0051], [0057]).
Claim(s) 1-2, 5-7, 10, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. [U.S. Pub. No. 2017/0345548] in view of Kim et al. [KR 10-1216946 B1].
Regarding Claim 1, Yu et al. shows an on-chip inductor (Figs. 1A-1D), comprising:
a plurality of insulating layers (102, 106, 110);
first (112), second (114) and third (116) spiral-shaped coil patterns inductively coupled to each other (see Figs. 1A-1D, elements 112, 114, and 116 inductively coupled to each other) and sequentially disposed on respective layers among the plurality of insulating layers (see Figs. 1A-1D), wherein the first, second and third spiral-shaped coil patterns have respective first ends (inner ends of elements 112, 114, and 116) overlapping each other (see Figs. 1A-1D, inner ends of elements 112, 114, and 116 are overlapping each other at elements 134, 138 and/or element CB);
a first via (134) connecting the respective first ends of the first and second spiral-shaped coil patterns to each other (see Figs. 1A-1D, element 134 connecting inner ends of elements 112 and 114); and
a second via (138) connecting the respective first ends of the second and third spiral-shaped coil patterns to each other (see Figs. 1A-1D, element 138 connecting inner ends of elements 114 and 116),
wherein the first and second vias overlap each other (see Figs. 1A-1D, elements 134, 138 overlap each other).
Yu et al. does not explicitly show a semiconductor substrate and a plurality of insulating layers stacked over the semiconductor substrate.
Kim et al. shows an on-chip inductor (Figs. 1-4) teaching and suggesting a semiconductor substrate (110); and a plurality of insulating layers (130, 140, 150) stacked over the semiconductor substrate (see Figs. 1-4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a semiconductor substrate and a plurality of insulating layers stacked over the semiconductor substrate as taught by Kim et al. for the inductor as disclosed by Yu et al. to facilitate mechanical stability and reliability to achieve desirable operating characteristics useful for monolithic semiconductor integrated circuit device incorporating high-frequency analog circuit and a digital signal processing circuit having excellent Q factor characteristics (Paragraph [0044]).
Regarding Claim 2, Yu et al. shows the first to third spiral-shaped coil patterns spiral outwardly from the respective first ends (see Figs. 1A-1D, elements 112, 114, and 116 spiral outwardly from the respective inner ends).
Regarding Claim 5, Yu et al. shows respective second ends (outer ends of elements 112, 114, and 116) of the first to third spiral-shaped coil patterns form first to third terminals (see Figs. 1A-1D, outer ends of elements 112, 114, and 116 form first, second, and third terminals).
Regarding Claim 6, Yu et al. shows the first to third terminals do not overlap each other (see Figs. 1A-1D, first, second, and third terminals of respective elements 112, 114, and 116 do not overlap each other in the top-bottom direction or y-axis direction and left-right direction or x-axis direction).
Regarding Claim 7, Yu et al. shows each of the first to third spiral-shaped coil patterns is a spiral inductor (see Figs. 1A-1D, each of elements 112, 114, and 116 is a spiral inductor).
Regarding Claim 10, Yu et al. shows the first (134) and second (138) vias form a common node for connecting the respective first ends of the first to third spiral-shaped coil patterns in common (see Fig. 1A-1D, elements 134, 138 form a common node such as common terminal CB for connecting the respective inner ends of elements 112, 114, and 116 in common, Paragraphs [0016]-[0017], [0020]).
Regarding Claim 17, Yu et al. shows an on-chip inductor (Figs. 1A-1D), comprising:
a multilayer interconnection layer (102, 106, 110) stacked in one direction (top-bottom direction or y-axis direction);
first (112), second (114) and third (116) spiral-shaped coil patterns inductively coupled to each other (see Figs. 1A-1D, elements 112, 114, and 116 inductively coupled to each other) and sequentially disposed on respective layers of the multilayer interconnection layer (see Figs. 1A-1D), wherein the first, second and third spiral-shaped coil patterns have respective first ends (inner ends of elements 112, 114, and 116) overlapping in the one direction (see Figs. 1A-1D, inner ends of elements 112, 114, and 116 are overlapping in top-bottom direction or y-axis direction at elements 134, 138 and/or element CB);
a first via (134) connecting the respective first ends of the first and second spiral-shaped coil patterns to each other (see Figs. 1A-1D, element 134 connecting inner ends of elements 112 and 114); and
a second via (138) connecting the respective first ends of the second and third spiral-shaped coil patterns to each other (see Figs. 1A-1D, element 138 connecting inner ends of elements 114 and 116),
wherein the first and second vias are disposed to overlap in the one direction (see Figs. 1A-1D, elements 134, 138 overlap in top-bottom direction or y-axis direction), and form a common node electrically connecting the respective first ends of the first to third spiral-shaped coil patterns in common (see Fig. 1A-1D, elements 134, 138 form a common node such as common terminal CB for connecting the respective inner ends of elements 112, 114, and 116 in common, Paragraphs [0016]-[0017], [0020]).
Yu et al. does not explicitly show a semiconductor substrate and a multilayer interconnection layer stacked on the semiconductor substrate in one direction.
Kim et al. shows an on-chip inductor (Figs. 1-4) teaching and suggesting a semiconductor substrate (110); and a multilayer interconnection layer (130, 140, 150) stacked on the semiconductor substrate (see Figs. 1-4) in one direction (top-bottom direction or y-axis direction).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a semiconductor substrate and a multilayer interconnection layer stacked on the semiconductor substrate in one direction as taught by Kim et al. for the inductor as disclosed by Yu et al. to facilitate mechanical stability and reliability to achieve desirable operating characteristics useful for monolithic semiconductor integrated circuit device incorporating high-frequency analog circuit and a digital signal processing circuit having excellent Q factor characteristics (Paragraph [0044]).
Regarding Claim 18, Yu et al. shows the first to third spiral-shaped coil patterns spiral outwardly from the respective first ends (see Figs. 1A-1D, elements 112, 114, and 116 spiral outwardly from the respective inner ends).
Regarding Claim 19, Yu et al. shows respective second ends (outer ends of elements 112, 114, and 116) of the first to third spiral-shaped coil patterns form first to third terminals (see Figs. 1A-1D, outer ends of elements 112, 114, and 116 form first, second, and third terminals), the first to third terminals not overlapping each other (see Figs. 1A-1D, first, second, and third terminals of respective elements 112, 114, and 116 do not overlap each other in the top-bottom direction or y-axis direction and left-right direction or x-axis direction).
Regarding Claim 20, Yu et al. shows each of the first to third spiral-shaped coil patterns is a spiral inductor (see Figs. 1A-1D, each of elements 112, 114, and 116 is a spiral inductor).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Kim et al. as applied to claim 1 above, and further in view of Yamauchi et al. [U.S. Pub. No. 2015/0028988].
Regarding Claim 8, Yu et al. in view of Kim et al. shows the claimed invention as applied above but does not show the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern.
Yamauchi et al. shows an inductor (Fig. 5) teaching and suggesting the third spiral-shaped coil pattern (32a) is disposed at a level higher than that of the first (32c) and second (32b) spiral-shaped coil patterns (see Fig. 5), and a line width of the third spiral-shaped coil pattern (32a) is greater than a line width of the first spiral-shaped coil pattern (32c) and a line width of the second spiral-shaped coil pattern (32b, see Fig. 5, a line width of element 32a is greater than a line width of element 32c and a line width of element 32b, Paragraphs [0044]-[0045]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern as taught by Yamauchi et al. for the inductor as disclosed by Yu et al. in view of Kim et al. to facilitate mechanical stability and reliability such as the stress applied to the insulating layers can be more weakened and risk of delamination can be diminished (Paragraph [0045]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Kim et al. as applied to claim 1 above, and further in view of Lee [U.S. Patent No. 7,317,354].
Regarding Claim 8, Yu et al. in view of Kim et al. shows the claimed invention as applied above but does not show the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern.
Lee shows an inductor (Figs. 7-15) teaching and suggesting the third spiral-shaped coil pattern (54 or 63) is disposed at a level higher than that of the first (52 or 61) and second (53 or 62) spiral-shaped coil patterns (see Figs. 7-15), and a line width of the third spiral-shaped coil pattern (54 or 63) is greater than a line width of the first spiral-shaped coil pattern (52 or 61) and a line width of the second spiral-shaped coil pattern (53 or 62, see Figs. 7-15, a line width of element 54 or 63 is greater than a line width of element 52 or 61 and a line width of element 53 or 62).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a line width of the third spiral-shaped coil pattern is greater than a line width of the first spiral-shaped coil pattern and a line width of the second spiral-shaped coil pattern as taught by Lee for the inductor as disclosed by Yu et al. in view of Kim et al. to provide an inductor with high quality factor to reduce the influence of eddy current of the substrate and parasitic capacitance between the inductor and the substrate on the quality factor, and improve efficiency and quality (Col. 1, Lines 40-45).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Kim et al. as applied to claim 1 above, and further in view of Maruyama [U.S. Patent No. 7,126,451].
Regarding Claim 9, Yu et al. in view of Kim et al. shows the claimed invention as applied above but does not show the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a thickness of the third spiral-shaped coil pattern is greater than a thickness of the first spiral-shaped coil pattern and a thickness of the second spiral-shaped coil pattern.
Maruyama shows a coil device (Figs. 8-9) teaching and suggesting the third spiral-shaped coil pattern (21-7) is disposed at a level higher than that of the first (21-5) and second (21-6) spiral-shaped coil patterns, and a thickness of the third spiral-shaped coil pattern (21-7) is greater than a thickness of the first spiral-shaped coil pattern (21-5) and a thickness of the second spiral-shaped coil pattern (21-6, see Figs. 8-9, a thickness of element 21-7 is greater than a thickness of element 21-5 and a thickness of element 21-6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the third spiral-shaped coil pattern is disposed at a level higher than that of the first and second spiral-shaped coil patterns, and a thickness of the third spiral-shaped coil pattern is greater than a thickness of the first spiral-shaped coil pattern and a thickness of the second spiral-shaped coil pattern as taught by Maruyama for the inductor as disclosed by Yu et al. in view of Kim et al. to have the coil be enhanced in the processing properties and precision of processing and further yield of material of the conductive flat plate is enhanced, resulting in improvement of conductivity and reduction of manufacturing cost (Col. 10, Lines 23-35).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Kim et al. as applied to claim 1 above, and further in view of Barry et al. [U.S. Pub. No. 2015/0028979].
Regarding Claim 11, Yu et al. in view of Kim et al. shows the claimed invention as applied above but does not show the semiconductor substrate is a silicon on insulator (SOI) substrate.
Barry et al. shows a device (Figs. 5 or 9) teaching and suggesting the semiconductor substrate (110) is a silicon on insulator (SOI) substrate (Paragraphs [0051], [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the semiconductor substrate is a silicon on insulator (SOI) substrate as taught by Barry et al. for the inductor as disclosed by Yu et al. in view of Kim et al. to offer less capacitance to structures formed thereon and permits use of lower metal layers for use in inductors to achieve desirable operating characteristics (Paragraphs [0051], [0057]).
Claim(s) 12-14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. [U.S. Pub. No. 2017/0345548] in view of Yosui et al. [WO 2015/037374].
Regarding Claim 12, Yu et al. shows an on-chip inductor (Figs. 1A-1D), comprising:
a plurality of insulating layers (102, 106, 110, 104, 108);
at least three spiral-shaped coil patterns (112, 114, and 116) inductively coupled to each other (see Figs. 1A-1D, elements 112, 114, and 116 inductively coupled to each other) and respectively disposed on the plurality of insulating layers (see Figs. 1A-1D), wherein the at least three spiral-shaped coil patterns have respective first ends (inner ends of elements 112, 114, and 116) aligned with each other in a vertical direction (see Figs. 1A-1D, inner ends of elements 112, 114, and 116 aligned with each other in a vertical direction at elements 134, 138 and/or element CB); and
vias (134, 138) penetrating through at least one insulating layer (104, 108) among the plurality of insulating layers to connect the respective first ends of the at least three spiral-shaped coil patterns and disposed to overlap each other (see Figs. 1A-1D, elements 134, 138 connect respective inner ends of elements 112, 114, and 116 and disposed to overlap each other).
In addition, Yosui shows an inductor (Fig. 1) teaching and suggesting vias (63, 62) penetrating through at least one insulating layer (13, 12) among the plurality of insulating layers to connect the respective first ends of the at least three spiral-shaped coil patterns (see Fig. 1, elements 63, 62 connect respective inner ends of elements 23, 22, 21).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have vias penetrating through at least one insulating layer among the plurality of insulating layers to connect the respective first ends of the at least three spiral-shaped coil patterns as taught by Barry et al. for the inductor as disclosed by Yu et al. in view of Kim et al. to facilitate electrical connection and conductivity to achieve desirable inductance values and reduce manufacture cost and time.
Regarding Claim 13, Yu et al. shows the at least three spiral-shaped coil patterns spiral outwardly from the respective first ends (see Figs. 1A-1D, elements 112, 114, and 116 spiral outwardly from the respective inner ends).
Regarding Claim 14, Yu et al. shows the plurality of insulating layers comprise at least three insulating layers (102, 106, 110, 104, 108).
Regarding Claim 16, Yu et al. shows the vias (134, 138) form a common node for connecting the respective first ends of the at least three spiral-shaped coil patterns in common (see Fig. 1A-1D, elements 134, 138 form a common node such as common terminal CB for connecting the respective inner ends of elements 112, 114, and 116 in common, Paragraphs [0016]-[0017], [0020]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Yosui as applied to claim 12 above, and further in view of Barry et al. [U.S. Pub. No. 2015/0028979].
Regarding Claim 15, Yu et al. in view of Yosui shows the claimed invention as applied above but does not show the plurality of insulating layers are stacked on a silicon on insulator (SOI) substrate.
Barry et al. shows a device (Figs. 5 or 9) teaching and suggesting the plurality of insulating layers are stacked on a silicon on insulator (SOI) substrate (Paragraphs [0051], [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of insulating layers are stacked on a silicon on insulator (SOI) substrate as taught by Barry et al. for the inductor as disclosed by Yu et al. in view of Yosui to offer less capacitance to structures formed thereon and permits use of lower metal layers for use in inductors to achieve desirable operating characteristics (Paragraphs [0051], [0057]).
Conclusion
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837