DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 17/983,541, application filed on 11/09/2022.
3. Claims 1-10 are currently pending in this application.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 11/09/2022 and 02/21/2023, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dhanwada et al. (US PG Pub No. 2017/0351785) in view of Wu et al. (US PG Pub No. 2011/0131540).
7. With respect to independent claim 1, Dhanwada teaches:
A method of providing an early power estimate on a hierarchy designed chip (circuit analysis conducted at early stage to ensure designed timing and power constraints, para 25; early dynamic power calculation, para 26), “early” meaning after simulation on a logical hierarchy and hierarchy manipulation and prior to final placement and wiring of the chip (see early in design process, para 21; early stage, para 25; macro analysis of switching activity at high levels of logical design hierarchy, para 29), the process comprising:
recording switching activity on all ports in the logical hierarchy (determining switching of logic gates by analyzing activities and determining a switching factor, para 9; amount of physical switching of logic gates, para 10; determining the switching of gates or nets, para 26);
creating a physical hierarchy (see physical hierarchy, para 29-30);
mapping all ports in the physical hierarchy to ports in the logical hierarchy (mapping between logical and physical hierarchies, para 29-30);
calculating power on the chip using the switching activity on the ports in the logical hierarchy mapped to ports in the physical hierarchy (dynamic power calculation based on switching activity, par 26-27, 31-32; see analysis and workload database for logical hierarchy and logic function based on connections to gates/logic and each other, including connections to ports for gate-level and mapped transistor level, para 23); and
outputting the result of the power calculation (see output of power calculations at 140 of Fig 1, para 26, 29-31).
Dhanwada appears to be silent regarding:
simulating the logical hierarchy for functional correctness.
However, Wu teaches:
simulating the logical hierarchy for functional correctness (performing simulation, para 4; passing tests in design process, para 68; see logic design and functional verifications, design checked for functional accuracy, para 71).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Wu’s simulation and validation step into the invention of Dhanwada for at least the following reason(s): as Wu explains, validating functional accuracy early during the design process aids in reducing the amount of time and resources needed to improve IC design flow, which would be advantageous to Dhanwada, as both Wu and Dhanwada relate to improved IC design flow (see para 5-10 of Wu as it relates to improving design flow, and see Dhanwada, Abstract, as it relates to improving design flow for IC design/chips).
8. Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dhanwada et al. (US PG Pub No. 2017/0351785) in view of Wu et al. (US PG Pub No. 2011/0131540) and McGaughy (US PG Pub No. 2005/0143966).
9. With respect to claim 2, Dhanwada teaches:
The method of claim 1, the creating a physical hierarchy comprises:
creating one or more recipes for a hierarchy manipulation (see design hierarchy and mapping of logical and physical design, reconciling signal activity, corresponding to physical hierarchy, para 29), where the recipes instruct the hierarchy manipulation what to do (mapping hierarchies, para 29), the recipes may be manually generated or generated by EDA (Engineering Design Automation) tools (see various analysis tools such as design and optimization and closure tools, para 8; see CAD simulation tools, para 3).
Dhanwada/Wu appears to be silent regarding:
and creating one or more name data bases (NDBs) by the hierarchy manipulation, as a record of what the NDBs did in creating the physical hierarchy.
However, Wu teaches:
and creating one or more name data bases (NDBs) by the hierarchy manipulation (see NDB, name-defining data structures, para 24; see block structure naming, hierarchy visualization map, para 72), as a record of what the NDBs did in creating the physical hierarchy (additional data structure such as NDB’s recorded, para 91;see hierarchical arranged levels, para 88).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated McCaughy’s NDB’s into the hierarchy of Dhanwada/Wu for at least the following reason(s): work and workloads such as flattening hierarchical models and other tasks are made for efficient for simulation and modeling of behavior of IC for logical/physical IC design by enabling naming structure and database recording standards for IC design to track changes and improvements in the design.
10. With respect to claim 3, while Dhanwada/Wu is silent regarding the limitations below, McCaughy teaches:
The method of claim 2, when more than one NDB has been created, merging the NDBs into a merged NDB; otherwise, treat the single NDB as the merged NDB (see merging data structures, including merging NDB’s, para 26; NDB’s are merged, para 119). (For motivation to combine references, see rejection of claim 2 above).
Allowable Subject Matter
11. Claim 4, and claims 5-9 which depend therefrom, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. Claim 10 is allowed over the prior art of record.
13. With respect to claim 10, the prior art made of record fails to teach the combination of steps recited in claim 10, including the following particular combination of steps as recited in claim 10, as follows:
step 2: translating a port name in the physical hierarchy, using a name database created by the hierarchy manipulation, to a port name of an atomic block in the logical hierarchy;
step 3: when steps 1 and 2 cannot trace from the port in the physical hierarchy until hitting an atomic block port in the logical hierarchy, then tracing up in the logical hierarchy to a top level in the logical hierarchy;
iterating steps 1, 2, and 3 until all physical hierarchy ports are mapped to ports in the logical hierarchy where switching activity is recorded; and
using the mapping of ports from the physical hierarchy to ports in the logical hierarchy, using a switching activity from a simulation recorded in the simulation to the ports in the physical hierarchy to estimate power.
14. With respect to claim 4 (and claims 5-9 which depend therefrom), the prior art made of record fails to teach the combination of steps recited in claim 4, including the following particular combination of steps as recited in claim 4, as follows:
using the merged NDB, tracing ports in the physical hierarchy until an atomic block is encountered.
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851