Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-20 are pending in this application.
Applicant elected without traverse Species I (claims 1-10, and 14-19) in the reply filed on August 20, 2025.
Claims 11-13 and 20 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 20, 2025.
The Examiner notes that claims 1-10 and 14-19 are examined and claims 11-13 and 20 are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 15, 2025 is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed December 30, 2025. Claims 1 and 15 are amended. Claims 11-13 and 20 remain withdrawn. The Examiner notes that claims 1-10 and 14-19 are examined.
Specification
The substitute specification filed December 30, 2025 has been entered. All objections to the specification are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (CN 101546777 A) in view of Wang (US 2013/0240962 A1) and Batude (US 2021/0376185 A1).
With respect to claim 1, Gao teaches in Fig. 14:
A method for forming a CMOS image sensor, comprising:
forming a substrate (silicon substrate 01),
a plurality of photosensitive doped layers (N-type doped region 05 and P-type doped region 06 of photodiode 100) on the substrate (01)
an isolation layer (buried oxygen layer 02) on the plurality of photosensitive doped layers and an active layer (layer that includes silicon film 03, see annotated Fig. 14 below) on the isolation layer (02),
wherein the substrate comprises pixel areas (para. 6 “CMOS image sensors are composed of CMOS digital-analog circuits and photosensitive pixels”),
and each of the plurality of photosensitive doped layers (05 and 06) is disposed on each a pixel area;
forming an electrical device (transistor 200 that includes silicon film 03, source and drains 10, gate dielectric 08, and gate 09) in the active layer (03 and 10 are in the active layer) and on the active layer (08 and 09 are on the active layer);
and forming an interconnection structure in the isolation layer and the active layer (metal plugs 15b and 16a and interconnection metal 17b);
wherein the plurality of photosensitive doped layers (06 and 05) are electrically coupled with the electrical device by the interconnection structure (connected through 16a, 17b, and 15b).
Gao fails to teach:
wherein the substrate comprises a plurality of mutually discrete pixel areas,
and each of the plurality of photosensitive doped layers is disposed on each of the plurality of pixel areas respectively;
wherein a projection of the electrical device on the substrate is located in a projection of a corresponding one of the plurality of photosensitive doped layers on the substrate.
Wang teaches:
wherein the substrate (second substrate 20) comprises a plurality of mutually discrete pixel areas (The photosensitive array 21, including a plurality of photosensitive units on a same plane, is formed on the drive circuit array.),
and each of the plurality of photosensitive doped layers (para. 42, “photosensitive units are photo diodes which include a stack of a P-type doping layer and a N-type doping layer, or a stack of a P-type doping layer, an I-type layer and a N-type doping layer”) is disposed on each of the plurality of pixel areas respectively (area with one of the pixels of the photosensitive array, see annotated Fig. 10 below);
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Gao discloses the claimed invention except for the pixels being a plurality of discrete pixels with photosensitive layers deposited on each pixel. Wang teaches that it is known to include an array of a plurality of discrete photosensitive layer, each with a photosensitive layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gao to teach multiple discrete pixels as taught by Wang to increase the sensitivity of the sensing device and reduce crosstalk between neighboring pixels. See MPEP 2144.
Batude teaches in Fig. 9:
wherein a projection of the electrical device (MOS transistor M1) on the substrate (substrate 101) is located in a projection of a corresponding one of the plurality of photosensitive doped layers (N-type doped semiconductor layer 103, emissive layer 105, and/or P-type doped semiconductor layer 107) on the substrate (substrate 101).
Gao/Wang discloses the claimed invention except for a projection of the electrical device on a substrate being located inside a projection of the photosensitive doped layers. Batude teaches that it is known to arrange the electrical device directly above the photosensitive doped layers in order such that the projection of the transistor is within the projection of the doped layers on the substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gao/Wang to use the arrangement of Batude for the purpose of reducing the size of the footprint of the device. See MPEP 2144.
With respect to claim 2, Gao further teaches in Fig. 4a:
wherein forming the substrate (01), the plurality of photosensitive doped layers (05 and 06), the isolation layer (02) and the active layer (layer including 03, see annotated Fig. 14 above) comprises:
forming an initial substrate structure (structure shown in Fig. 5),
wherein the initial substrate structure comprises the substrate (01), an initial photosensitive doped layer on the substrate (05 and 06), the isolation layer on the initial photosensitive doped layer (02) and the active layer on the isolation layer (03);
Wang further teaches in Fig. 10-11:
and forming an isolation structure (isolating structures 26 and shallow trench isolating structures 11) in the initial substrate structure (second device layer 200),
wherein the isolation structure (26 and 11) penetrates through the initial photosensitive doped layer (photodiode layer 21),
and the isolation structure is disposed between adjacent pixel areas, so that the initial photosensitive doped layer forms the plurality of photosensitive doped layers (see annotated Fig. 10 above).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gao in view of Wang and Batude as explained above.
With respect to claim 3, Wang further teaches in Fig. 2:
wherein the isolation structure (26 and 11) also penetrates through the active layer (layer of device layer 100 that includes source and drains 14a and 14b).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gao in view of Wang and Batude as explained above.
With respect to claim 4, Gao further teaches:
providing an initial substrate (substrate 01)
injecting a first doping ion into the initial substrate to form the substrate and the initial photosensitive doped layer (para. 59 “Then, high energy phosphorus ions are implanted, for example, with an energy of 400-2000 keV and a dose of 1E12-5E13, to form the N-type doping region 05 of the photodiode 100. The P-type doped region 06 of the photodiode 100 is formed by implanting boron ions, for example, with an energy of 100-400 keV and a dose of 4E12-1E13.”);
forming the isolation layer (02) on the initial photosensitive doped layer (05 and 06);
and forming the active layer (layer that includes 03) on the isolation layer (02).
With respect to claim 5, Gao further teaches:
wherein forming the initial substrate structure comprises:
providing an initial substrate (structure of Fig. 4a), wherein the initial substrate comprises a base substrate (01), the isolation layer on the base substrate (02), and the active layer on the isolation layer (03);
and injecting a first doping ion into the base substrate to form the substrate and the initial photosensitive doped layer on the substrate. (para. 59 “Then, high energy phosphorus ions are implanted, for example, with an energy of 400-2000 keV and a dose of 1E12-5E13, to form the N-type doping region 05 of the photodiode 100. The P-type doped region 06 of the photodiode 100 is formed by implanting boron ions, for example, with an energy of 100-400 keV and a dose of 4E12-1E13.”);
With respect to claim 6, Wang further teaches:
wherein forming the initial photosensitive doped layer (photodiode layer 21, comprising heavily doped P-type silicon layer 21a, lightly doped P-type silicon layer 21b, and heavily doped N-type silicon layer 21C) comprises forming the initial photosensitive doped layer by an epitaxial growth process (para. 69 “A lightly-doped P-type silicon layer 21b is formed on the heavily-doped P-type silicon 21a using epitaxial growth”).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the epitaxial growth method of Wang for the implantation method of Gao while forming the doped photosensitive layer because the methods are known equivalents of forming doped semiconductors and it would have yielded the predictable result of forming a photosensitive doped layer. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 7, Gao further teaches:
wherein the electrical device comprises a gate structure (08 and 09) on the substrate (01) and a source drain region (10) respectively disposed in the active layer (layer that includes 03, see annotated Fig. 10 above) on two sides of the gate structure (08 and 09).
With respect to claim 8, Gao further teaches:
wherein the interconnection structure (15b, 16a, and 17b) comprises a first plug (15b) on the active layer (see annotated Fig. 10 above),
a second plug (16a) on one photosensitive doped layer (05 and 06) and an electrical coupling layer (17b) for coupling the first plug (15b) with the second plug (16a), and the first plug (15b) is electrically coupled with the electrical device (see Fig. 10).
With respect to claim 9, Gao further teaches:
wherein the interconnection structure is made of a material comprising metal (para. 63 Metal tungsten is deposited (including a protective thin layer on the sidewall and bottom of the tungsten plug, Ti or TiN or Ti/TiN, not shown), and metal plugs 15a, 15b, 16a, 16b are formed by chemical mechanical polishing or etching back.”)
With respect to claim 14, Gao further teaches:
wherein the plurality of photosensitive doped layers (05 and 06) are doped with N-type ions (N-type doping region 05), and the substrate is doped with P-type ions (para. 57 “The silicon substrate 01 can be P-type silicon, or can be P-type lightly doped silicon 01b epitaxially grown on P-type heavily doped silicon 01a;”).
With respect to claim 15, Gao teaches in Fig. 14:
A CMOS image sensor, comprising:
a substrate (silicon substrate 01),
a plurality of photosensitive doped layers (N-type doped region 05 and P-type doped region 06 of photodiode 100) on the substrate (01)
an isolation layer (buried oxygen layer 02) on the plurality of photosensitive doped layers and an active layer (layer that includes silicon film 03, see annotated Fig. 14 above) on the isolation layer (02),
wherein the substrate comprises pixel areas (para. 6 “CMOS image sensors are composed of CMOS digital-analog circuits and photosensitive pixels”),
and each of the plurality of photosensitive doped layers (05 and 06) is disposed on each a pixel area;
an electrical device (transistor 200 that includes silicon film 03, source and drains 10, gate dielectric 08, and gate 09) disposed in the active layer (03 and 10 are in the active layer) and on the active layer (08 and 09 are on the active layer);
and an interconnection structure disposed in the isolation layer and the active layer (metal plugs 15b and 16a and interconnection metal 17b);
wherein the plurality of photosensitive doped layers (06 and 05) are electrically coupled with the electrical device by the interconnection structure (connected through 16a, 17b, and 15b).
Gao fails to teach:
wherein the substrate comprises a plurality of mutually discrete pixel areas,
and each of the plurality of photosensitive doped layers is disposed on each of the plurality of pixel areas respectively;
wherein a projection of the electrical device on the substrate is located in a projection of a corresponding one of the plurality of photosensitive doped layers on the substrate.
Wang teaches:
wherein the substrate (second substrate 20) comprises a plurality of mutually discrete pixel areas (The photosensitive array 21, including a plurality of photosensitive units on a same plane, is formed on the drive circuit array.),
and each of the plurality of photosensitive doped layers (para. 42, “photosensitive units are photo diodes which include a stack of a P-type doping layer and a N-type doping layer, or a stack of a P-type doping layer, an I-type layer and a N-type doping layer”) is disposed on each of the plurality of pixel areas respectively (area with one of the pixels of the photosensitive array, see annotated Fig. 10 above);
Gao discloses the claimed invention except for the pixels being a plurality of discrete pixels with photosensitive layers deposited on each pixel. Wang teaches that it is known to include an array of a plurality of discrete photosensitive layer, each with a photosensitive layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gao to teach multiple discrete pixels as taught by Wang to increase the sensitivity of the sensing device and reduce crosstalk between neighboring pixels. See MPEP 2144.
Batude teaches in Fig. 9:
wherein a projection of the electrical device (MOS transistor M1) on the substrate (substrate 101) is located in a projection of a corresponding one of the plurality of photosensitive doped layers (N-type doped semiconductor layer 103, emissive layer 105, and/or P-type doped semiconductor layer 107) on the substrate (substrate 101).
Gao/Wang discloses the claimed invention except for a projection of the electrical device on a substrate being located inside a projection of the photosensitive doped layers. Batude teaches that it is known to arrange the electrical device directly above the photosensitive doped layers in order such that the projection of the transistor is within the projection of the doped layers on the substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gao/Wang to use the arrangement of Batude for the purpose of reducing the size of the footprint of the device. See MPEP 2144.
With respect to claim 16, Wang further teaches in Fig. 10-11:
Further comprising an isolation structure (isolating structures 26 and shallow trench isolating structures 11) disposed between adjacent photosensitive doped layers (photodiode layer 21) and between adjacent pixel areas (see annotated Fig. 10 above)
wherein the isolation structure (26 and 11) penetrates through the plurality of photosensitive doped layers (photodiode layer 21),
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gao in view of Wang and Batude as explained above.
With respect to claim 17, Wang further teaches in Fig. 2:
wherein the isolation structure (26 and 11) also penetrates through the active layer (layer of device layer 100 that includes source and drains 14a and 14b).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gao in view of Wang and Batude as explained above.
With respect to claim 18, Gao further teaches:
wherein the electrical device comprises a gate structure (08 and 09) on the substrate (01) and a source drain region (10) respectively disposed in the active layer (layer that includes 03, see annotated Fig. 10 above) on two sides of the gate structure (08 and 09).
With respect to claim 19, Gao further teaches:
wherein the interconnection structure (15b, 16a, and 17b) comprises a first plug (15b) on the active layer (see annotated Fig. 10 above),
a second plug (16a) on one photosensitive doped layer (05 and 06) and an electrical coupling layer (17b) for coupling the first plug (15b) with the second plug (16a), and the first plug (15b) is electrically coupled with the electrical device (see Fig. 10).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gao (CN 101546777 A) in view of Wang (US 2013/0240962 A1) and Batude (US 2021/0376185 A1) as applied to claim 8 above and further in view of Or-Bach (US 8,298,875 B1).
With respect to claim 10, Gao/Wang/Batude teaches all limitations of claim 8 upon which claim 10 depends. Gao further teaches:
forming an opening in the active layer and the isolation layer, wherein the opening penetrates through the active layer and the isolation layer (see Fig. 9, 16a penetrates through 02 and 07, which is part of the active layer, see annotated Fig. 10 above);
forming an interconnection dielectric layer in the opening;
forming the first plug on the active layer (metal plug 15b, see Fig. 19);
forming the second plug (metal plug 16a), wherein the second plug (16a) is disposed on a surface of the photosensitive doped layer (05);
and forming an electrical coupling layer (17b) on a top surface of the first plug (15b) and a top surface of the second plug (16a).
Claim 10 differs from Gao in that the interconnection dielectric (isolation dielectric 07) is not formed in an opening. Therefore, Gao/Wang/Batude fails to teach:
forming an interconnection dielectric layer in the opening;
forming the second plug penetrating through the interconnection dielectric layer,
Or-Bach teaches:
forming an interconnection dielectric layer (low-temperature gap fill oxide 420) in the opening (transistor isolation 414) (see Fig. 4D-4H);
forming the second plug (thru layer via 460) penetrating through the interconnection dielectric layer (420) (see Fig. 4J),
Gao/Wang/Batude discloses the claimed invention except for the interconnection dielectric layer disposed in the opening that the second plug penetrates. Or-Bach discloses that it is known in the art to provide an interconnection dielectric layer where the plug penetrates. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the method of Gao/Wang/Batude with the interconnection dielectric of Or-Bach, in order to improve isolation of the components of the device. See MPEP 2144.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897