DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous actions: claims 1 through 20 are rejected
Present action: claims 1 through 18, 21, and 22 are rejected
Claim Objections
Claim 21 is objected to because of the following informalities:
Claim 21 recites “the a third via structure via” in line 15. The words “the” and the second “via” are extraneous, the examiner suggests “
Claim 21 recites “and .
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation "the first metal via" in line 17. There is insufficient antecedent basis for this limitation in the claim. The examiner will assume that the applicant intended “the first metal lines”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s) or interpreted by the examiner.
Claim(s) 1, 2, 3, 4, 5, 15, 16, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2023/0317596) in view of Oh (US 2022/0384311) in view of Suga (US 7393775)
Regarding claim 1.
Kim teaches:
A semiconductor structure comprising: a device layer (fig 3:AR1105,110; [para 0027]) comprising one or more semiconductor devices (fig 3:F1,160,165; [para 0043]), a through silicon via (fig 3:400; [para 0024]) and at least one device level metal via (fig 3:222; [para 0024]);
a first wiring layer (fig 3:230; [para 0049]) comprising a plurality of first metal lines (fig 3:204; [para 0060]), wherein at least one of the first metal lines (fig 3:204; [para 0060]) of the plurality of first metal lines (fig 3:204; [para 0060]) is in direct contact with the at least one device level metal via (fig 3:222; [para 0024]);
a second wiring layer (fig 3:250; [para 0049]) comprising a plurality of second metal lines (fig 3:252; [para 0024]), wherein the first wiring layer (fig 3:230; [para 0049]) is located between the device layer (fig 3:AR1105,110; [para 0027])and the second wiring layer (fig 3:250; [para 0049]), and the plurality of second metal lines (fig 3:252; [para 0024]) are orientated relative to the plurality of first metal lines (fig 3:204; [para 0060]);
a first via structure (fig 3:530; [para 0024]) having a first end terminating on a horizontal surface and a second end, opposite the first end, that is in direct physical contact with the through silicon via (fig 3:400; [para 0024]) and a second via structure (fig 3:180a; [para 0052]) having a first end and a second end, opposite the first end, that is in direct physical contact with a first semiconductor device (fig 3:F1,160,165; [para 0043]) of the one or more semiconductor devices (fig 3:F1,160,165; [para 0043]), wherein a lower portion of the second via (fig 3:180a; [para 0052]) structure extends into the device layer (fig 3:AR1105,110; [para 0027]).
Kim does not teach a skip level via.
Oh teaches:
A semiconductor structure comprising:
a first wiring layer (fig 6:FM1,312; [para 0075]) comprising a plurality of first metal lines (fig 6:FM1; [para 0104]), wherein at least one of the first metal lines (fig 6:FM1; [para 0104]) of the plurality of first metal lines (fig 6:FM1; [para 0104]) is in direct contact with the at least one device level metal via (fig 6:FV1; [para 0104]);
a second wiring layer (fig 6FM2:314; [para 0074]) comprising a plurality of second metal lines (fig 6:fm2; [para 0074]), wherein the first wiring layer (fig 6:312,fm1; [para 0104]) is located between the device layer and the second wiring layer (fig 6:314,fm; [para 0104]);
and at least one first skip-level via comprising a first via structure having a first end terminating on a horizontal surface of the second wiring layer (fig 6:fm2; [para 0111]) and a second end, opposite the first end,
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide skip level vias in order that the structures inside semiconductor devices may become more complicated and highly integrated (paragraph 4).
Kim does not teach diagonally oriented lines.
Suga teaches:
a second wiring layer comprising a plurality of second metal lines (fig 10:12; [column 9 lines 25-35), wherein the first wiring layer (fig 10:10; [column 9 lines 30-35]) is located between the [substrate] and the second wiring layer (fig 10:12; [column 9 lines 30-40]), and the plurality of second metal lines (fig 10:12; [column 9 lines 30-45]) are diagonally orientated relative to the plurality of first metal lines (fig 10:10; [column 9 lines 30-45])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first and second lines at a diagonal in order reduce wire lengths and delay times and improve design flexibility (Suga column 2 lines 1-10).
Regarding claim 2.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 1.
Suga teaches:
the plurality of second metal lines (fig 10:12; [column 9 lines 30-40]) are offset 30° to 60° relative to the plurality of first metal lines (fig 10:10; [column 9 lines 30-40) (fig 8; [column 8 lines 6).
Regarding claim 3.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 2, further
Suga teaches:
the plurality of second metal lines (fig 10:12); [column 9 lines 30-40]) are offset 40° to 50° relative to the plurality of first metal lines (fig 10:10; [column 9 lines 30-40]) (fig 8,column 8 lines 1-15).
Regarding claim 4.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 1, further
Kim teaches
both the first wiring layer (fig 3:230; [para 0049])and the second wiring layer (fig 3:250; [para 0049])are located on a frontside of the device layer (fig 3:AR1105,110; [para 0027]).
Regarding claim 5.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 4, further
Kim teaches
at least one first metal via (fig 3:242; [para 0024]) connecting the second wiring layer (fig 3:250; [para 0049]) to the first wiring layer (fig 3:230; [para 0049]).
Regarding claim 15.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 1, further
Oh teaches:
the second wiring layer (fig 6:fm2; [para 0104]) is a signal line ([para 0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the line to be a signal line in order that signals can be transmitted across the structures to the device thereby enabling operation
Regarding claim 16.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 1, further
Oh teaches:
the one or more semiconductor devices (fig 3:F1,160,165; [para 0043]) comprise at least one transistor ([para 0029]).
Regarding claim 17.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 16, further
Oh teaches:
at least one device level metal via (fig 6:fv1; [para 0104]) is in direct contact with the at least one transistor (fig 6:f1.g1.ca1; [para 0092]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device level via to be in direct contact with the transistor in order to convey charge while minimizing connection length and resistance.
Regarding claim 18.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 1, further
Oh teaches:
the at least one first skip-level via has a vertical height that is greater than a vertical height of at least one device level metal via (fig 6:fv1; [para 0104]).
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Claim(s) 6, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2023/0317596) in view of Oh (US 2022/0384311) in view of Suga (US 7393775) as applied to claim 5 and further in view of Fuchida (US 5723908)
Regarding claim 6.
Kim in view of Oh in view of Suga teaches the semiconductor structure of claim 4, above
Kim in view of Oh in view of Suga does not teach third wiring level.
Fuchida teaches:
a third wiring layer comprising a plurality of third metal lines (fig 9:40b; [column 7 lines 40-55]), wherein the third wiring layer is located above the second wiring layer (fig 9:10; [column 7 lines 40-55]) and each of the third metal lines (fig 9:40b; [column 7 lines 40-55]) is orthogonal to each of the first metal lines (fig 9:20; [column 7 lines 40-55]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order to provide another level of interconnection and power distribution thereby enabling more flexibility in connection placement.
Regarding claim 7.
Kim in view of Oh in view of Suga in view Fuchida teaches the semiconductor structure of claim 6, further
Fuchida teaches:
at least one second skip-level via connecting the third wiring layer (fig 9:40b; [column 7 lines 40-55]) to the first wiring layer (fig 9:20; [column 7 lines 40-55]).
Regarding claim 8.
Kim in view of Oh in view of Suga in view Fuchida teaches the semiconductor structure of claim 7, further
Fuchida teaches:
at least one second metal via connecting the third wiring layer (fig 9:40b; [column 7 lines 40-55]) to the second wiring layer (fig 9:10; [column 7 lines 40-55]).
Claim(s) 9, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2023/0317596) in view of Oh (US 2022/0384311) in view of Suga (US 7393775) as applied to claim 1 and further in view of Livengood (US 2002/0020862)
Regarding claim 9.
Kim in view of Oh in view of Suge teaches the semiconductor structure of claim 1.
Kim in view of Oh in view of Suga does not teach the first and second wiring layers are located on the back side of the device.
Livengood teaches:
both the first wiring layer (fig 2:116; [para 0041]) and the second wiring layer (fig 2:204; [para 0041]) are located on a backside of the device layer (fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first and second wiring layers to be on the backside of the device in order to function as a backside power supply thereby enabling more efficient use of frontside area and reducing voltage drop and noise margin (paragraph 7)
Regarding claim 10.
Kim in view of Oh in view of Suga in view of Livengood teaches the semiconductor structure of claim 9, further
Livengood teaches:
the first wiring layer (fig 2:116; [para 0041]) is present in a backside power distribution layer ([para 0020,0040]).
Regarding claim 11.
Kim teaches:
at least one first metal via (fig 3:342; [para 0024]) connecting the second wiring layer (fig 3:352; [para 0024]) to the first wiring layer (fig 3:304; [para 0024]).
Claim(s) 12, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2023/0317596) in view of Oh (US 2022/0384311) in view of Suga (US 7393775) in view of Livengood (US 2002/0020862) as applied to claim 11 and further in view of Fuchida (US 5723908)
Regarding claim 12.
Kim in view of Oh in view of Suga in view of Livengood teaches the semiconductor structure of Claim 11, above
Kim in view of Oh in view of Suga in view of Livengood does not teach each of the third metal lines is orthogonal to each of the first metal lines.
Fuchida teaches:
a third wiring layer comprising a plurality of third metal lines (fig 9:40b; [column 9 lines 50-60]), wherein the third wiring layer (fig 9:40; [column 9 lines 45-55]) is located beneath the second wiring layer (fig 9:10; [column 9 lines 30-40]) and each of the third metal lines (fig 9:40b; [column 9 lines 50-60]) is orthogonal to each of the first metal lines (fig 9:20; [column 9 lines 55-60]).
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It would have been obvious to one of ordinary skill in the art to provide an orthogonal layer of wiring lines in order to provide additional signal routing with high packing density (Fuchida column 1 lines 10-35).
Regarding claim 13.
Kim in view of Oh in view of Suga in view of Livengood in view of Fuchida teaches the semiconductor structure of claim 12, further
Fuchida teaches:
at least one second skip-level via connecting the third wiring layer to the first wiring layer (annotated fig 9).
Regarding claim 14.
Kim in view of Ohin view of Suga in view of Livengood in view of Fuchida teaches the semiconductor structure of claim 13, further
Fuchida teaches:
at least one second metal via connecting the third wiring layer (fig 9:40; [column 9 lines 30-40) to the second wiring layer (fig 9:10; [column 9 lines 30-40]).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Kim (US 2023/0317596) in view of Suga (US 7393775) in view of Oh (US 2022/0384311)
Regarding claim 21.
Kim teaches:
A semiconductor structure comprising: a device layer (fig 3:AR1105,110; [para 0027]) comprising one or more semiconductor devices (fig 3:F1,160,165; [para 0043]), a through silicon via (fig 3:400; [para 0024]) and a device level metal via (fig 3:222; [para 0024]) in contact with a first semiconductor device (fig 3:F1,160,165; [para 0043]) of the one or more semiconductor devices (fig 3:F1,160,165; [para 0043]);
a first wiring layer (fig 3:230; [para 0049])comprising a plurality of first metal lines (fig 3:204; [para 0060]);
a second wiring layer (fig 3:250; [para 0049]) comprising a plurality of second metal lines (fig 3:252; [para 0024]), wherein the first wiring layer (fig 3:250; [para 0049]) is located between the device layer (fig 3:AR1105,110; [para 0027]) and the second wiring layer (fig 3:250; [para 0049]), and the plurality of second metal lines (fig 3:252; [para 0024]) are orientated relative to the plurality of first metal lines (fig 3:204; [para 0060]);
a first via structure (fig 3:530; [para 0024]) having a first end terminating on a horizontal surface and a second end, opposite the first end, that is in direct physical contact with the through silicon via (fig 3:400; [para 0024]), a second via structure (fig 3:180a; [para 0052]) having a first end and a second end, opposite the first end, that is in direct physical contact with a first semiconductor device (fig 3:F1,160,165; [para 0043]) of the one or more semiconductor devices (fig 3:F1,160,165; [para 0043]), wherein a lower portion of the second via structure (fig 3:180a; [para 0052]) extends into the device layer (fig 3:AR1105,110; [para 0027]), and a third via structure (fig 3:242; [para 0024])having a first end on a horizontal surface of the second wiring layer (fig 3:250; [para 0049])and a second end, opposite the first end, that is in direct physical contact with the first metal (lines) (fig 3:204; [para 0060]).
Kim does not teach diagonally oriented lines.
Suga teaches:
a second wiring layer comprising a plurality of second metal lines (fig 10:12; [column 9 lines 25-35), wherein the first wiring layer (fig 10:10; [column 9 lines 30-35]) is located between the [substrate] and the second wiring layer (fig 10:12; [column 9 lines 30-40]), and the plurality of second metal lines (fig 10:12; [column 9 lines 30-45]) are diagonally orientated relative to the plurality of first metal lines (fig 10:10; [column 9 lines 30-45])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first and second lines at a diagonal in order reduce wire lengths and delay times and improve design flexibility (Suga column 2 lines 1-10).
Kim does not teach a skip level via.
Oh teaches:
A semiconductor structure comprising: a device layer comprising one or more semiconductor devices (fig 5,6:F1; [para 0034]), a through silicon via (fig 6:TV1; [para 0105]);
a first wiring layer (fig 6:FM1,312; [para 0075])comprising a plurality of first metal lines (fig 6:FM1; [para 0104]);
a second wiring layer (fig 6:FM2:314; [para 0074]) comprising a plurality of second metal lines (fig 6:fm2; [para 0074]), wherein the first wiring layer (fig 6:312,fm1; [para 0104])is located between the device layer (fig 6:F1; [para 0034]) and the second wiring layer (fig 6FM2:314; [para 0074]), and the plurality of second metal lines (fig 6:fm2; [para 0074]) are orientated relative to the plurality of first metal lines (fig 6:FM1; [para 0104]);
and at least one first skip-level via (fig 6:SV1; [para 0094]) comprising a first via structure (fig 6:SV1; [para 0094]) having a first end terminating on a horizontal surface of the second wiring layer (fig 6:FM2:314; [para 0074]) and a second end, opposite the first end
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order that the structures inside semiconductor devices may become more complicated and highly integrated (paragraph 4).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Livengood (US 2002/0020862) in view of Suga (US 7393775)
Regarding claim 22.
Livengood teaches:
A semiconductor structure comprising: a device layer comprising one or more semiconductor devices (fig 2:104,106,107[para 0035]), a through silicon via (fig 2:210; [para 0043]) and at least one device level via (fig 2:117a; [para 0043]);
a first wiring layer (fig 2:116; [para 0041]) comprising a lines, wherein at least one of the first lines is in direct contact with the at least one device level via (fig 2:117a; [para 0042]);
a second wiring layer (fig 2:204; [para 0041]) comprising a of second lines, wherein the first wiring layer (fig 2:116; [para 0041]) is located between the device layer devices (fig 2:104,106,107; [para 0035]) and the second wiring layer (fig 2:116; [para 0041]), ;
and a first skip-level via (fig 2:206; [para 0043]) having a first end terminating on a horizontal surface of the second wiring layer (fig 2:204; [para 0041]) and a second end, opposite the first end, that is in direct physical contact with a first semiconductor device (fig 2:104; [para 0035]) of the one or more semiconductor devices (fig 2:104,106,107; [para 0035]), wherein a lower portion of the first skip-level via extends into the device layer.
Livengood does not teach that the vias and lines are composed of metal in the embodiment.
Livengood teaches:
Forming conductive paths of metal ([para 26])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the vias and lines of metal because of metals high conductivity and patternability enabling specific conductive paths to be formed
Livengood does not teach that wiring layers comprises a plurality of lines.
Livengood does not teach pluralities of lines and diagonal lines.
Suga teaches:
a first wiring layer comprising a plurality of first metal lines (fig 10:10; [column 9 lines 30-35]), a second wiring layer comprising a plurality of second metal lines (fig 10:12; [column 9 lines 25-35), wherein the first wiring layer is located between the [substrate] and the second wiring layer (fig 10:12; [column 9 lines 25-35), and the plurality of second metal lines fig 10:12; [column 9 lines 25-35) are diagonally orientated relative to the plurality of first metal lines (fig 10:10; [column 9 lines 30-35])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first and second lines at a diagonal in order reduce wire lengths and delay times and improve design flexibility (Suga column 2 lines 1-10).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 through 18 have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not teach a first via connecting a device to a second wiring layer and second via connecting a through silicon via to the second wiring layer.
However, newly applied reference Livengood teaches additional arrangements of skip level vias connecting to devices and through vias
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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