DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 4, 5, 15, 16, 17, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2022/0384311) in view of Suga (US 7393775).
Regarding claim 1.
Oh teaches a semiconductor structure comprising: a device layer comprising one or more semiconductor devices (fig 5,6:F1,g1,ca1;[para 0034]), a through silicon via (fig 6:TV1;[para 0116]) and at least one device level metal via (fig 6:FV1;[para 0104]); a first wiring layer (fig 6:FM1,312;[para 0075]) comprising a plurality of first metal lines (fig 6:FM1;[para 0104]), wherein at least one of the first metal lines (fig 6:FM1;[para 0104]) of the plurality of first metal lines (fig 6:FM1;[para 0104]) is in direct contact with the at least one device level metal via (fig 6:FV1;[para 0104]); a second wiring layer (fig 6:fm2,314;[para 0074]) comprising a plurality of second metal lines (fig 6:fm2:;[para 0074], wherein the first wiring layer (fig 6:312,fm1;[para 0104]) is located between the device layer and the second wiring layer (fig 6:314,fm2;[para 0104]), […]and at least one first skip-level via having a first end terminating on a horizontal surface of the second wiring layer (fig 6:fm2;[para 0111]) and a second end, opposite the first end, that is in direct physical contact with the through silicon via (fig 6:TV1;[para 0111]) or one of the semiconductor devices present in the device layer
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Oh does not teach diagonal lines
Suga teaches a second wiring layer comprising a plurality of second metal lines (fig 10:12[column 9 lines 25-35), wherein the first wiring layer (fig 10:10[column 9 lines 30-35]) is located between the [substrate] and the second wiring layer (fig 10:12[column 9 , and the plurality of second metal lines (fig 10:12) are diagonally orientated relative to the plurality of first metal lines (fig 10:10[column 9 lines 30-45])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first and second lines at a diagonal in order reduce wire lengths and delay times and improve design flexibility (Suga column 2 lines 1-10).
Regarding claim 2, Oh in view of Suga teaches the structure of claim 1
Suga teaches the plurality of second metal lines (fig 10:12[column 9 lines 30-40]) are offset 30° to 60° relative to the plurality of first metal lines (fig 10:10[column 9 lines 30-40) (fig 8[column 8 lines 6).
Regarding claim 3, Oh in view of Suga teaches the structure of claim 2
Suga teaches the plurality of second metal lines (fig 10:12)[column 9 lines 30-40]) are offset 40° to 50° relative to the plurality of first metal lines (fig 10:10[column 9 lines 30-40]) (fig 8,column 8 lines 1-15).
Regarding claim 4, Oh in view of Suga teaches the structure of claim 2.
Oh teaches both the first wiring layer (fig 6:FM1,312;[para 0104]) and the second wiring layer (fig 6:fm2,314;[para 0104]) are located on a frontside of the device layer (fig 6;[para 0104]).
Regarding claim 5, Oh in view of Suga teaches the structure of claim 4.
Oh teaches at least one first metal via (fig 6:fv2;[para 0104]) connecting the second wiring layer (fig 6:fm2;[para 0104]) to the first wiring layer (fig 6:fm2]).
Regarding claim 15, Oh in view of Suga teaches the semiconductor structure of Claim 1, further:
Oh teaches the second wiring layer (fig 6:fm2;[para 0104]) is a signal line ([para 0073]).
Regarding claim 16, Oh in view of Suga teaches the structure of claim 1.
Oh teaches the one or more semiconductor devices (fig 5,6:f1,g1,ca1;[para 0034] comprise at least one transistor ;[para 0034].
Regarding claim 17, Oh in view of Suga teaches the structure of claim 16
Oh teaches at least one device level metal via (fig 6:fv1;[para 0104]) is in direct contact with the at least one transistor (fig 6:f1.g1.ca1;[para 0092]).
Regarding claim 18, Oh in view of Suga teaches the structure of claim 1
Oh teaches the at least one first skip-level via has a vertical height that is greater than a vertical height of at least one device level metal via (fig 6:fv1;[para 0104]}.
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Regarding claim 19, Oh in view of Suga teaches the structure of claim 1.
Oh teaches each of the plurality of first metal lines (fig 5:fm1);[para 0104]), the plurality of second metal lines (fig 6:fm2;[para 0104]), the at least one device level metal via (fig 6:fv1;[para 0104]) and the at least one first skip via (fig 6:192;[para 0111]) comprises an electrically conductive metal or an electrically conductive metal alloy.
Regarding claim 20, oh in view of Suga teaches the structure of claim 1.
Oh teaches the first wiring layer (fig 6:312,fm1;[para 0073]) further comprises a first dielectric material (fig 6:312;[para 0073) embedding the plurality of first metal lines (fig 6:fm1;[para 0104]), and the second wiring layer (fig 6:314,fm2;[para 0073]) further comprises a second dielectric material (fig 6:314;[para 0073]) embedding the plurality of second metal lines (fig 6:fm2;[para 0104]), wherein the at least one first skip-level via passes through the first dielectric material (fig 6:312]0073]) without contact any of the plurality of first metal lines (fig 6:fm1;[para 0104]).
Claim(s) 6, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2022/0384311) in view of Suga (US 7393775) as applied to claim 5 and further in view of Fuchida (US 5723908)
Regarding claim 6.
Oh in view of Suga teaches elements of the claimed invention above.
Oh in view of Suga does not teach third wiring level.
Fuchia teaches a third wiring layer comprising a plurality of third metal lines (fig 9:40b[column 7 lines 40-55]), wherein the third wiring layer is located above the second wiring layer (fig 9:10[column 7 lines 40-55]) and each of the third metal lines (fig 9:40b[column 7 lines 40-55]) is orthogonal to each of the first metal lines (fig 9:20[column 7 lines 40-55]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order to provide another level of interconnection and power distribution thereby enabling more flexibility in connection placement.
Regarding claim 7, Oh in view of Suga in view of Fuchida teaches the structure of claim 7.
Fuchida teaches at least one second skip-level via connecting the third wiring layer (fig 9:40b[column 7 lines 40-55]) to the first wiring layer (fig 9:20[column 7 lines 40-55]).
Regarding claim 8, Oh in view of Suga in view of Fuchida teaches the structure of claim 7.
Fuchida teaches at least one second metal via connecting the third wiring layer (fig 9:40b[column 7 lines 40-55]) to the second wiring layer (fig 9:10[column 7 lines 40-55]).
Claim(s) 1, 9, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2022/0384311) in view of Suga (US 7393775) in view of Wang (US 2021/0343639)
Regarding claim 1.
Oh teaches a semiconductor structure comprising: a device layer comprising one or more semiconductor devices (fig 5,6:F1,G1,ca1;[para 0034]), a through silicon via (fig 6:tv1;[para 0105]); […]a first wiring layer (fig 6:BM1;[para 0094]) comprising a plurality of first metal lines (fig 6;[para 0094); […]a second wiring layer (fig 6:BM3;[para 0094]) comprising a plurality of second metal lines (fig 6;[para 0094]), wherein the first wiring layer (fig 6B:M1;[para 0094]) is located between the device layer and the second wiring layer (fig 6:BM3;[para 0094]); and at least one first skip-level via (fig 6:SV1;[para 0094]) having a first end terminating on a horizontal surface of the second wiring layer (fig 6:BM3;[para 0094,0095]) and a second end, opposite the first end, that is in direct physical contact with the through silicon via (fig 6:TV1;[para 0094,0095]) or one of the semiconductor devices present in the device layer (fig 6:;[para 0094,0095]).
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Oh does not teach diagonally oriented second metal lines.
Suga teaches a second wiring layer comprising a plurality of second metal lines (fig 10:12[column 9 lines 25-35]), wherein the first wiring layer (fig 10) is located between the [substrate] and the second wiring layer (fig 10), and the plurality of second metal lines (fig 10:12[column 9 lines 30-40) are diagonally orientated relative to the plurality of first metal lines (fig 10:10[column 9 lines 30-45), a via (fig 10:14[column 9 lines 30-40]) having a first end terminating on a horizontal surface of the second wiring layer (fig 4c:12[column 5 lines 30-40])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first and second lines at a diagonal in order reduce wire lengths and delay times and improve design flexibility (Suga column 2 lines 1-10).
Oh does not teach a device level metal via.
Wang teaches at least one device level metal via (fig 25:300;[para 0089]); a first wiring layer (fig 25:315;[para 0091]) comprising a plurality of first metal lines (fig 25:315;[para 0091]), wherein at least one of the first metal lines (fig 25:315;[para 0091]) of the plurality of first metal lines is in direct contact with the at least one device level metal via (fig 25:300;[para 0091]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a device level via connecting to the backside metal line in order to reduce the number of through silicon vias and front side power distribution.
Regarding claim 9, Oh in view of Suga in view of Wang teaches the structure of claim 1.
Oh teaches both the first wiring layer (fig 6:BM1;[para 0094]) and the second wiring layer (fig 6:BM3;[para 0094]) are located on a backside (fig 6:BS;[para 0094]) of the device layer (fig 6;[para 0094]).
Regarding claim 10, Oh in view of Suga in view of Wang teaches the structure of claim 9.
Oh teaches the first wiring layer (fig:BM1;[para 0108]) is present in a backside power distribution layer (;[para 0108]).
Regarding claim 11, Oh in view of Suga in view of Wang teaches the structure of claim 9.
Oh teaches at least one first metal via (fig 6:BV1,BV2;[para 0094]) connecting the second wiring layer (fig 6:BM3;[para 0094]) to the first wiring layer (fig 6:BM1;[para 0094]).
Claim(s) 12, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2022/0384311) in view of Suga (US 7393775) in view of Wang (US 2021/0343639) as applied to claim 11 and further in view of Fuchida (US 5723908).
Regarding claim 12.
Oh in view of Suga in view of Wang teaches the structure of claim 11.
Oh in view of Suga in view of Wang does not teach each of the third metal lines is orthogonal to each of the first metal lines.
Fuchida teaches a third wiring layer comprising a plurality of third metal lines (fig 9:40b[column 9 lines 50-60]), wherein the third wiring layer (fig 9:40[column 9 lines 45-55]) is located beneath the second wiring layer (fig 9:10[column 9 lines 30-40]) and each of the third metal lines (fig 9:40b[column 9 lines 50-60])is orthogonal to each of the first metal lines (fig 9:20[column 9 lines 55-60]).
It would have been obvious to one of ordinary skill in the art to provide an orthogonal layer of wiring lines in order to provide additional signal routing with high packing density (Fuchida column 1 lines 10-35).
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Regarding claim 13.
Oh in view of Suga in view of Wang teaches the structure of claim 12
Fuchida teaches at least one second skip-level via connecting the third wiring layer to the first wiring layer (fig 9).
Regarding claim 14.
Oh in view of Suga in view of Wang teaches the structure of claim 12
Fuchida teaches at least one second metal via connecting the third wiring layer (fig 9:40[column 9 lines 30-40) to the second wiring layer (fig 9:10[column 9 lines 30-40]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not teach the structure comprising a through silicon via.
However, Briggs (US 9911651) in view of Suga (US 7393775) in combination the newly applied reference Oh (US 2022/0384311) and Oh (US 2022/0384311) in view of Suga (US 7393775) in view of Wang (US 2021/0343639) teaches all elements of the claimed invention (see above).
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 16, 2026