DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 4/3/2026 that has been entered, wherein claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/3/2026 has been entered.
Claim Rejections - 35 USC § 112
The rejection of claims 8-13 rejected under 35 U.S.C. 112(b) is withdrawn in light of Applicant’s amendment of 4/3/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7-8, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Walker et al. (US 2009/0001821 A1) in view of Ma et al. (US 2013/0055416 A1) both of record.
Regarding claim 1, Walker teaches a semiconductor package(Fig. 10) comprising:
a substrate(162);
a first-level interconnect terminal(166, ¶0185) disposed on a first surface of the substrate(162);
a backside interconnect terminal(164, ¶0185) disposed on the first surface of the substrate(162), wherein the backside interconnect terminal(164, ¶0185) is coupled(¶0185, ¶0191) to the first-level interconnect terminal(166, ¶0185) through the substrate(162); and
an integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprising:
a front-side shield(152 of 144, ¶0181) disposed on, or embedded at least partially within, the integrated circuit die(176, 150, 152, 154, ¶0181-182, ¶0205);
front-side active circuitry(150 of 144, ¶0185, ¶0191) coupled to the first-level interconnect terminal(166, ¶0185),
a backside shield(152 of 142, ¶0181) disposed on, or embedded at least partially within, the integrated circuit die(176, 150, 152, 154, ¶0181-182, ¶0205) and coupled to the backside interconnect terminal(166, ¶0185), wherein the front-side active circuitry(150 of 144, ¶0185, ¶0191) is coupled(¶0191) to the backside shield(152 of 142, ¶0181) through the first- level interconnect terminal(166, ¶0185), the substrate(162), and the backside interconnect terminal(164, ¶0185).
Walker does not explicitly teach a front-side metal mesh; a backside metal mesh. Walker does teach shield 152 is formed in the top layer of metal interconnects of chips 142, 144(¶0181).
Ma teaches a semiconductor package(Fig. 3A) comprising a front-side metal mesh(202, ¶0046). Making the Walker’s front-side shield and backside shield a metal mesh taught by Ma, would result in a front-side metal mesh; a backside metal mesh. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, to include a front-side metal mesh and a backside metal mesh, as taught by combining with Ma, so that security elements in the shield are coupled to the underlying electronics via the intermediate metal layers(¶0046).
The limitation of the “front-side active circuitry(150 of 144, ¶0185, ¶0191) is configured to perform electrical continuity verification of at least one of the front-side metal mesh(152 of 144, ¶0181) or the backside metal mesh(152 of 142, ¶0181) to detect tampering with the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) or unauthorized access to the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182)” is a recitation how the product/device is being used. The structure as defined in Walker in view of Ma could be used in the manner claimed (i.e. the front-side active circuitry of Walker in view of Ma could be configured to perform electrical continuity verification of at least one of the front-side metal mesh or the backside metal mesh to detect tampering with the integrated circuit die or unauthorized access to the integrated circuit die) and thus Walker in view of Ma anticipates the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 7, Walker teaches the semiconductor package of claim 1, wherein the front-side active circuitry(150, ¶0185, ¶0191) is coupled to the front-side metal shield(152 of 144, ¶0181) and the backside metal shield(152 of 142, ¶0181).
Walker does not explicitly teach a front-side metal mesh and the backside metal mesh. Walker does teach a front-side shield(152 of 144, ¶0181) and a backside shield(152 of 142, ¶0181). Further Walker teaches shield 152 is formed in the top layer of metal interconnects of chips 142, 144(¶0181).
Ma teaches a semiconductor package(Fig. 3A) comprising a front-side metal mesh(202, ¶0046). Making the Walker’s front-side shield and backside shield a metal mesh taught by Ma, would result in the front-side active circuitry(150, ¶0185, ¶0191) coupled to the front-side metal shield and the backside metal shield. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the front-side active circuitry(150, ¶0185, ¶0191) coupled to the front-side metal shield and the backside metal shield, as taught by combining with Ma, so that security elements in the shield are coupled to the underlying electronics via the intermediate metal layers(¶0046).
The limitation of the front-side active circuitry(150 of 144, ¶0185, ¶0191) is to check electrical continuity of at least one of the front-side metal mesh or the backside metal mesh is a functional limitation. The structure as defined in Walker, in view of Ma could be used in the manner claimed (i.e. the front-side active circuitry(150, ¶0185, ¶0191) of Walker, in view of Ma could be used to check electrical continuity of at least one of the front-side metal mesh or the backside metal mesh) and thus Walker, in view of Ma, render obvious the limitations of this claim. MPEP 2112.01, 2114.
Regarding claim 8, Walker teaches a semiconductor package(Fig. 10) comprising:
a substrate(162);
a first interconnect terminal(166, ¶0185) disposed on a first surface of the substrate(162);
a second interconnect terminal(164, ¶0185) disposed on the first surface of the substrate(162), wherein the second interconnect terminal(164, ¶0185) is coupled(¶0185, ¶0191) to the first interconnect terminal(166, ¶0185) through the substrate(162); and
an integrated circuit(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprising:
a front-side shield(152 of 144, ¶0181);
front-side active circuitry(150 of 144, ¶0185, ¶0191) coupled to the first interconnect terminal(166, ¶0185); and
a backside shield(152 of 142, ¶0181) coupled to the second interconnect terminal(166, ¶0185),
wherein the front-side shield(152 of 144, ¶0181) is disposed on, or embedded at least partially within, the integrated circuit die(176 as a sole chip, ¶0205) comprising the front-side active circuitry(150, ¶0185, ¶0191), and wherein the backside shield(152 of 142, ¶0181) is disposed on, or embedded at least partially within, the integrated circuit die(176 as a sole chip, ¶0205), wherein the front-side active circuitry(150 of 144, ¶0185, ¶0191) is coupled(¶0191) to the backside shield(152 of 142, ¶0181) through the first- level interconnect terminal(166, ¶0185), the substrate(162), and the backside interconnect terminal(164, ¶0185).
Walker does not explicitly teach a front-side metal mesh; a backside metal mesh Walker does not explicitly teach a front-side metal mesh; a backside metal mesh. Walker does teach shield 152 is formed in the top layer of metal interconnects of chips 142, 144(¶0181).
Ma teaches a semiconductor package(Fig. 3A) comprising a front-side metal mesh(202, ¶0046). Making the Walker’s front-side shield and backside shield a metal mesh taught by Ma, would result in a front-side metal mesh; a backside metal mesh. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, to include a front-side metal mesh and a backside metal mesh, as taught by combining with Ma, so that security elements in the shield are coupled to the underlying electronics via the intermediate metal layers(¶0046).
Regarding claim 14, Walker teaches the semiconductor package(Fig. 10) comprising:
a substrate(162);
a first terminal(166, ¶0185) disposed on a first surface of the substrate(162), the first terminal(166, ¶0185) being a first type(bump);
a second terminal(164, ¶0185) disposed on the first surface of the substrate(162), the second terminal(164, ¶0185) being a second type(wire) different than the first type(bump), wherein the second terminal(164, ¶0185) is coupled(¶0185, ¶0191) to the first terminal(166, ¶0185) through the substrate(162); and
an integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprising:
a first shield(152 of 144, ¶0181) disposed on, or embedded at least partially within, the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182);
active circuitry(150, ¶0185, ¶0191) coupled to the first terminal(166, ¶0185) and
a second shield(152 of 142, ¶0181) coupled to the second terminal(166, ¶0185), wherein the second shield(152 of 142, ¶0181) is disposed on, or embedded at least partially within, the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182), wherein the active circuitry(150 of 144, ¶0185, ¶0191) is coupled(¶0191) to the backside shield(152 of 142, ¶0181) through the first terminal(166, ¶0185), the substrate(162), and the second terminal(164, ¶0185).
Walker does not explicitly teach a front-side metal mesh; a backside metal mesh Walker does not explicitly teach a front-side metal mesh; a backside metal mesh. Walker does teach shield 152 is formed in the top layer of metal interconnects of chips 142, 144(¶0181).
Ma teaches a semiconductor package(Fig. 3A) comprising a front-side metal mesh(202, ¶0046). Making the Walker’s front-side shield and backside shield a metal mesh taught by Ma, would result in a front-side metal mesh; a backside metal mesh. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, to include a front-side metal mesh and a backside metal mesh, as taught by combining with Ma, so that security elements in the shield are coupled to the underlying electronics via the intermediate metal layers(¶0046).
The limitation of the “active circuitry(150 of 144, ¶0185, ¶0191) is configured to perform electrical continuity verification of at least one of the front-side metal mesh(152 of 144, ¶0181) or the backside metal mesh(152 of 142, ¶0181) to detect tampering with the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) or unauthorized access to the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182)” is a recitation how the product/device is being used. The structure as defined in Walker in view of Ma could be used in the manner claimed (i.e. the active circuitry of Walker in view of Ma could be configured to perform electrical continuity verification of at least one of the front-side metal mesh or the backside metal mesh to detect tampering with the integrated circuit die or unauthorized access to the integrated circuit die) and thus Walker in view of Ma anticipates the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 20, Walker teaches the semiconductor package of claim 17, wherein the active circuitry(150, ¶0185, ¶0191) is coupled to the first metal shield(152 of 144, ¶0181) and the second metal (152 of 142, ¶0181).
Walker does not explicitly teach a first metal mesh and the second metal mesh. Walker does teach a first shield(152 of 144, ¶0181) and a second shield(152 of 142, ¶0181). Further Walker teaches shield 152 is formed in the top layer of metal interconnects of chips 142, 144(¶0181).
Ma teaches a semiconductor package(Fig. 3A) comprising a first metal mesh(202, ¶0046). Making the Walker’s first shield and second shield a metal mesh taught by Ma, would result in a second metal mesh coupled to the second interconnect terminal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, to include a front-side metal mesh; a backside metal mesh coupled to the second interconnect terminal, as taught by combining with Ma, so that security elements in the shield are coupled to the underlying electronics via the intermediate metal layers(¶0046).
The limitation of the front-side active circuitry(150, ¶0185, ¶0191) is to check electrical continuity of at least one of the first metal mesh or the second metal mesh. The structure as defined in Walker, in view of Ma could be used in the manner claimed (i.e. the front-side active circuitry(150, ¶0185, ¶0191) of Walker, in view of Ma could be used to check electrical continuity of at least one of the first metal mesh or the second metal mesh) and thus Walker, in view of Ma, render obvious the limitations of this claim. MPEP 2112.01, 2114.
Claims 2, 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Walker et al. (US 2009/0001821 A1) and Ma et al. (US 2013/0055416 A1) as applied to claims 1, 8 and 14 above, further in view of Stuber et al. (US 2014/0175637 A1) as cited in the IDS of 11/9/2022, all of record.
Regarding claim 2, Walker, in view of Ma, teaches the semiconductor package of claim 1, wherein the backside interconnect terminal(164, ¶0185) is a wirebond pad(¶0191, Fig. 10).
Walker and Ma are not relied on to teach a first-level interconnect terminal(166, ¶0185) is a controlled collapse chip connection (C4) solder bump.
Stuber teaches a package(Fig. 2F) wherein the first-level interconnect terminal(207, ¶0034) is a controlled collapse chip connection (C4) pad(¶0005-6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the first-level interconnect terminal is a controlled collapse chip connection (C4) pad, as taught by Stuber, so that the footprint on the board used by the chip is no larger than the area of the chip(¶0005) with substantial package size reductions(¶0006).
Regarding claim 9, Walker, in view of Ma, teaches the semiconductor package of claim 8, wherein the second interconnect terminal(164, ¶0185) is a wirebond pad(¶0191, Fig. 10).
Walker and Ma are not relied on to teach the first-level interconnect terminal(166, ¶0185) is a controlled collapse chip connection (C4) solder bump.
Stuber teaches a package(Fig. 2F) wherein the first-level interconnect terminal(207, ¶0034) is a controlled collapse chip connection (C4) pad(¶0005-6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the first-level interconnect terminal is a controlled collapse chip connection (C4) pad, as taught by Stuber, so that the footprint on the board used by the chip is no larger than the area of the chip(¶0005) with substantial package size reductions(¶0006).
Regarding claim 15, Walker, in view of Ma, teaches the semiconductor package of claim 14, wherein the second terminal(164, ¶0185) is a wirebond pad(¶0191, Fig. 10).
Walker and Ma are not relied on to teach the first terminal(166, ¶0185) is a controlled collapse chip connection (C4) solder bump.
Stuber teaches a package(Fig. 2F) wherein the first terminal(207, ¶0034) is a controlled collapse chip connection (C4) pad(¶0005-6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the first terminal is a controlled collapse chip connection (C4) pad, as taught by Stuber, so that the footprint on the board used by the chip is no larger than the area of the chip(¶0005) with substantial package size reductions(¶0006).
Claims 3, 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Walker et al. (US 2009/0001821 A1) and Ma et al. (US 2013/0055416 A1) as applied to claims 1, 8 and 14 above, further in view of Chang (US 2012/0273945 A1) as cited in the IDS of 11/9/2022, all of record.
Regarding claim 3, Walker, in view of Ma, teaches the semiconductor package of claim 1, wherein the backside interconnect terminal(164, ¶0185) is a wirebond pad(¶0191, Fig. 10).
Walker and Ma are not relied on to teach the first-level interconnect terminal(166, ¶0185) is a copper-pillar bump.
Chang teaches a semiconductor package(Fig. 2F) wherein the first-level interconnect terminal(20, 32, 32”, ¶0026) is a copper-pillar bump(¶0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the first-level interconnect terminal is a copper-pillar bump, as taught by Chang, in order to achieve finer pitch with minimum probability of bump bridging, reduce the capacitance load for the circuits, and to allow the electronic component to perform at higher frequencies(¶0003).
Regarding claim 10, Walker, in view of Ma, teaches the semiconductor package of claim 8, wherein the second interconnect terminal(164, ¶0185) is a wirebond pad(¶0191, Fig. 10).
Walker and Ma are not relied on to teach the first interconnect terminal(166, ¶0185) is a copper-pillar bump.
Chang teaches a semiconductor package(Fig. 2F) wherein the second interconnect terminal(20, 32, 32”, ¶0026) is a copper-pillar bump(¶0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the second interconnect terminal is a copper-pillar bump, as taught by Chang, in order to achieve finer pitch with minimum probability of bump bridging, reduce the capacitance load for the circuits, and to allow the electronic component to perform at higher frequencies(¶0003).
Regarding claim 16, Walker, in view of Ma, teaches the semiconductor package of claim 14, wherein the second terminal(164, ¶0185) is a wirebond pad(¶0191, Fig. 10).
Walker and Ma are not relied on to teach the first terminal(166, ¶0185) is a copper-pillar bump.
Chang teaches a semiconductor package(Fig. 2F) wherein the first terminal(20, 32, 32”, ¶0026) is a copper-pillar bump(¶0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the first terminal is a copper-pillar bump, as taught by Chang, in order to achieve finer pitch with minimum probability of bump bridging, reduce the capacitance load for the circuits, and to allow the electronic component to perform at higher frequencies(¶0003).
Claims 4-6, 11-13 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Walker et al. (US 2009/0001821 A1) and Ma et al. (US 2013/0055416 A1) as applied to claims 1, 8 and 14 above, further in view of Muchsel et al. (US 2018/0018673 A1), all of record.
Regarding claim 4, Walker, in view of Ma, teaches the semiconductor package of claim 1, wherein the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a function circuit(154, ¶0181, ¶0191) coupled to both the front-side metal mesh(152 of 144, ¶0181) and the backside metal mesh(152 of 142, ¶0181).
Walker and Ma are not relied on to teach a physically unclonable function circuit.
Muchsel teaches a semiconductor package(Fig. 3) comprising a physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, to include a physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the integrated circuit comprises a physically unclonable function circuit coupled to both the front-side metal mesh and the backside metal mesh to output a first fingerprint value, wherein a modification of an electrical characteristic of at least one of the backside metal mesh or the front-side metal mesh causes the physically unclonable function circuit to output a second fingerprint value that is not equal to the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used to output a first fingerprint value, wherein a modification of an electrical characteristic of at least one of the backside metal mesh or the front-side metal mesh causes the physically unclonable function circuit to output a second fingerprint value that is not equal to the first fingerprint value ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 5, Walker, in view of Ma, teaches the semiconductor package of claim 4, but is not relied on to teach the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a key generation circuit coupled to the physically unclonable function circuit, the key generation circuit to derive a key for a cryptographic function at least in part on the first fingerprint value.
Muchsel teaches a semiconductor package(Fig. 3) wherein the integrated circuit(300, ¶0045) comprises a key generation circuit(310, ¶0045) coupled to the physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the integrated circuit comprises a key generation circuit coupled to the physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the key generation circuit to derive a key for a cryptographic function at least in part on the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used so that the key generation circuit can derive a key for a cryptographic function at least in part on the first fingerprint value ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 6, Walker, in view of Ma, teaches the semiconductor package of claim 4, but is not relied on to teach the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a cryptographic circuit coupled to the physically unclonable function circuit, the physically unclonable function circuit to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value.
Muchsel teaches a semiconductor package(Fig. 3) wherein the integrated circuit(300, ¶0045) comprises a cryptographic circuit(310, ¶0050) coupled to the physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the integrated circuit comprises a key generation circuit coupled to the physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the physically unclonable function circuit to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used so that the physically unclonable function circuit is used to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value. ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 11, Walker, in view of Ma, teaches the semiconductor package of claim 8, wherein the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a function circuit(154, ¶0181, ¶0191) coupled to both the front-side metal mesh(152 of 144, ¶0181) and the backside metal mesh(152 of 142, ¶0181).
Walker and Ma are not relied on to teach a physically unclonable function circuit.
Muchsel teaches a semiconductor package(Fig. 3) comprising a physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, to include a physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the integrated circuit comprises a physically unclonable function circuit coupled to both the front-side metal mesh and the backside metal mesh to output a first fingerprint value, wherein a modification of an electrical characteristic of at least one of the backside metal mesh or the front-side metal mesh causes the physically unclonable function circuit to output a second fingerprint value that is not equal to the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used to output a first fingerprint value, wherein a modification of an electrical characteristic of at least one of the backside metal mesh or the front-side metal mesh causes the physically unclonable function circuit to output a second fingerprint value that is not equal to the first fingerprint value ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 12, Walker, in view of Ma, teaches the semiconductor package of claim 11, but is not relied on to teach the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a key generation circuit coupled to the physically unclonable function circuit, the key generation circuit to derive a key for a cryptographic function based at least in part on the first fingerprint value.
Muchsel teaches a semiconductor package(Fig. 3) wherein the integrated circuit(300, ¶0045) comprises a key generation circuit(310, ¶0045) coupled to the physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the integrated circuit comprises a key generation circuit coupled to the physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the key generation circuit to derive a key for a cryptographic function based at least in part on the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used so that the key generation circuit can derive a key for a cryptographic function at least in part on the first fingerprint value ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 13, Walker, in view of Ma, teaches the semiconductor package of claim 11, but is not relied on to teach the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a cryptographic circuit coupled to the physically unclonable function circuit, the physically unclonable function circuit to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value.
Muchsel teaches a semiconductor package(Fig. 3) wherein the integrated circuit(300, ¶0045) comprises a cryptographic circuit(310, ¶0050) coupled to the physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the integrated circuit comprises a key generation circuit coupled to the physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the physically unclonable function circuit to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used so that the physically unclonable function circuit is used to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value. ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 17, Walker, in view of Ma, teaches the semiconductor package of claim 14, wherein the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a function circuit(154, ¶0181, ¶0191) coupled to both the front-side metal mesh(152 of 144, ¶0181) and the backside metal mesh(152 of 142, ¶0181).
Walker and Ma are not relied on to teach a physically unclonable function circuit.
Muchsel teaches a semiconductor package(Fig. 3) comprising a physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, to include a physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the integrated circuit comprises a physically unclonable function circuit coupled to both the front-side metal mesh and the backside metal mesh to output a first fingerprint value, wherein a modification of an electrical characteristic of at least one of the backside metal mesh or the front-side metal mesh causes the physically unclonable function circuit to output a second fingerprint value that is not equal to the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used to output a first fingerprint value, wherein a modification of an electrical characteristic of at least one of the backside metal mesh or the front-side metal mesh causes the physically unclonable function circuit to output a second fingerprint value that is not equal to the first fingerprint value ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 18, Walker, in view of Ma, teaches the semiconductor package of claim 17, but is not relied on to teach the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a key generation circuit coupled to the physically unclonable function circuit, the key generation circuit to derive a key for a cryptographic function at least in part on the first fingerprint value.
Muchsel teaches a semiconductor package(Fig. 3) wherein the integrated circuit(300, ¶0045) comprises a key generation circuit(310, ¶0045) coupled to the physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the integrated circuit comprises a key generation circuit coupled to the physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the key generation circuit to derive a key for a cryptographic function at least in part on the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used so that the key generation circuit can derive a key for a cryptographic function at least in part on the first fingerprint value ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 19, Walker, in view of Ma, teaches the semiconductor package of claim 17, but is not relied on to teach the integrated circuit die(176 as a sole chip, ¶0205, 150, 152, 154, ¶0181-182) comprises a cryptographic circuit coupled to the physically unclonable function circuit, the physically unclonable function circuit to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value.
Muchsel teaches a semiconductor package(Fig. 3) wherein the integrated circuit(300, ¶0045) comprises a cryptographic circuit(310, ¶0050) coupled to the physically unclonable function circuit(310, ¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Walker, so that the integrated circuit comprises a key generation circuit coupled to the physically unclonable function circuit, as taught by Muchsel, in order to eliminate the need to store keys in non-volatile memory and, render the semiconductor package immune to reverse engineering and other advanced methods by sophisticated attackers(¶0051).
The limitation of the physically unclonable function circuit to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value is a recitation how the product/device is being used. The structure as defined in Walker, in view of Ma and Muchsel could be used in the manner claimed (i.e. the structure of Walker, in view of Ma and Muchsel could be used so that the physically unclonable function circuit is used to disable the cryptographic circuit when the second fingerprint value is not equal to the first fingerprint value. ) and thus Walker, in view of Ma and Muchsel render obvious the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Response to Arguments
Applicant's arguments filed 4/3/2026 have been fully considered but they are not persuasive.
Regarding 1, Applicant's argue Walker's Paragraph [0205] is Non-Enabling Boilerplate That Cannot Supply Missing Structural Teaching The Examiner's rejection relies heavily on Walker's paragraph [0205], which states that "the inter-shield checking subsystem 174 may be implemented with other chip arrangements for example, but not limited to, non-back-to-back multi-chip arrangements such as piggy-back chip arrangements or with a chip arrangement including a sole chip such that the chip arrangement is formed from a single piece of material prior to the circuits being formed on the chip." See Walker, paragraph [0205]. The Examiner has alleged that this "sole chip" mention teaches the claimed structure of a single integrated circuit die having both a front-side metal mesh and a backside metal mesh. Applicant respectfully submits Walker [0205] is an aspirational "may be implemented" statement that provides no concrete structure and no reasonably teachable modification pathway. Such boilerplate cannot substitute for an actual disclosure when it is the only support for the Examiner's mapping.
The examiner respectfully submits that Walker expressly states the disclosed functionality may be implemented as a "sole chip" and this disclosure would be understood by one of ordinary skill in the art that the various structures described in reference to Fig. 10 of Walker may be integrated on a single chip. A person of ordinary skill in the art would understand the structure of Fig. 10 of Walker to have a sole chip 176 instead of dual chips 144 and 142.
Applicant's argue further Walker's only concrete fabrication/placement teaching for the "shield" appears at paragraph [0181], which teaches that "[t]he shield 152 is typically formed in the top layer of metal interconnects of each chip 142, 144." See Walker, paragraph [0181]. The Final Action identifies no portion of Walker that teaches forming or patterning a comparable structure on the opposite side of a sole chip, beyond the single conclusory sentence in [0205].
The examiner respectfully submits a person of ordinary skill in the art would understand the structure of Fig. 10 of Walker to have a sole chip 176 instead of dual chips 144 and 142. The top metal layer of 142 would correspond to the top layer of the sole chip 176 and the top layer metal of 144 would correspond to the bottom layer of sole chip 176.
Applicant's argue further The Combination of Walker and Ma Does Not Teach the Added Through-Substrate Coupling in the Amended Independent Claims the Final Action still does not identify a disclosure in Walker or Ma that supports the added through-substrate coupling between the relevant terminals in the amended independent claims. Instead, the rejection relies on importing a dual-chip signal routing discussion into a different "sole chip" context without evidentially support.
The examiner respectfully submits that Walker expressly states the disclosed functionality may be implemented as a "sole chip" and this disclosure would be understood by one of ordinary skill in the art that the various structures described in reference to Fig. 10 of Walker may be integrated on a single chip. A person of ordinary skill in the art would understand the structure of Fig. 10 of Walker to have a sole chip 176 instead of dual chips 144 and 142. Thus Walker in view of Ma discloses the front-side active circuitry(150 of 144) is coupled to the backside metal mesh(152 of 142) through the first- level interconnect terminal (166), the substrate(162), and the backside interconnect terminal(164).
Conclusion
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/LAURA M DYKES/Examiner, Art Unit 2892
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