DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 6/5/2026. Claims 1-25 are pending and have been examined. Claims 1, 3, 15, 17, 19-20 and 24-25 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7, 18 and 23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In regards to claim 7, the limitation stating “…wherein the complex number matrix multiplication instruction has one or more matrix size indicators to indicate one or more of the M rows of the first source complex number matrix, the K columns of the first source complex number matrix, and the N columns of the second source complex number matrix” fails to comply with the written description requirement, based on amendments made to claim 1 from which claim 7 depends upon; wherein claim 1 now states “…wherein the complex number matrix multiplication instruction has a matrix size indicator to select one of a plurality of different supported matrix shapes for at least one of the first and second source complex number matrices”. Thus, claim 7 fails to comply with the written description requirement because the original disclosure does not properly describe an instruction that includes both (1) a matrix size indicator to select one of a plurality of different supported matrix shapes for at least one of the first and second source complex number matrices and (2) one or more matrix size indicators to indicate one or more of the M rows of the first source complex number matrix, the K columns of the first source complex number matrix, and the N columns of the second source complex number matrix in sufficient detail that one skilled in the art can reasonably conclude the inventor had possession of the claimed invention.
Specifically, paragraph [00231] and Fig. 18 disclose a matrix indicator (element 1834) which in one embodiment uses a single indicator to select one of a fixed number of different possible supported predetermined combinations of matrix shapes and in another embodiment provides three matrix indicators to specify a number of rows or columns for matrices. However, the specification does not provide a single embodiment which includes all of the matrix size indicators which are claimed in the combination of claims 1 and 7, rather the specification provides two different alternative embodiments that may be used to implement matrix size indicators in element 1834. Thus, the disclosure does not appear to provide support for claim 7.
Claims 18 and 23 are similarly rejected on the same basis as claim 7 above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “An apparatus” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…complex number matrix multiplication…perform operations corresponding to a complex number matrix multiplication… the complex number matrix multiplication… to indicate a first source complex number matrix having M rows by K columns of complex numbers, a second source complex number matrix having K rows by N columns of complex numbers, wherein at least one of the first and second source complex number matrices …and wherein the complex number matrix multiplication…select one of a plurality of different supported matrix shapes for at least one of the first and second source complex number matrices, the operations including, for each row m of the M rows, and for each column n of the N columns, to: generate K complex numbers by K complex multiplications of K complex numbers of the row m of the first source complex number matrix with K corresponding complex numbers of the column n of the second source complex number matrix; combine the K generated complex numbers to generate a complex number…combine the generated complex number with a complex number at, a row m of M rows and a column n of N columns of a destination complex number matrix…” which describe a process that under its broadest reasonable interpretation encompasses mathematical calculations and mental processes. That is other than reciting generic computing components (e.g. a cache, registers, non-register storage, circuitry and a processor) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses performing matrix multiplication of two matrices including complex values with an optional accumulation of values (see paragraphs [00203-00205] of applicant’s specification which disclose arithmetic equations that correspond to the mathematics indicated in the claim), thus the limitation encompasses mathematical calculations (MPEP 2106.04(a)(2)(I)(C)). Further, the claims discuss a selection of a matrix shape for at least one of the first and second complex matrices thus the limitation encompasses mental processes (MPEP 2106.04(a)(2)(III)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation or a mental process in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within both the “Mathematical concepts” and “Mental process” groupings of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
a cache; a processor coupled with the cache, the processor comprising registers and non-register matrix storage, the processor including …circuitry… the processor to perform…an instruction… is to be stored in the non-register matrix storage… instruction has a matrix size indicator …
and either store the generated complex number at a row m of M rows and a column n of N columns of a destination
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)) and ties the abstract idea to a particular type of data/technological field (complex number matrices and matrix sizes), e.g. a particular field of use or technological environment (MPEP 2106.05(h));and (b) recites insignificant extra-solution activity (i.e. data outputting) (See MPEP 2106.05 (g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)) and ties the abstract idea to a particular type of data/technological field (complex number matrices and matrix sizes), e.g. a particular field of use or technological environment (MPEP 2106.05(h)). While, (b) recites insignificant extra-solution activity of data outputting (see MPEP 2106.05(g)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
7. Claim 2, dependent upon claim 1 further recites “…wherein the processor is a central processing unit (CPU), and wherein the CPU comprises: decode circuitry to decode the… instruction; and execution circuitry coupled with the decode circuitry, the execution circuitry to perform the operations corresponding to the… instruction” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Furthermore, using computer components such as decoder and execution circuitry can be viewed as well-understood, routine and conventional because it is well-known in computer architecture to process instructions by using a pipeline which include decode and execute circuitry (See NPL reference “Computer Architecture A Quantitative Approach”, pages C-34 to C-35 and 232). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
8. Claim 3, dependent upon claim 1 further recites“…wherein the processor is a graphics processing unit (GPU), and wherein the GPU comprises: decode circuitry to decode… the instruction; scheduler circuitry coupled with the decode circuitry, the scheduler circuitry to schedule… the instruction; a plurality of execution circuits, each corresponding to a different thread of a thread group, the plurality of execution circuits to collectively perform the operations corresponding to the instruction; and a plurality of sets of registers, each corresponding to a different one of the plurality of execution circuits, the plurality of sets of registers to collectively store the first source, the second source, and the destination…” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)) and ties the abstract idea to a particular technological environment (e.g. a GPU multi-threaded environment) (MPEP 2106.05(h)). Furthermore, using computer components such as decoder, scheduler, execution circuits and register files can be viewed as well-understood, routine and conventional because it is well-known in GPU architectures to include those types of hardware when executing SIMT instructions (See NPL reference “Computer Architecture A Quantitative Approach”, pages C-34 to C-35 and pages 291-297 and 310). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
9. Claim 4, dependent upon claim 3, further recites “…wherein the instruction has a synchronization indicator to synchronize the threads of the thread group by causing the threads of the thread group to wait until all other of the threads of the thread group have executed … prior to execution of other subsequent instructions” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Furthermore, the additional limitation ties the abstract idea to a particular field of use or technological environment (SIMT multi-threaded processor environment) (MPEP 2106.05(h)). Furthermore, synchronizing threads of a thread group can be viewed as well-understood, routine and conventional because it is well-known in graphics processing to synchronize threads of a thread group (See NPL reference “Computer Architecture A Quantitative Approach”, pages 313-314). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
10. Claim 5, dependent upon claim 3, further recites “…wherein the instruction has an alignment indicator to indicate that the threads of the thread group are to execute the same… instruction” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Furthermore, the additional limitation ties the abstract idea to a particular field of use or technological environment (SIMT multi-threaded processor environment) (MPEP 2106.05(h)). Furthermore, executing a same instruction across multiple threads simultaneously can be viewed as well-understood, routine and conventional because it is well-known in graphics processing to execute SIMT instructions (See NPL reference “Computer Architecture A Quantitative Approach”, pages 291-297 and 310). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
11. Claim 6, dependent upon claim 1, further recites “wherein the complex number matrix multiplication instruction is a single-instruction, multiple-thread (SIMT) instruction” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Furthermore, the additional limitation ties the abstract idea to a particular field of use or technological environment (multi-threaded processor environment) (MPEP 2106.05(h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
12. Claim 7, dependent upon claim 1, further recites “…wherein the complex number matrix multiplication instruction has one or more matrix size indicators to indicate one or more of the M rows of the first source complex number matrix, the K columns of the first source complex number matrix, and the N columns of the second source complex number matrix”, which discloses a size indicator used in the instruction to indicate a size of the matrices used in the abstract idea. Thus, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)) and ties the abstract idea to a particular type of data (matrix data with a particular number of columns and rows), e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
13. Claim 8, dependent upon claim 1, further recites “…wherein the complex number matrix multiplication instruction has a matrix layout indicator to indicate a layout of one of the first and second source complex number matrices as being either a row-major layout or a column major layout”, which discloses a matrix layout indicator used in the instruction to indicate a layout of the matrices used in the abstract idea. Thus, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)) and ties the abstract idea to a particular type of data (matrix in a column or row major layout), e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
14. Claim 9, dependent upon claim 1, further recites “…wherein the destination complex number matrix has an integer multiple of four complex numbers” which discloses a number of elements stored in the destination matrix used in the abstract idea of claim 1. Thus, the claim recites additional embellishments of the abstract idea of claim 1 and includes no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
15. Claim 10, dependent upon claim 1, further recites “…the processor is to perform operations corresponding to a real number matrix multiplication instruction, the real number matrix multiplication instruction to indicate a first source real number matrix having M' rows by K' columns of real numbers, a second source real number matrix having K' rows by N' columns of real numbers, and the operations including, for each row m' of the M' rows, and for each column n' of the N' columns, to: generate K' real numbers by K' real multiplications of K' real numbers of the row m' of the first source real number matrix with K' corresponding real numbers of the column n' of the second source real number matrix; combine the K' generated real numbers to generate a real number; and either store the generated real number at, or combine the generated real number with a real number at, a row m' of M' rows and a column n' of N' columns of a destination real number matrix”, which discloses an additional abstract idea performed using generic computing components to store a result of the abstract idea. Thus, the additional limitations tie the abstract ideas to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f) and insignificant extra-solution activities (data outputting) which are well-understood, routine and conventional (see MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
16. Claim 11, dependent upon claim 10, further recites “…wherein the processor includes circuitry to be configured by the complex number matrix multiplication instruction to perform the operations corresponding to the complex number matrix multiplication instruction, and wherein the circuitry is to be configured by the real number matrix multiplication instruction to perform the operations corresponding to the real number matrix multiplication instruction”, thus the limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
17. Claim 12, dependent upon claim 1, further recites “wherein the processor, for each said row m of the M rows of the first source complex number matrix, and for each said column n of the N columns of the second source complex number matrix, is to generate the K complex numbers concurrently” which ties the abstract idea of claim 1 to being performed in a parallel computing environment such as a GPU. Thus, the additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)) and to a particular technological computing environment (e.g. parallel computing) (see MPEP 2106.05(h)). Furthermore, parallel computing can be viewed as well-understood, routine and conventional because it is well-known to execute operations concurrently (See NPL reference “Computer Architecture A Quantitative Approach”, pages 9-10 and 291-294). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
18. Claim 13, dependent upon claim 1, further recites “…wherein the processor, for each said row m of the M rows of the first source complex number matrix, and for each said column n of the N columns of the second source complex number matrix, is to generate a plurality of portions of the K complex numbers sequentially” which ties the abstract idea of claim 1 to being performed sequentially in a processor. Thus, the additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)) and to a particular technological computing environment (e.g. sequential loop computing) (see MPEP 2106.05(h)). Furthermore, sequential computing can be viewed as well-understood, routine and conventional because it is well-known to execute operations sequentially (See NPL reference “Computer Architecture A Quantitative Approach”, pages C-34 to C-35 and 313). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
19. Claim 14, dependent upon claim 1, further recites “…wherein the processor is to combine the generated complex number with the complex number at the row m of the M rows and the column n of the N columns of the destination complex number matrix” which recites further details of the abstract idea recited in claim 1. Further, the claim recites additional the limitations that tie the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
20. Claims 15, 19 and 24 are similarly rejected on the same basis as claim 1 above.
21. Claims 16-18, 20-23 and 25 are similarly rejected on the same basis as claims 3-4, 7 and 14 above.
Claim Rejections - 35 USC § 103
22. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
23. Claim(s) 1-2, 7-8, 10-16, 18-19 and 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zivkovic, PGPUB No. 2020/0310820, Grochowski, PGPUB No. 2019/0258481 and further in view of Milanovic, PGPUB No. 2021/0042261.
In regards to claim 1, Zivkovic discloses An apparatus (See Fig. 12) comprising: a cache; and a processor coupled with the cache (See Fig. 12 and [0142]: wherein a L3 cache (element 1216) is coupled with the processor (element 1255)) the processor comprising registers ([0141]: wherein registers (1206) store matrix data) the processor including complex number matrix multiplication circuitry to perform operations corresponding to a complex number matrix multiplication instruction ([0143, 0158, 0181-0182]: wherein a processor includes an matrix accelerator to perform multiply accumulate instructions using complex numbers (see abstract, 0145-0147, 0158 and Fig. 21 for further clarity)) the complex number matrix multiplication instruction to indicate a first source complex number matrix having a row and a column of complex numbers, a second source complex number matrix having a row by a column of complex numbers ([0145-0147]: wherein a complex multiplication or alternatively multiplication and accumulation instruction indicates a first and a second source vector registers each storing a 1x1 matrices of complex numbers) wherein at least one of the first and second source complex matrices is to be stored in the registers ([0141-0147])the operations including, for each row m, and for each column n, to: generate K complex numbers by K complex multiplications of K complex numbers of the row m of the first source complex number matrix with K corresponding complex numbers of the column n of the second source complex number matrix ([0145-0147] and See Fig. 13 resultants of multipliers (element 1302)) combine the K generated complex numbers to generate a complex number ([0145-0147]: wherein adders (1303) combine the generated complex numbers to generate a complex number (See Fig. 13)) and either store the generated complex number at, or combine the generated complex number with a complex number at, a row and a column n of a destination complex number matrix. ([0145-0147]: wherein a generated complex number result is stored at 1x1 matrix destination register for operand z or combined with a complex number in an accumulator register)
Zivkovic does not disclose the processor comprising non-register matrix storage, a matrix multiplication instruction indicating a first source matrix having M rows by K columns of number, a second source complex number matrix having K rows by N columns of complex numbers, wherein at least one of the first and second source complex number matrices is to be stored in the non-register matrix storage, and wherein the complex number matrix multiplication instruction has a matrix size indicator to select one of a plurality of different supported matrix shapes for at least one of the first and second source complex number matrices, the operations including, for each row m of the M rows, the operations including, for each row m of the M rows, and for each column n of the N columns, to: generate K numbers by K multiplications of K numbers of the row m of the first source number matrix with K corresponding numbers of the column n of the second source number matrix; combine the K generated numbers to generate a number; and either store the generated number at, or combine the generated number with a number at, a row m of M rows and a column n of N columns of a destination number matrix. Zivkovic generally discloses performing complex number matrix operations using 1x1 matrices using vector registers, and additionally discloses performing real matrix multiplication using a NxM matrix and a 1xM matrix ([0148]), however Zivkovic has not explicitly disclosed performing matrix multiplication using MxN and KxN sized matrices.
Grochowski discloses non-register matrix storage ([0028]: wherein system memory stores matrices) a matrix multiplication instruction indicating a first source matrix having M rows by K columns of number, a second source complex number matrix having K rows by N columns of complex numbers ([0064-0065]: wherein the matrix multiplication and/or accumulation instruction indicates a first source matrix A having a number of rows and columns and a source matrix B having a number of rows and columns. Wherein the number of columns of matrix A equals the number of rows of matrix B) wherein at least one of the first and second source matrices is to be stored in the non-register matrix storage ([0028 and 0064]) and wherein the matrix multiplication instruction has a matrix size indicator to select one of a plurality of different supported matrix shapes for at least one of the first and second source matrices ([0032-0033]: wherein a matrix dimension indicator selects one of a plurality of different fixed size matrices supported for at least one of the matrices operands) the operations including, for each row m of the M rows, the operations including, for each row m of the M rows, and for each column n of the N columns, to: generate K numbers by K multiplications of K numbers of the row m of the first source number matrix with K corresponding numbers of the column n of the second source number matrix; combine the K generated numbers to generate a number; and either store the generated number at, or combine the generated number with a number at, a row m of M rows and a column n of N columns of a destination number matrix. ([0064, 0069 and 0078]: wherein source matrices A and B are multiplied to generate K number of products which are combined and then a result is stored to matrix C or a result is accumulated with data in matrix C (See Fig. 5))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the complex matrix multiply accumulate instructions of Zivkovic to use two-dimensional source matrices and a matrix size indicator such that a plurality of rows and columns are used in the operations as the matrix multiply and accumulate instructions of Grochowski. It would have been obvious to one of ordinary skill in the art because it would allow the instructions of Zivkovic to operate on predetermined size matrices allowing for a simplified implementation that would optimize execution logic and/or operate on flexible/arbitrary sized matrices (Grochowski [0032-0033]). Furthermore, the courts have deemed that changes in size are obvious, thus it would have been obvious to execute complex matrix operations using 2-D matrices (See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (MPEP 2144.04(IV)(A)).
The combination of Zivkovic and Grochowski does not explicitly disclose the processor comprising non-register matrix storage nor wherein at least one of the first and second source matrices is to be stored in the non-register matrix storage. Grochowski does disclose non-register matrix storage in an external system memory, and thus does not explicitly disclose a processor comprising non-register matrix storage.
Milanovic discloses the processor comprising non-register matrix storage ([0071] and Fig. 1) wherein at least one of the first and second source matrices is to be stored in the non-register matrix storage. ([0071 and 0073-0074]: wherein a processor comprises a scratchpad or cache memory to store matrices ([0101-0102])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Zivkovic and Grochowski to use non-register matrix storage as the processor of Milanovic. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using non-register matrix data storage in a processor as taught in Milanovic) for another (using register matrix storage or main memory matrix storage as taught in Zivkovic and Grochowski) to yield predictable results (using non-register matrix storage in a processor) (MPEP 2143, Example B). Furthermore, using non-register memory such as a processor cache can free register space in a processor, which would reduce register pressure and improve register resource allocation.
Claim 15 is similarly rejected on the same basis as claim 1 above as claim 15 is the method claim corresponding to the apparatus of claim 1 above.
Claim 19 is similarly rejected on the same basis as claim 1 above as claim 19 is the system claim corresponding to the apparatus of claim 1 above. (Note: Claim 15 discloses an additional limitation stating a processor coupled to a DRAM memory. This limitation is disclosed in Zivkovic [0116 and 12A]: discloses a system memory coupled to processor (element 1255), wherein system memory can be a DRAM)
Claim 24 is similarly rejected on the same basis as claim 1 above as claim 24 is the non-transitory medium claim corresponding to the apparatus of claim 1 above. (Note: Claim 24 discloses an additional limitation stating a non-transitory medium. This limitation is disclosed in Zivkovic [0133-0134 and 0229])
In regards to claim 2, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the processor is a central processing unit (CPU), and wherein the CPU comprises: decode circuitry to decode the complex number matrix multiplication instruction (Zivkovic [0138, 0140 and Fig. 12A]|Grochowski: See Fig. 1) and execution circuitry coupled with the decode circuitry, the execution circuitry to perform the operations corresponding to the complex number matrix multiplication instruction. (Zivkovic [0138, 0143 and Fig. 12A]| Grochowski: See Fig. 1))
In regards to claim 7, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the complex number matrix multiplication instruction has one or more matrix size indicators to indicate one or more of the M rows of the first source complex number matrix, the K columns of the first source complex number matrix, and the N columns of the second source complex number matrix. (Grochowski [0032-0033]: wherein matrix instruction includes matrix dimension indicators indicating number of rows and columns of each source matrix)
Claim 18 is similarly rejected on the same basis as claim 7 above as claim 18 is the method claim corresponding to the apparatus of claim 7 above.
Claim 23 is similarly rejected on the same basis as claim 7 above as claim 23 is the system claim corresponding to the apparatus of claim 7 above.
In regards to claim 8, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the complex number matrix multiplication instruction has a matrix layout indicator to indicate a layout of one of the first and second source complex number matrices as being either a row-major layout or a column major layout. (Grochowski [0061]: wherein matrix instruction has a memory layout dimension indicator indicated a row-major or column major layout of one of the matrix source operands)
In regards to claim 10, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the processor is to perform operations corresponding to a real number matrix multiplication instruction, the real number matrix multiplication instruction to indicate a first source real number matrix having M' rows by K' columns of real numbers, a second source real number matrix having K' rows by N' columns of real numbers (Zivkovic [0181-0188]| Grochowski [0027, 0108 and Figs. 1 and 5]) and the operations including, for each row m' of the M' rows, and for each column n' of the N' columns, to: generate K' real numbers by K' real multiplications of K' real numbers of the row m' of the first source real number matrix with K' corresponding real numbers of the column n' of the second source real number matrix; combine the K' generated real numbers to generate a real number; and either store the generated real number at, or combine the generated real number with a real number at, a row m' of M' rows and a column n' of N' columns of a destination real number matrix. (Zivkovic [0181-0188] | Grochowski [0027, 0108 and Figs. 1 and 5])
In regards to claim 11, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 10 (see rejection of claim 10 above) wherein the processor includes circuitry to be configured by the complex number matrix multiplication instruction to perform the operations corresponding to the complex number matrix multiplication instruction, and wherein the circuitry is to be configured by the real number matrix multiplication instruction to perform the operations corresponding to the real number matrix multiplication instruction. (Zivkovic [0139, 0147 and 0181-0182]: wherein complex number multiply accumulate operations and real number matrix multiply accumulate operations are performed using existing complex multiply accumulate circuitry (also see abstract and Figs. 13 and 17-18))
In regards to claim 12, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the processor, for each said row m of the M rows of the first source complex number matrix, and for each said column n of the N columns of the second source complex number matrix, is to generate the K complex numbers concurrently. (Zivkovic [0206] |Grochowski [0097-0098])
In regards to claim 13, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above).
The combination of Zivkovic, Grochowski and Milanovic thus far does not disclose wherein the processor, for each said row m of the M rows of the first source complex number matrix, and for each said column n of the N columns of the second source complex number matrix, is to generate a plurality of portions of the K complex numbers sequentially.
Grochowski discloses wherein the processor, for each said row m of the M rows of the first source matrix, and for each said column n of the N columns of the second source matrix, is to generate a plurality of portions of the K numbers sequentially. ([0041-0045 and 0078-0079]: wherein matrices are multiplied in sequences such that portions of generated products are generated sequentially. (see abstract))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the matrix multiply instruction of Zivkovic to be performed sequentially such that the instruction can be stopped and restarted using intermediate matrix multiply results such as the matrix multiply instruction of Grochowski. It would have been obvious because this may help to ensure continued forward progress in the face of possible interruptions, and may tend to be especially advantageous for long or extremely long completion times of the matrix multiplication instructions (Grochowski [0046]).
In regards to claim 14, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the processor is to combine the generated complex number with the complex number at the row m of the M rows and the column n of the N columns of the destination complex number matrix. (Zivkovic [0147 and Fig. 13] | Grochowski [0064-0065])
Claim 16 is similarly rejected on the same basis as claim 14 above as claim 16 is the method claim corresponding to the apparatus of claim 14 above.
Claim 22 is similarly rejected on the same basis as claim 14 above as claim 22 is the system claim corresponding to the apparatus of claim 14 above.
24. Claim(s) 3, 6, 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zivkovic, Grochowski, Milanovic and further in view of Pisha, USPAT No. 12,475,189.
In regards to claim 3, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the processor comprises: decode circuitry to decode the complex number matrix multiplication instruction and execute circuitry to execute the complex number matrix multiplication instruction (Zivkovic [0138-0139 and 0143-0147]: wherein processor comprises decode circuitry to decode complex matrix multiply and accumulate instructions and execution circuitry (See Fig. 12A-13))
The combination of Zivkovic, Grochowski and Milanovic thus far does not explicitly disclose processor of Fig. 12A being a graphics processing unit.
However, Zivkovic discloses a processor is a graphics processing unit ([0093 and 0108])
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Fig. 12A of Zivkovic to be a graphics processing unit. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention because it would have been the simple substitution of one known element (executing instructions using a graphics processing unit) for another (executing instructions using a generic processing unit) to obtain predictable results (executing complex matrix multiplication instructions using a graphics processing unit) (MPEP 2143, Example B).
The combination of Zivkovic, Grochowski and Milanovic does not further disclose scheduler circuitry to schedule the complex number matrix multiplication instruction; a plurality of execution circuitry, each corresponding to a different thread of a thread group, the plurality of execution circuitry to collectively perform the operations corresponding to the complex number matrix multiplication instruction; and a plurality of sets of registers, each corresponding to a different one of the plurality of execution circuitry, the plurality of sets of registers to collectively store the first source complex number matrix, the second source complex number matrix, and the destination complex number matrix. Zivkovic discloses using a plurality of cores to executes threads simultaneously ([0140]), however Zivkovic does not disclose using a plurality of execution circuits to collectively perform the operations corresponding to the complex number matrix multiplication instruction. Thus, another reference is brought in for that teaching.
Pisha discloses scheduler circuitry to schedule the complex matrix multiplication instruction (Column 5, lines 1-10 and 30-45 and Column 58, lines 13-14 to Column 59, lines 5-38: wherein scheduler unit schedules complex matrix multiply accumulate instruction) a plurality of execution circuits, each corresponding to a different thread of a thread group, the plurality of execution circuits to collectively perform the operations corresponding to the complex matrix multiplication instruction (Column 57, lines 43-55, Column 58, lines 14-40, and Column 59, lines 5-38: wherein a plurality of execution circuits are disclosed each corresponding to a different thread within a thread group to collectively perform the operations corresponding to a complex matrix multiplication (See Fig. 29)) and a plurality of sets of registers, each corresponding to a different one of the plurality of execution circuits, the plurality of sets of registers to collectively store the first source complex number matrix, the second source complex number matrix, and the destination complex number matrix. (Column 5, lines 1-9, Column 57, lines 43-55, Column 58, lines 14-40, and Column 59, lines 5-47: wherein a plurality of sets of registers of a register file each correspond to a different one of a plurality of execution circuits and each collectively store matrices needed for the mma instructions (See Fig.29))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the graphics processing unit of Zivokic which performs complex multiply accumulate instructions to use a SIMT architecture which executes complex matrix accumulate instructions using a graphics processing unit as taught in Pisha. It would have been obvious to one of ordinary skill in the art because using a SIMT architecture can be used for the benefits of massive parallelism and improved processing efficiency which can optimize graphics processing units.
Claim 20 is similarly rejected on the same basis as claim 3 above as claim 20 is the system claim corresponding to the apparatus of claim 3 above.
In regards to claim 6, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above).
The combination of Zivkovic, Grochowski and Milanovic does not disclose wherein the complex number matrix multiplication instruction is a single-instruction, multiple-thread (SIMT) instruction. Zivkovic does disclose executing a complex matrix multiply instruction in a multi-threading environment but does not explicitly indicate executing the instruction in a SIMT architecture.
Pisha discloses wherein the complex number matrix multiplication instruction is a single-instruction, multiple-thread (SIMT) instruction (Column 5, lines 1-5 and 31-45, Column 45, lines 16-26, Column 57, lines 53-55: wherein a complex MMA instruction is executed in a SIMT environment and thus is a SIMT instruction)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the graphics processing unit of Zivokic which performs complex multiply accumulate instructions to use a SIMT architecture which executes complex matrix accumulate instructions using a graphics processing unit as taught in Pisha. It would have been obvious to one of ordinary skill in the art because using a SIMT architecture can be used for the benefits of massive parallelism and improved processing efficiency which can optimize graphics processing units.
In regards to claim 9, the combination of Zivkovic, Grochowski and Milanovic discloses The apparatus of claim 1 (see rejection of claim 1 above).
The combination of Zivkovic, Grochowski and Milanovic does not explicitly disclose wherein the destination complex number matrix has an integer multiple of four complex numbers. Grochowski does disclose that a destination matrix can be of any arbitrary size, but does explicitly disclose that that size includes an integer multiple of four.
Pisha discloses wherein the destination complex number matrix has an integer multiple of four complex numbers. (See Figs. 2-3 and Column 5, lines 46-67: wherein a destination complex number has an integer multiple of four complex numbers (8x4 or 8x8))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the destination matrix of Zivkovic, Grochowski and Milanovic to include a multiple of four complex numbers as the destination matrix of Pisha. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention because it would have been the simple substitution of one known element (using a destination matrix size that is a integer multiple of four) for another (using a generic or arbitrary size destination matrix) to obtain predictable results (executing complex matrix multiplication instructions to store complex number results that are a multiple of four to a destination matrix) (MPEP 2143, Example B). Furthermore, the courts have deemed that changes in size are obvious, thus it would have been obvious to include a destination matrix that has a multiple of four numbers (See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (MPEP 2144.04(IV)(A)).
25. Claim(s) 4-5, 17, 21 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zivkovic, Grochowski, Milanovic, Pisha and further in view of NPL reference, “Parallel Thread Execution ISA” hereby referred to as PTX.
In regards to claim 4, the combination of Zivkovic, Grochowski, Milanovic and Pisha discloses The apparatus of claim 3 (see rejection of claim 3 above).
The combination of Zivkovic, Grochowski, Milanovic and Pisha does not disclose wherein the complex number matrix multiplication instruction has a synchronization indicator to synchronize the threads of the thread group by causing the threads of the thread group to wait until all other of the threads of the thread group have executed the complex number matrix multiplication prior to execution of other subsequent instructions.
PTX discloses wherein a matrix multiplication instruction has a synchronization indicator to synchronize the threads of the thread group by causing the threads of the thread group to wait until all other of the threads of the thread group have executed the matrix multiplication prior to execution of other subsequent instructions. (pages 275-277: wherein a warp-level mma instruction includes a. sync qualifier to synchronize threads of a warp causing threads to wait until all other threads of the warp have executed the same mma instruction before resuming execution)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the complex matrix multiply instructions of Zivkovic, Grochowski, Milanovic and Pisha to include a synchronization indicator as the matrix multiply instructions of PTX. It would have been obvious to one of ordinary skill in the art because including a synchronization indicator to allow the threads of a warp in a SIMT architecture to synchronize ensures data consistency in shared memory.
Claim 17 is similarly rejected on the same basis as claim 4 above as claim 17 is the method claim corresponding to the apparatus of claim 4 above.
Claim 21 is similarly rejected on the same basis as claim 4 above as claim 21 is the system claim corresponding to the apparatus of claim 4 above.
Claim 25 is similarly rejected on the same basis as claim 4 above as claim 25 is the non-transitory medium claim corresponding to the apparatus of claim 4 above.
In regards to claim 5, the combination of Zivkovic, Grochowski, Milanovic and Pisha discloses The apparatus of claim 3 (see rejection of claim 3 above).
The combination of Zivkovic, Grochowski, Milanovic and Pisha does not disclose wherein the complex number matrix multiplication instruction has an alignment indicator to indicate that the threads of the thread group are to execute the same complex number matrix multiplication instruction.
PTX discloses wherein a matrix multiplication instruction has an alignment indicator to indicate that the threads of the thread group are to execute the same matrix multiplication instruction. (pages 275-277: wherein a warp-level mma instruction includes a align qualifier to indicate that threads of a warp are to execute the same mma instruction)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the complex matrix multiply instructions of Zivkovic, Grochowski, Milanovic and Pisha to include a align indicator as the matrix multiply instructions of PTX. It would have been obvious to one of ordinary skill in the art because including a align indicator ensures that all threads of a warp are working with a synchronized data layout, for complex operations where data is distributed across the registers of multiple threads within a warp, thus ensuring data consistency.
Response to Arguments
26. Applicant’s arguments, see page 1 of the remarks filed on 6/5/2026, with respect to claim objections have been fully considered and are persuasive. Therefore, the objections have been withdrawn.
27. Applicant's arguments filed on 6/5/2026, with respect to 35 USC 101 rejections have been fully considered but they are not persuasive. Thus, the previous 35 USC 101 rejections have been maintained.
28. Applicant argues the 101 rejections on pages 2-3 of the remarks, in the substance that:
“By supporting the claimed complex number matrix multiplication instruction, multiplication of complex numbers may be performed faster and/or more efficiently and/or with lower power consumption compared to if a software sequence of instructions needed to be used to perform matrix multiplication of complex numbers instead. Also, by the processor supporting the claimed complex number matrix multiplication instruction, code using matrix multiplication of complex numbers (e.g., digital signal processing, machine learning, etc.) can be more compact thus requiring less time to execute and/or less energy to execute and/or requiring less memory or energy to store and/or load the code. Both of these represent an improvement to the functioning of a computer itself.
Also, claim 1 recites "the processor including complex number matrix multiplication circuitry to perform operations corresponding to a complex number matrix multiplication instruction." (emphasis added) The complex number matrix multiplication circuitry is not a "generic computer component".
Accordingly, the present claims are not directed to a judicial exception because they recite additional elements demonstrating that the claim as a whole integrates the exception into a practical application since the claimed invention represents an improvement to the functioning of a computer itself. See e.g., MPEP 2106.04(d)(1)”
The examiner respectfully disagrees with the applicant’s assertions above. The examiner cites MPEP 2106.04(d)(1) which states “…if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology. Second, if the specification sets forth an improvement in technology, the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement. That is, the claim includes the components or steps of the invention that provide the improvement described in the specification.” The examiner notes that the applicant has stated an improvement in paragraph [00207] and in the above arguments that appear to describe how using a single instruction to perform the abstract idea (e.g. math) improves processor functionality because it requires less code and thus the math could be performed faster. However, this is recited in a conclusory manner without any detail of what steps or components of the invention provide the improvement to the functioning of the computer (e.g. what components were changed in the processor to improve efficiency and speed of processor?)
Furthermore, the examiner asserts that the claims do not reflect an improvement to the functioning of the processor but merely recite instructions to implement an abstract idea or other exception on a computer (e.g. “apply it”) (MPEP 2106.05(f)). In particular MPEP 2106.05(f) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general-purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more….Similarly, "claiming the improved speed or efficiency inherent with applying the abstract idea on a computer" does not integrate a judicial exception into a practical application or provide an inventive concept.” The examiner asserts the current claims merely recite using a single instruction to perform math on a processor and as indicated above inherency of improved speed or efficiency with applying the abstract idea on a computer does not integrate a judicial exception into a practical application.
Furthermore, the improvements argued above appear to reflect an improvement to the abstract idea itself (e.g. performing a complex number matrix multiplication algorithm with less code). An improvement to an abstract idea does not reflect an improvement to the functioning of a computer (MPEP 2106.04(a)(2): ‘‘the discovery of [a mathematical formula] cannot support a patent unless there is some other inventive concept in its application. Flook, 437 U.S. at 594, 198 USPQ at 199. MPEP 2106.04, I. Flook, 437 U.S. at 591-92, 198 USPQ2d at 198 ("the novelty of the mathematical algorithm is not a determining factor at all"))
The applicant then argues that the limitation stating “complex number matrix multiplication circuitry” is not a generic computing component but the examiner disagrees because this is “generic circuitry” which performs matrix multiplication using complex numbers, and there are no distinguishing limitations that would indicate this is anything other than generic multipliers, adders and/or accumulators as known in the art to perform matrix multiplication.
29. Applicant’s arguments, see page 4 of the remarks with respect to the rejection(s) of claim(s) 1, 15, 19 and 24 under 35 USC 103 in view of Zivkovic and Grochowski have been fully considered and are partially persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Zivkovic, Grochowski and Milanovic.
Claims 2-14, 16-18, 20-23 and 25 are argued at least based on dependency upon one of the independent claims above and therefore remain rejected at least based upon their respective dependencies.
30. Applicant argues on page 4 of the remarks, the combination of Zivkovic and Grochowski, in the substance that:
“Firstly, Zivkovic and Grochowski do not disclose or render obvious that "the complex number matrix multiplication instruction has a matrix size indicator to select one of a plurality of different supported matrix shapes for at least one of the first and second source complex number matrices."
The examiner respectfully disagrees because Grochowski paragraphs [0032-0033] disclose various matrix size (dimension) indicators that can select any number of a predetermined size matrices or specific a number of rows and columns of matrices. Thus, Grochowski discloses the above amended limitation.
Conclusion
31. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
32. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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