DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a gate structure having a backside gate contact extension”, “a shallow trench isolation structure located entirely beneath the gate structure, and “the backside gate contact extension is…present in a lower portion of the shallow trench isolation structure” (emphases added).
Since the backside gate contact extension as claimed is part of the gate structure, and the shallow trench isolation structure as claimed is required to be entirely beneath the gate structure, the shallow trench isolation structure is required to be entirely beneath the gate contact extension. However, claim 1 also requires the backside gate contact extension to be present in the shallow trench isolation structure. It is unclear how the shallow trench isolation structure could be both entirely beneath the gate structure (including the gate contact extension), and the gate contact extension also located in the shallow trench isolation structure. This renders the scope of claim 1 indefinite.
For the purpose of compact prosecution, the Examiner has interpreted the gate contact extension to be consistent with the prior art cited below.
Claims 2-17 and 19-20 depend on claim 1, and are rejected for implicitly including the indefinite subject matter above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 15-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liaw (PG Pub. No. US 2024/0006417 A1).
Regarding claim 1, Liaw teaches a semiconductor structure (¶ 0014: 100) comprising:
a gate structure (¶ 0054: 128, including portions 128N and 128P) having a backside gate contact extension (¶¶ 0082, 0088: 142 and/or 146B);
a shallow trench isolation structure (¶¶ 0066, 0083: 132 and/or 138) located entirely beneath the gate structure (fig. 2D-2 among others: 132/138 located entirely beneath 128N/128P);
a frontside interlayer layer (¶ 0061: 130) located above the shallow trench isolation structure and surrounding the gate structure (fig. 2D-2: 130 located above 132/138 and surrounds 128N/128P), wherein the backside gate contact extension is located entirely beneath the frontside interlayer dielectric layer and present in a lower portion of the shallow trench isolation structure (fig. 2D-2: 142/146B entirely beneath 130, and at least a portion of 132/138 present in 132/138);
a first backside metal level (¶ 0088: M1) comprising a pair of spaced apart backside power rails (¶ 0088 & fig. 2D-2: M1 includes 146A/Vss and 146A/Vdd) and located beneath the backside gate contact extension of the gate structure (fig. 2D-2: 146A located beneath a portion of 142/146B) and beneath the shallow trench isolation structure (fig. 2D-2: 146A located beneath 132/138);
a second backside metal level (¶ 0095: M2, including portion 152) comprising a backside signal line (¶ 0096: 152 comprises a conductive layer suitable for signal transmission, meeting the broadest reasonable interpretation of ‘signal line’) and located beneath the shallow trench isolation structure and on the first backside metal level (fig. 2E-3: 152 located beneath 132/138 and on 146); and
a backside skip-level through via (¶¶ 0088, 0096: 146B and/or 150) connecting the backside signal line to the backside gate contact extension of the gate structure (figs. 2E-1 & 2E-2: 146B/150 connects 152 to 142/146B).
Regarding claim 2, Liaw teaches the semiconductor structure of Claim 1, wherein the backside skip-level through via passes through the first backside metal level (fig. 2E-2: at least potion 146B passes through M1) and a portion of the backside skip-level through via is located between the pair of spaced apart backside power rails that are present in the first backside metal level (fig. 2E-2: at least portion 146B located between 146A/Vss and 146A/Vdd).
Regarding claim 3, Liaw teaches the semiconductor structure of Claim 2, further comprising:
a dielectric spacer (¶¶ 0082, 0093: 144 and/or 148) located on a sidewall of the backside skip-level through via (figs. 2E-1 & 2E-2: 144 located on sidewall of 146B, and 148 located on sidewall of 150), wherein the dielectric spacer isolates the backside skip-level through via from the pair of spaced apart backside power rails present in the first backside metal level (figs. 2E-1 & 2E-2: 144/148 isolates 146B/150 from 146A/Vss and 146Vdd).
Regarding claim 15, Liaw teaches the semiconductor structure of Claim 1, wherein the pair of spaced apart backside power rails are present on the shallow trench isolation structure that is located beneath the gate structure (fig. 2E-2: 146A/Vss and 146A/Vdd preset on 132/138 beneath 128N/128P).
Regarding claim 16, Liaw teaches the semiconductor structure of Claim 1, wherein the pair of spaced apart backside power rails are present in a backside interlayer dielectric material layer (¶ 0088 & fig. 2E-2: 146A/Vss and 146A/Vdd preset in dielectric layer 144), and the backside signal line is present in another backside interlayer dielectric material layer (¶ 0095 & fig. 2E-1: at least portion 150 present in interlayer dielectric material layer 148).
Regarding claim 17, Liaw teaches the semiconductor structure of Claim 1, wherein the backside skip-level through via has a height that is taller than the height of the pair of spaced apart backside power rails that are present in the first backside metal level (fig. 2E-3: 146B/150 taller than 146A/Vss and 146A/Vdd).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 12-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (PG Pub. No. US 2022/0045050 A1) in view of Rubin et al. (PG Pub. No. US 2020/0135646 A1).
Regarding claim 1, Kim teaches a semiconductor structure (figs. 1 & 21A-21B among others) comprising:
a gate structure (¶ 0034: GE) having a backside gate contact extension (¶ 0054: uppermost portion of GC);
a shallow trench isolation structure (¶ 0050: ILD2) located entirely beneath the gate structure (fig. 21A: entirety of ILD2 located under GE);
a frontside interlayer layer (¶ 0040: GS and/or ILD1) located entirely above the shallow trench isolation structure and surrounding the gate structure (fig. 21A: GS/ILD1 located entirely above ILD2 and surrounds GE), wherein the backside gate contact extension is located entirely beneath the frontside interlayer dielectric layer and present in a lower portion of the shallow trench isolation structure (fig. 21B: uppermost portion of GC located entirely beneath GS/ILD1 and present in a portion of ILD2)
a first backside metal level comprising a pair of spaced apart backside power rails (¶ 0023 & fig. 2D: metal layer M1 comprises spaced-apart power rails POR1, POR2) and located beneath the backside gate contact extension of the gate structure and beneath the shallow trench isolation structure (figs. 21A-21B: M1 disposed beneath uppermost portion of GC and beneath ILD2 in the D3 direction);
a second backside metal level (¶ 0060: M2) comprising a backside line (fig. 2D: line IL2 comprised by M2) and located beneath the shallow trench isolation structure and on the first backside metal level (fig. 2D: M2 located beneath ILD2 and on M1); and
a backside skip-level through via (¶¶ 0057-0060: VI2 and/or IL1 and/or VI1) connecting the backside line to the backside gate contact extension of the gate structure (fig. 2D: VI2/IL1/VI1 electrically connects IL2 to uppermost portion of GC).
Kim is silent to the backside line comprising a signal line.
Rubin teaches a semiconductor structure (fig. 1 among others) including backside metal levels (BEOL, similar to M1 and/or M2 of Kim) configured to provide a signal to a gate contact structure (¶ 0050: backside metallization configured to provide gate control signals to gate terminals).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the backside line of Kim as a signal line, as a means to provide control of the gate structure, enabling functionality of the device.
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Regarding claim 2, Kim in view of Rubin teaches the semiconductor structure of Claim 1, wherein the backside skip-level through via passes through the first backside metal level and a portion of the backside skip-level through via is located between the pair of spaced apart backside power rails that are present in the first backside metal level (Kim, fig. 2D: at least a portion of VI2/IL2/VI1 located between POR1 and POR2).
Regarding claim 3, Kim in view of Rubin teaches the semiconductor structure of Claim 2, further comprising:
a dielectric spacer (Kim, ¶ 0057: ILD3) located on a sidewall of the backside skip-level through via, wherein the dielectric spacer isolates the backside skip-level through via from the pair of spaced apart backside power rails present in the first backside metal level (Kim, fig. 2D: ILD3 located on a sidewall of via portion IL1/VI1, and electrically isolates VI2/IL1/VI1 from POR1 and POR2).
Regarding claim 4, Kim in view of Rubin teaches the semiconductor structure of Claim 1, wherein the gate structure is a common gate structure that is present in an n-type field effect transistor (nFET) device region and in a p-type field effect transistor (pFET) device region (Kim, fig. 2D: GE is a common electrode extending into regions NR and PR), wherein the gate structure in the nFET device region is a component of a first nFET (Kim, ¶ 0024: GE in region NR is a component of an NMOSFET), and the gate structure in the pFET device region is component of a first pFET (Kim, ¶ 0024: GE in region PR is a component of an PMOSFET).
Regarding claim 5, Kim in view of Rubin teaches the semiconductor structure of Claim 4, wherein a first backside power rail of the pair of spaced apart backside power rails is present in the nFET device region (Kim, ¶ 0024 & fig. 2D: POR1 present in NMOSFET region NR) and is electrically connected to a first nFET device source/drain region of the first nFET (Kim, ¶ 0023: POR1 electrically connected to nFET source/drain region LEP2), and a second backside power rail of the pair of spaced apart backside power rails is present in the pFET device region (Kim, ¶ 0024: POR1 present in PMOSFET region PR) and is electrically connected to a first pFET device source/drain region of the first pFET (Kim, ¶ 0023: POR2 electrically connected to pFET source/drain region LEP1).
Regarding claim 6, Kim in view of Rubin teaches the semiconductor structure of Claim 5, wherein the first backside power rail is electrically connected to the first nFET device source/drain region of the first nFET (Kim, ¶ 0028: epitaxial pattern LEP2 in NMOSFET region NR) by a first via-to-backside power rail (VBPR) contact structure (Kim, ¶ 0052 & fig. 2D: POR1 electrically connected to LEP2 via first active contact AC2), and the second backside power rail is electrically connected to the first pFET device source/drain region of the first pFET (Kim, ¶ 0028: epitaxial pattern LEP1 in PMOSFET region PR) by a second VBPR contact structure (Kim, ¶ 0052 & fig. 2D: POR2 electrically connected to LEP1 via second active contact AC2).
Regarding claim 12, Kim in view of Rubin teaches the semiconductor structure of Claim 5, further comprising:
a second nFET present in the nFET device region (Kim, figs. 1, 2B: region NR includes a plurality of gate electrodes GE and active patterns AP2), and a second pFET present in the pFET device region (Kim, figs. 1, 2A: region PR includes a plurality of gate electrode portions GE and active patterns AP1).
Regarding claim 13, Kim in view of Rubin teaches the semiconductor structure of Claim 12, wherein the second nFET is spaced apart from the first nFET by a first dielectric material pillar (Kim, fig. 2B: at least active patterns AP2 spaced apart by pillar portions of dielectric ILD1), and the second pFET is spaced apart from the second nFET by a second dielectric material pillar (Kim, fig. 2A: at least active patterns AP1 spaced apart by pillar portions of dielectric ILD1).
Regarding claim 14, Kim in view of Rubin teaches the semiconductor structure of Claim 1, wherein the gate structure and the backside gate contact extension are of unitary construction (Kim, ¶¶ 0035, 0056, 0099: in at least one embodiment, GE and GC are integrally connected and comprise the same material, and therefore meet the broadest reasonable interpretation of ‘unitary construction’) and are both composed of a gate dielectric material (Kim, ¶ 0036: GI) and a gate electrode (Kim, ¶ 0036: GE).
Examiner’s note: if the term ‘unitary construction’ is intended to mean the gate structure and the backside gate contact extension are formed in a single process, the Examiner asserts that process limitations do not carry weight in a claim drawn to structure. Since GC and GE comprise a continuous structure of a common material, the limitation of ‘unitary construction’ is met.
Regarding claim 15, Kim in view of Rubin teaches the semiconductor structure of Claim 1, wherein the pair of spaced apart backside power rails are present on the shallow trench isolation structure (Kim, ILD2) that is located beneath the gate structure (Kim, fig. 2D: POR1 and POR2 at least indirectly disposed on ILD2, which is located beneath GE).
Regarding claim 16, Kim in view of Rubin teaches the semiconductor structure of Claim 1, wherein the pair of spaced apart backside power rails are present in a backside interlayer dielectric material layer (Kim, ¶ 0057 & fig. 2D: POR1 and POR1 present in ILD3), and the backside signal line is present in another backside interlayer dielectric material layer (Kim, ¶ 0060 & figs. 2C-2D: IL2 present in ILD4).
Regarding claim 17, Kim in view of Rubin teaches the semiconductor structure of Claim 1, wherein the backside skip-level through via has a height that is taller than the height of the pair of spaced apart backside power rails that are present in the first backside metal level (Kim, fig. 2D: VI2/IL1/VI1 taller than POR1/POR2).
Regarding claim 19, Kim in view of Rubin teaches the semiconductor structure of Claim 1, further comprising:
a dielectric spacer (Kim, ¶ 0038: SW4) present along an entirety of a sidewall of the gate structure (Kim, fig. 2D: SW4 present along an entirety of GE) and partially along a sidewall of the backside gate contact extension (Kim, fig. 2D: SW4 at least indirectly disposed along a portion of GC).
Regarding claim 20, Kim in view of Rubin teaches the semiconductor structure of Claim 1, wherein the backside gate contact extension is present in an area that is located between an nFET device region and a pFET device region (Kim, fig. 2D: GC located in region between NR and PR), and
the gate structure is present in both the nFET device region and the pFET device region (Kim, fig. 2D: GE extends into both nFER region NR and pFET region PR).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Rubin as applied to claim 6 above, and further in view of Liu (PG Pub. No. US 2021/0358901 A1).
Regarding claim 7, Kim in view of Rubin teaches the semiconductor structure of Claim 6, comprising a first backside power rail.
Kim in view of Rubin does not teach the semiconductor structure further comprising:
a first backside metal via structure electrically connecting the first backside power rail to an electrically conductive structure that is present in the second backside metal level.
Liu teaches a semiconductor structure (fig. 4) including a first backside metal via structure (¶ 0028: BV0) electrically connecting a first backside power rail (¶ 0031: 440, similar to POR1/POR2 of Kim) to an electrically conductive structure that is present in a second backside metal level (fig. 4: BV0 electrically connects 440 to 430 an overlying metal level BM1, similar to M2 of Kim).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Kim in view of Rubin with a backside metal via structure, as a means to provide power from a supply voltage source to the backside power rail (Liu, ¶ 0026).
Regarding claim 8, Kim in view of Rubin and Liu teaches the semiconductor structure of Claim 5, further comprising:
a frontside back-end-of-the-line (BEOL) structure (Liu, ¶ 0025: M0) located above the gate structure (Liu, fig. 4: M0 locate above gate regions G).
Regarding claim 9, Kim in view of Rubin and Liu teaches the semiconductor structure of Claim 8, further comprising:
a carrier wafer (Kim, ¶ 0022: SUB, comprising active device regions NR and PR) located on the frontside BEOL structure (Liu, fig. 4: active device region AL, corresponding to SUB of Kim, located at least indirectly on M0).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Rubin and Liu as applied to claim 8 above, and further in view of Chang et al. (PG Pub. No. US 2021/0375761 A1).
Regarding claim 10, Kim in view of Rubin and Liu teaches the semiconductor structure of Claim 8, comprising a BEOL structure (Liu, M0), a second nFET device source/drain region of the first nFET (Kim, ¶ 0032 & fig. 2D: UEP2), and a second pFET device source/drain region of the first pFET (Kim, ¶ 0031 & fig. 2D: UEP1).
Kim in view of Rubin and Liu does not teach wherein the frontside BEOL structure is electrically connected to a second nFET device source/drain region of the first nFET by a first frontside source/drain contact structure and a first frontside metal via structure, and to a second pFET device source/drain region of the first pFET by a second frontside source/drain contact structure and a second frontside metal via structure.
Chang teaches a semiconductor structure (¶ 0026: 200) including a frontside BEOL structure (¶ 0122: 120) electrically connected to a second nFET device source/drain region of a first nFET (¶¶ 0014, 0035 & fig. 31C: 92, disposed in an NMOS regio 50N) by a first frontside source/drain contact structure and a first frontside metal via structure (¶¶ 0072-0073, 0100 & fig. 31C: 92 connected to 120 by at least one via and at least one metal feature), and to a second pFET device source/drain region of the first pFET (¶¶ 0014, 0035 & fig. 31C: 92, disposed in an PMOS region 50P) by a second frontside source/drain contact structure and a second frontside metal via structure (¶¶ 0072-0073, 0100 & fig. 31C: 92 connected to 120 by at least one via and at least one metal feature).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor structure of Kim in view of Rubin with frontside contact and metal via structures, as a means to improve routing performance by decreasing routing density (Chang, ¶ 0011).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Rubin as applied to claim 5 above, and further in view of Chung et al. (PG Pub. No. US 2021/0376130 A1).
Regarding claim 11, Kim in view of Rubin teaches the semiconductor structure of Claim 5, wherein the gate structure in the nFET device region wraps around a channel region present in the nFET device region (¶¶ 0034, 0039 & fig. 2D: GE in NR region wraps around four sidewalls of channel CHP2), and the gate structure in the pFET device region wraps around a channel region present in the pFET device region (¶¶ 0034, 0039 & fig. 2D: GE in PR region wraps around four sidewalls of channel CHP1).
Kim in view of Rubin does not teach the channel regions comprises a plurality of vertically stacked semiconductor channel material nanosheets.
Chung teaches a semiconductor structure (¶ 0026: 200) including a gate structure (¶ 0028: 240) wrapping around a plurality of vertically stacked semiconductor channel material nanosheets (¶ 0029 & fig. 3D among others: 240 wraps around a plurality of vertically stacked semiconductor channel material nanosheets 215).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the channel regions of Kim in view of Rubin with a plurality of vertically stacked nanosheets, as a means to provide better gate control ability, lower leakage current (Chung, ¶ 0024) and higher output current.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, configuring the gate-wrapped channel structure of Kim with a plurality of stacked nanosheets would involve a mere duplication of essential working parts.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 and 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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