Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/03/2025. Examiner acknowledges that claims 14-16 are not a method of making, and thus examines the group I invention, claims 1-9 and 14-16, below on the merits. Claims 10-13 are still withdrawn as being a method of making.
Response to Arguments
In response to the applicants arguments, filed on 01/14/2026, regarding the reference Baek et al on pages 9, 10 and 11, it is acknowledged that the applicant understands the “groove” and “notch” of their present disclosure to contain no other material filling in the groove or notch. However, according to the broadest reasonable interpretation, a groove and a notch need not be empty of material but can be filled in, thus the examiner finds the applicants arguments non-persuasive. Additionally, in light of the amendments the examiner uses different base reference to reject independent claim 1. It is recommended that the applicant add in language around the nature of the groove and notch being not-filled with material.
With regards to the arguments pertaining to Jang et al on pages 11-13, it must be noted that the claims are seeking to patent a product and not a method of using. If the applicant wishes to submit claims under the category of “method of using” applicant may do so, but at the present moment claim 14 is with regards to a structure. Even though Jang may disclose three independent regions, said regions form one structural mask. As mentioned before, the three regions may be used for three different purposes but that does not negate their structural basis as both a semi-permeable and permeable region on which the varying layers [including the gate electrode/capacitor electrode combination] are created by using those layers. Additionally, according to paragraph 0184 of Jang et al, it states that the pattern mask 610 includes a transmitting portion 611 and semi-transmitting portion 612. Thus, Jang et al does disclose one single mask layer, which may be used in three independent steps, but nonetheless one single layer with three different portions to it that form the differing grooves and notches of the device. Thus, the examiner finds the applicants arguments unpersuasive.
With regards to the applicants arguments pertaining to the Sun reference on page 16, Sun does not need to explicitly mention a notch to describe or show one in the disclosure, additionally a notch and a groove can be filled in with other material and still be a notch or a groove of the specific layers where such exists. Thus, the examiner finds the applicants arguments not persuasive.
With regards to the arguments pertaining to the Tang reference, as with the Sun reference, a notch or a groove does not need to be explicitly stated if a notch or a groove is shown or described within certain layers. Additionally, the slopes are shown visually in the disclosure to be different and thus it would be obvious for one of ordinary skill in the art to see such differences and utilize them in their own invention. The examiner finds the applicants arguments not persuasive.
Regarding the applicants arguments pertaining to Asai et al, Yamada and Kim, on pages 17-19, similar to the Sun and Tang references, the notches and grooves need not be explicitly stated as such but if described and/or visually shown in the disclosure, it is disclosed and could be used by one of ordinary skill in the art to combine such a feature. The examiner finds the applicants arguments not persuasive.
Additionally, with reference to the Jang, Baek, Sun, Tang, Asai, Ymada and Kim references, simply because they describe a different use of a similar structure does not negate them from reading onto the claims of the applicant’s disclosure. All of the references are in the same field of endeavor and can be read onto the applicants claims. The specific usage of a device is not in question but rather the structure of the product, of which the references are similar enough to read onto the claims.
It is recommended that the applicant modify the language regarding the groove and notch to incorporate some necessity that the grooves and notches do not have any material filling them in but rather are empty, or open to the air [or some variation of the sort].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al (US 20200292890)
Ishikawa et al teaches
[claim 1] An array substrate (paragraph 0012),
comprising: a substrate; and a metal film disposed on the substrate, wherein the metal film is provided with a first notch, the first notch comprises a first groove located in a middle of the first notch and a second groove located at an edge of the first groove and communicated with the first groove (figure 7, paragraphs 0054-0055, where element 35 is the metal layer disposed on the substrate [element 10], and is provided with a first notch [comprised of the first and second groove as shown in figure 1 below], where the first groove is in the center and the second groove is on the edge of the first groove and communicated with the first groove [as shown in figure 1 below]),
a bottom surface of the first groove is closer to the substrate compared to a bottom surface of the second groove, and a projection of the first groove on a plane parallel to the substrate is located within that of the second groove on the plane parallel to the substrate (figure 7, paragraphs 0054-0055, figure 1 below, where the bottom surface of the first groove is close to the substrate [element 10] than the bottom of the second groove, and the projection onto the substrate of the notch has the first groove within the second groove),
a depth of the first groove is greater than that of the second groove (figure 7, paragraphs 0054-0055, where the first groove has a greater depth than the second groove [as shown in figure 1 below]).
However, Ishikawa et al does not specifically disclose
[claim 1] and a sidewall slope of the first groove is less than that of the second groove.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Ishikawa et al to modify the slopes of the two grooves to be different than one another. In particular, according to figure 7 [as shown in figure 1 below] the sidewall slopes of the first and second groove are the same slope. There are thus only two possibilities to try, either the first groove slope is greater than, or the second being, the first groove slope is less than the second groove slope. It would be obvious to try these differing changes for particular use case to make the device optimal for a specific use case.
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Figure 1: From Figure 7 of Ishikawa et al.
Claim(s) 2, 3, 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al (US 20200292890 A1) in view of Baek et al (US 20040041149 A1) and in further view of Sun et al (CN 104538408 A).
Regarding claims 2 and 3:
Ishikawa et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 2] The array substrate according to claim 1, wherein1 the array substrate has a display region and a non-display region surrounding the display region, the metal film is also provided with a second notch, the second notch is disposed in the display region, the metal film is divided by the second notch to obtain a gate electrode, the firstnotch is disposed in the non-display region, and the metal film is divided by the first notch to obtain a wire, and a sidewall slope of the second notch is greater than that of the second groove.
[claim 3] The array substrate according to claim 2, wherein sidewalls of the first notch corresponding to the second groove and the first groove are a stepped form.
However, Baek et al teaches
[claim 2] the metal film is also provided with a second notch (figure 4, where the second notch resides between element 123 and 127).
and the metal film is divided by the first notch to obtain a wire (figure 4, paragraph 0092, where element 127 is an extension of the gate lines 121, thus acting as a wire caused by the division of first notch).
[claim 3] The array substrate according to claim 2, wherein sidewalls of the first notch corresponding to the second groove and the first groove are a stepped form (figure 1 above as a snippet of figure 4, where the sidewalls of the first notch [elements 123q as well as 125q] create the second groove [which is situated in the area above 123p not overlapped by 123q as well as the area above 125p not overlapped by 125q], where each is a step form, as there is a step from the bottom of the first groove to the bottom of the second groove).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Ishikawa et al to incorporate the teachings of Baek et al in order to provide a second notch such that more than one transistor can be disposed to control the LED thus creating better control for the display pixel [by including multiple types of transistors to control said pixel].
However, Ishikawa et al as modified does not specifically disclose
[claim 2] The array substrate according to claim 1, wherein the array substrate has a display region and a non-display region surrounding the display region, the second notch is disposed in the display region, the metal film is divided by the second notch to obtain a gate electrode, the first notch is disposed in the non-display region, and a sidewall slope of the second notch is greater than that of the second groove.
However, Sun et al does teach
[claim 2] The array substrate according to claim 1, wherein the array substrate has a display region and a non-display region surrounding the display region (figure 2-1, paragraphs 0093-0095 where the non-display area is represented by the area left of the vertical line and contains element 103 and surrounds the display region which is the region right of the vertical line and contains element 102),
the second notch is disposed in the display region, the metal film is divided by the second notch to obtain a gate electrode, the first notch is disposed in the non-display region (figure 2-1, paragraphs 0093-0095, where Baek et al contains the first and second notch and is substituted for elements 102 and 103, where the first notch [as shown in figure 1 above and figure 4 of Baek et al] is situated between elements 125 and 123, all of which is in place of element 103 in Sun et al, thus being in the non-display area. Element 102 is replaced by element 127 of Baek et al in figure 4, and thus the second notch is in the display area).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Ishikawa et al as modified to incorporate the teachings of Sun et al in order to minimize material and make a more efficient process by keeping portions of the circuit in the non-display area and other portions in the display area.
Regarding claims 5 and 18:
Ishikawa et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 5] The array substrate according to claim 1, wherein the array substrate has a display region and a non-display region surrounding the display region, there is a plurality of first notches, the display region and the non-display region are each provided with a plurality of the first notches, the metal form is divided by the first notches in the display region to obtain gate electrodes for driving thin film transistor, and the metal form is divided by the first notches in the non-display region to obtain wires.
[claim 18] The array substrate according to claim 5, wherein the display region is further provided with a second notch, and the metal film is divided by the second notch in the display region to obtain a gate electrode for switching thin film transistor.
However, Baek et al teaches
[claim 18] The array substrate according to claim 5, wherein the display region is further provided with a second notch, and the metal film is divided by the second notch in the display region to obtain a gate electrode for thin film transistor (figure 4, paragraphs 0083-0084, where element 123 [as shown in figure 2 below] has two notches, the first and the second notch divided by a metal film which is a gate electrode).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Ishikawa et al to incorporate the teachings of Baek et al in order to provide a second notch such that more than one transistor can be disposed to control the LED thus creating better control for the display pixel [by including multiple types of transistors to control said pixel].
However, Ishikawa et al as modified does not specifically disclose
[claim 5] The array substrate according to claim 1, wherein the array substrate has a display region and a non-display region surrounding the display region, there is a plurality of first notches, the display region and the non-display region are each provided with a plurality of the first notches, the metal form is divided by the first notches in the display region to obtain gate electrodes for driving thin film transistor, and the metal form is divided by the first notches in the non-display region to obtain wires.
[claim 18] switching [thin film transistor].
However, Sun et al does teach
[claim 5] The array substrate according to claim 1, wherein the array substrate has a display region and a non-display region surrounding the display region (figure 2-1, paragraphs 0093-0095 where the non-display area is represented by the area left of the vertical line and contains element 103 and surrounds the display region which is the region right of the vertical line and contains element 102),
there is a plurality of first notches, the display region and the non-display region are each provided with a plurality of the first notches (where Baek et al and Sun et al detail an array of pixels, thus what is shown in just one pixel, but due to paragraph 0009 of Sun et al the single pixel is repeated in an array thus containing a plurality of the single notch).
the metal form is divided by the first notches in the display region to obtain gate electrodes for driving thin film transistor, and the metal form is divided by the first notches in the non-display region to obtain wires (figure 2-1 of Sun et al and paragraph 0093-0095 where element 125 of Baek et al replaces element 103 of Sun et al and element 123 of Baek et al replaces element 102 of Sun et al. Thus the first notches span the display and non-display region of Sun et al [left of the vertical line in figure 2-1 is the non-display region, right of the vertical line of figure 2-1 is the display region], and element 123 of Baek et al is a gate electrode and element 125 of Baek et al is a wire extension of the gate line, thus the gate electrode is situated in the display region and the wire is situated in the non-display region [paragraphs 0083 and 0097 of Baek et al]).
[claim 18] switching [thin film transistor] (paragraph 003, where the device shown [single device] can be used a switch type transistor).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Ishikawa et al as modified to incorporate the teachings of Sun et al in order to minimize material and make a more efficient process by keeping portions of the circuit in the non-display area and other portions in the display area.
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Figure 2 from Fig. 4 of Baek et al (US 20040041149 A1).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al (US 20200292890), Baek et al (US 20040041149 A1) and Sun et al (CN 104538408 A) in further view of Tang et al (CN 110444567).
Ishikawa et al as modified teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 4] the array substrate according to claim 2, wherein a sidewall slope of the second notch is greater than that of the first notch.
However, Tang et al does teach
[claim 4] the array substrate according to claim 2, wherein a sidewall slope of the second notch is greater than that of the first notch (figure 6, where element 403 is the second notch and element 404 is the first notch, where the second notch has a steeper slow than the first notch [as seen visually]).
It would have been obvious to one of ordinary sill in the art at the time of filing to have modified the teachings of Ishikawa et al as modified to incorporate the teachings of Tang et al in order to provide a more efficient device by creating a less steep side wall so as to minimize charge build-up and allow for better charge flow and thus better control of the transistor.
Claim(s) 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al (US 20200292890), Baek et al (US 20040041149 A1) and Sun et al (CN 104538408 A) in further view of Asai et al (US 20200249510 A1).
Ishikawa et al as modified teaches all of the limitations of the parent claims, claims 2 and 5, but does not specifically disclose
[claim 7] the array substrate according to claim 2, wherein the wire is a scan wire or a data wire.
[claim 8] the array substrate according to claim 5, wherein the wire is a scan wire or a data wire.
However, Asai et al does teach
[claim 7] the array substrate according to claim 2, wherein the wire is a scan wire or a data wire (paragraph 0089, where the metal film [MF2, element 63] is a data line).
[claim 8] the array substrate according to claim 5, wherein the wire is a scan wire or a data wire (paragraph 0089, where the metal film [MF2, element 63] is a data line).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaching of Ishikawa et al as modified to incorporate the teaching of Asai et al to incorporate a data line as one part of the metal film in order to minimize material used and making a more efficient device by combining gate line and data line into a single line.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al (US 20200292890) in view of Yamada et al (US 20150044789 A1).
Ishikawa et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 9] the array substrate according to claim 1, wherein the metal film is in a form of a capacitor layer, a source electrode layer, or a drain layer.
However, Yamada et al does teach
[claim 9] the array substrate according to claim 1, wherein the metal film is in a form of a capacitor layer, a source electrode layer, or a drain layer (figure 7, paragraph 0075, where element 24b and 24c make up the metal film and a notch [see by label CH] is the notch in the metal film, where the metal film comprises both a drain and source electrode [24b is the source electrode, 24c is the drain electrode]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Ishikawa et al to incorporate the teachings of Yamada et al in order to use the metal film as a source and drain electrode to create a more efficient transistor instead of depositing layer upon layer to form said electrodes.
Claim(s) 14 are rejected under 35 U.S.C. 103 as being unpatentable by Jang et al (DE 102019135043 where US 20210193699 serves as the translation).
Jang et al teaches
[claim 14] A mask, comprising: a plate body; wherein the plate body is provided with a first opening, the first opening is provided with a semi-permeable membrane, the semi-permeable membrane is provided with a light-transmitting hole, and the mask is configured to etch a metal film on an array substrate to form a first groove facing the light-transmitting hole and a second groove facing the semi-permeable membrane (figure 9A, paragraphs 0184-0185, where element 610 is the mask comprising a plate body and has a first opening [section left of element 613] where there is a semi-permeable portion [element 612] and fully permeable portion [element 611], and a first groove is formed from the fully transparent portion [element 611] and a second groove is formed from a semi-permeable portion [element 612], as seen in figure 9C where element A1 has a step wise formation with element G1 and 121).
Wherein the semi-permeable membrane is configured to form a weak exposure area in the photoresist, and the light-transmitting hole is configured to form a first strong exposure area in the photoresist (figure 9A, paragraphs 0184-0185, where by nature of the membrane being semi-permeable and the hole being fully permeable the membrame is configured to form a weaker exposure in the photo-resist than the hole where light fully goes through, verses the semi-permeable membrane where only a portion of the light hits the photo resist),
And wherein a depth of the first groove is greater than that of the second groove (figure 9C, paragraphs 0184-0185, where element 121 and CE2 forms the first groove [left-hand side of these elements forms the first groove], and where the space between element A1 and the edge of element 121 forms the second groove, and the first groove is deeper than the second groove).
However, Jang et al does not specifically disclose
[claim 14] and a sidewall slope of the first groove is less than that of the second groove.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Jang et al to modify the slopes of the two grooves to be different than one another. In particular, according to figure 9C, the sidewall slopes of the first and second groove are the same slope. There are thus only two possibilities to try, either the first groove slope is greater than, or the second being, the first groove slope is less than the second groove slope. It would be obvious to try these differing changes for particular use case to make the device optimal for a specific use case.
Claim(s) 15, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable by Jang et al (DE 102019135043 where US 20210193699 serves as the translation) in view of Kim et al (US 20150187817).
Jang et al as modified teaches all of the limitations of the parent claim, claim 14, and additionally teaches
[claim 15] the second opening is configured to form a gate electrode in the metal film, and the first opening is configured to form a wire in the metal film (figure 9A and 9C, paragraphs 00184-00185, where the second opening [element 612 and 611 on the right hand side of element 613] forms a gate electrode [element G1 attached to element CE2 – that is they’re the same layer both formed from the second opening] and the first opening forms a data line as seen on the far left side of figure 9C where element DL is the data line formed),
And the second opening is configured to form a second strong exposure area in the photoresist (figures 9A and 9C, paragraphs 0184-0185, where element 511 on the right hand side of element 613 is the second opening and is not permeable thus is configured, intrinsically, to be a strong exposure area [akin to element 611 on the left-hand side of element 613 is the strong exposure when compared the to semi-permeable weak exposure area]).
[claim 19] The mask according to claim 16, wherein the mask further comprises a second opening, the second opening is a through hole which is disposed to face a part of the metal film in the display region (figures 9A, 9C and 9G, where element G1 is the gate electrode [formed of the same metal as CE2] which is formed by the second opening [element 611 on the right hand side of element 613], which is a through hole [no film] disposed to face a part of the metal film in the display region),
and the second opening is configured to form a second strong exposure area in the photoresist and to form a gate electrode for switching thin film transistor in the metal film (figures 9A, 9C and 9G where element 611 on the right-hand side, akin to element 611 on the left-hand side which is determined as a strong exposure unit, is also a strong exposure area to form the gate electrode).
However, Jang et al does not specifically disclose
[claim 15] The mask according to claim 14, wherein the mask further comprises a second opening, the second opening is configured to provide a part of the metal film facing a display region of the array substrate, the first opening is configured to provide a part of the metal film facing a non-display region of the array substrate.
[claim 16] The mask according to claim 14, wherein there is a plurality of first openings, and the display region and the non-display region of the array substrate are each provided with a plurality of the first openings correspondingly, the first openings in the display region are configured to form gate electrodes for driving thin film transistor in the metal film, and the first openings in the non-display region are configured to form wires in the metal film.
However, Kim et al does teach
[claim 15] The mask according to claim 14, wherein the mask further comprises a second opening, the second opening is configured to provide a part of the metal film facing a display region of the array substrate, the first opening is configured to provide a part of the metal film facing a non-display region of the array substrate (figure 3E, paragraph 0060, where the non-display region is shown below the mast [element M3] and the substrate [element 110] as NA, and the display region is shown as element OA. The first opening of Jang et al is in place of the non-display area in Kim et al, and thus the second opening of Jang et al is in the display area of Kim et al. In the display area a gate electrode is formed [element 111] by the second opening).
[claim 16] The mask according to claim 14, wherein there is a plurality of first openings, and the display region and the non-display region of the array substrate are each provided with a plurality of the first openings correspondingly, the first openings in the display region are configured to form gate electrodes for driving thin film transistor in the metal film, and the first openings in the non-display region are configured to form wires in the metal film ((figure 3E, paragraph 0060, where the non-display region is shown below the mast [element M3] and the substrate [element 110] as NA, and the display region is shown as element OA. The first opening of Jang et al cover the entire mask of Kim et al, thus the first opening of Jang et al has multiple openings as delineated by the permeability, the first element left of element 613, element 612 and also element 611 adjacent to the left of the semi-permeable element 612 make up the first part of the first opening, the second part is made up of the rest of the first opening [area of the mast of figure 9A of Jant et al left of element 613]. Thus when placed onto Kim et al’s mask, the entire first opening cover both the display and non-display area. In Jang et al the mask creates a gate electrode and data line [element G1 and DL] which could aligh with the display area and non-display area of Kim et al, respectively).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Jang et al to incorporate the teachings of Kim et al in order to streamline the process of etching gate and data lines by providing a single mask to etch both in one step instead of etching them in multiple steps with multiple masks.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al (US 20200292890 A1) in view of Baek et al (US 20040041149 A1).
Ishikawa et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 17] The array substrate according to claim 1, wherein the metal film is a gate electrode layer.
However, Baek et al does teach
[claim 17] The array substrate according to claim 1, wherein the metal film is a gate electrode layer (paragraph 0083, figure 2 above, where the first notch and second notch are all within the metal film where the metal film incorporates element 123, thus the metal film is a gate electrode layer [as shown by the second groove of the first notch being in direct contact with the gate electrode 123]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaching of Ishikawa et al to incorporate the teaching of Baek et al in order to create a functioning transistor in a display area such that a metal gate electrode is required.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818