DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant argues regarding claim1 on “Applicant’s Arguments/Remarks Made in an Amendment” “REMARKS” section dated 10/30/2025 that " It is respectfully submitted that Arnold fails to disclose every feature of claim 1. For example, Arnold is silent with respect to at least the following features of claim 1: "a monolithically integrated level shifting stage configured to receive an input signal corresponding to a signal across the resistive load and output a level shifted signal that corresponds to the input signal”. Instead, Arnold's auxiliary gate relies on inherent two-dimensional electron gas (2DEG) resistance for voltage drop during gate biasing (e.g., '"[p] art of this potential is used to form the auxiliary 2DEG under the auxiliary gate 15 and only part is transferred to the second additional terminal 12 which is connected to the active gate 10" ([0282]); [0070]-[ 0071]; FIG. 2), with optional parallel diodes or resistors for pull-down during turn-off ([0084]; FIG. 4A). These are gate-control elements, not a dedicated level shifter processing a current sensing signal (VCS) from a resistive load across scaled transistor sources to shift it (e.g., >1V; claim 29) for amplifier input. Arnold's "decoupling structures" or "voltage dividers" (e.g., [0097]-[0102], [0107]; FIGS. 45, 50) are for EMI shielding or gate clamping, not monolithic VCS shifting tied to a sensing resistor for low- voltage compatibility with enhancement-mode amplifiers (e.g., compare Arnold's description with the Specification at paragraphs [0035], [0176]-[0179]; FIG. 8). Moreover, the Office Action's mapping to a "monolithically integrated ... level shifting stage" via "shielded structures . . . capacitors, resistors, HEMTs" ([0102]; Office Action 17) is erroneous, as Arnold's shields are passive isolation layers ([0160]-[0166]; FIG. 45), not active shifters receiving/processing a resistive-load signal.
However, the examiner disagrees. As in claim 1, Resistive loads connected between the gate and source of GaN HEMTs or Power MOSFETs in general are also known and their aim can vary from reducing the oscillations during high voltage switching, protecting the device against electro-static discharge and in general ensuring a robust operation. For example in the data sheet of the GaN Systems parts [21] a 3 kΩ resistor is recommended to be added between the gate terminal (gate bus) and the source (or ground) (Paragraph [0017]. … In an embodiment, the described p-GaN islands are arranged in such a way that the conductive path at a gate voltage between the first and second threshold levels follows a meander shape or labyrinth shape to increase the length of the path and therefore the resistance between the main terminals (source and drain) in a given area (Paragraph [0093]), … .The pull-down network through the second auxiliary heterojunction transistor may further comprise of a resistor added in series with the second auxiliary transistor between the gate and drain terminal of the second auxiliary transistor. The resistor is between the gate and drain terminals of the second auxiliary transistor. Therefore the resistor does not form a common junction between the first auxiliary transistor and the gate of the active transistor. The resistor acts to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the heterojunction power device. The additional resistive element performs this function by leading to an increased potential, during turn-off, of the second auxiliary transistor gate terminal compared to the second auxiliary transistor drain terminal. An additional resistor could be connected between the drain terminal of the second auxiliary transistor and the source terminal of the active power transistor. The additional resistor acts as a parallel pull-down network during the active device turn-off. Therefore, it will be understood that the additional resistor is not connected through a common junction connecting the source of the first auxiliary transistor and the gate of the active transistor. During the active device turn-on and on-state the additional resistor can act as a voltage limiting component to protect the gate terminal of the active device (Paragrpah [0105]-[0115]). Also, see FIG. 10-12. This clearly indicates that level shifting stage configured to receive an input signal corresponding to a signal across the resistive load and output a level shifted signal that corresponds to the input signal …
Applicant also argues regarding claim 1 that "an amplifier stage configured to receive the level shifted signal as an input and provide an output signal to an output node of the heterojunction device, wherein the output signal of the amplifier stage is proportional to the signal across the resistive load."”
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However, the examiner disagrees. See FIG, 12 where the gate (the gate of the enable or disable transistor may be driven by an external signal directly or through a signal conditioning circuit such as inverter, buffer, voltage follower, Schmidt trigger, amplifier, voltage divider, protection circuit or latching circuit as in Paragraph [0128]), .. level shifted signal as an input (to (46)) and provide an output signal to an output node of the heterojunction device, wherein the output signal of the amplifier stage is proportional to the signal across the resistive load (44 and 45)”.
Allowable Subject Matter
Claim 15 (their dependent claims 16-28) objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 10-14, 29 and 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by over Arnold et al. (US PGpub: 2021/0335781 A1), herein after Arnold.
Regarding claim 1, Arnold teaches, in FIG. 1, an Ill-nitride power semiconductor based heterojunction device comprising:
a first heterojunction transistor comprising a first drain terminal, a first source terminal and a first gate terminal; a second heterojunction transistor comprising a second drain terminal, a second source terminal and a second gate terminal, wherein the second drain terminal is operatively connected to the first drain terminal, the second gate terminal is operatively connected to the first gate terminal (GaN HEMT (Le., hetero-Junction) drain 12 and scaled replica 22 FETs, the gates and drains of ail FETs connected in parallel, the source of replica FET 22 connected to the source of main FET 12 via a sensing resistor 24 providing a sensing voltage Vsense, which is passed to level shifting, diode connected FET M36, whose output is passed to amplifier FET M37 to provide an amplified current sensing signal Vdetect (Claims 1, 7)),;
a resistive load comprising a first terminal operatively connected to the first source terminal and a second terminal operatively connected to the second source terminal (An output of FET M37 ls a source current that is converted to voltage by resistor R35 connected, to the main FET source (claims 2, 3));
a monolithically integrated level shifting stage configured to receive an input signal corresponding to a signal across the resistive load and output a level shifted signal that corresponds to the input signal (The entire circuit including main, replica FETs, and the sensing circuit 30 with FETs and resistors may be Monolithically integrated on the same substrate, Claims 5, 6, 30);
an amplifier stage configured to receive the level shifted signal as an input and provide an output signal to an output node of the heterojunction device, wherein the output signal of the amplifier stage is proportional to the signal across the resistive load (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13); and
wherein the second heterojunction transistor has a substantially identical structure to the first heterojunction transistor, and wherein the second heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a scale factor X, where X is larger than 1 (Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 2, Arnold teaches the heterojunction device of claim 1, wherein the output signal of the amplifier stage is a current signal, and wherein the heterojunction device is connected or connectable an output resistor, the output resistor is configured to convert the current signal to an output voltage with a magnitude proportional to a resistance of the output resistor (Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 3, Arnold teaches the heterojunction device of claim 2, wherein the output resistor is operatively connected between the output node and the first source terminal; and wherein the resistance of the output resistor is substantially constant with respect to temperature across a temperature range of about -55 degrees Celsius to about 150 degrees Celsius (Paragraph [0013], [0154]-[0156], [0229]).
Regarding claim 5, Arnold teaches the heterojunction device of claim 1, wherein the amplifier stage comprises one or more monolithically integrated operational amplifiers, voltage repeaters, resistors and/or capacitors; and wherein the output signal of the amplifier stage is proportional to a current or voltage across the resistive load (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13) and Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 6, Arnold teaches the heterojunction device of claim 5, wherein the amplifier structure comprises at least two resistive structures, wherein the at least two resistive structures are ratiometrically matched and formed in a same layer of the heterojunction device, such that a resistance of each of the two resistive structures have approximately the same variability with respect to temperature or process variations (The entire circuit including main, replica FETs, and the sensing circuit 30 with FETs and resistors may be Monolithically integrated on the same substrate, Claims 5, 6, 30. Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13) and Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 7, Arnold teaches the heterojunction device of claim 1, wherein the level shifting stage comprises at least one of: (i) one or more low voltage diodes operatively connected in series, and/or (ii) one or more gate-source connected enhancement mode transistors operatively connected in series (The entire circuit including main, replica FETs, and the sensing circuit 30 with FETs and resistors may be Monolithically integrated on the same substrate, Claims 5, 6, 30. Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13) and Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 10, Arnold teaches the heterojunction device of claim 1, further comprising an offset cancellation circuit configured to remove an offset signal from the output signal of the amplifier stage (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13).
Regarding claim 11, Arnold teaches the heterojunction device of claim 10, wherein the offset cancellation circuit is monolithically integrated in the amplifier stage of the heterojunction device (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track, Claims 10,11,13).
Regarding claim 12, Arnold teaches the heterojunction device of claim 10, wherein the offset cancellation circuit is configured to receive the output signal of the amplifier stage as an input and output a corrected output signal (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13) and Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 13, Arnold teaches the heterojunction device of claim 10, wherein the offset cancellation circuit comprises at least one of an enhancement mode transistor, a depletion mode transistor, a resistor and/or a capacitor (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13) and Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29, … Shielded structures may be capacitors, resistors, HEMTs or any other active and passive devices on the chip).
Regarding claim 14, Harari teaches the heterojunction device of claim 1, comprising a monolithically integrated stand-by circuit configured to detect when the device is operating under a no load condition, and, in response to the detection, to generate a stand-by signal to lower a power consumption of at least one of the level shifting stage or the amplifier stage (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their V(gs) voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13) and Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 29, Harari teaches the heterojunction device of claim 1, wherein the level shifted signal output by the level shifting stage corresponds to the input signal with a voltage shift of 1V or more (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their Vgs voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13. Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Regarding claim 30, Harari teaches the heterojunction device of claim 1, wherein the amplifier stage is monolithically integrated in the heterojunction device (Diode-connected FET M38 acts as an offset voltage connection of ensuing FET M37, since, at least to a first order, their Vgs voltages cancel out, particularly since they are monolithically integrated and track (Claims 10,11,13. Digital output signal OUTp , FIG. 1, indicates whether positive current is flowing in the FFT. In addition, OUTn (Fig. 5) indicates negative current (claim 14), In operation the level shifting FET M36 produces about 1.5V at its drain, i.e., it shifts the input voltage by as much, claim 29).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Arnold et al. (US PGpub: 2021/0335781 A1), herein after Arnold, in view of Udrea et al. (US Patent: 6362508 B1), herein after Udrea.
Regarding claim 4, Arnold does not explicitly teach the heterojunction device of claim 1, wherein the device comprises: a heterojunction comprising a two dimensional carrier gas; and one or more isolation regions configured to reduce an interference between two or more of the first heterojunction transistor, the level shifting stage and/or the amplifier stage, wherein the isolation regions do not comprise the two dimensional carrier gas .
However, it is commonly known and desirable to form isolated regions on substrates, including GaN, to reduce interference between devices, as exemplified in Udrea (Figs. 3, 4; para. [0064], [0131]. The skilled person incorporates into Udrea such measures in an obvious manner for their known effect (claim 4). Depletion mode devices are commonly used for level shifting due to their negative gate-source voltage in operation. Udrea (Fig. 3, Paragraph [0116] teaches depletion mode devices monolithically integrated on a GaN power FET substrate. The skilled person uses a depletion mode FET as a level shifter as a functional equivalent of, and an obvious alternative to the diode-connected FET M36 in Fig. 1 of Arnold, claims 8, 9).
Regarding claim 8, Arnold does not explicitly teach the heterojunction device of claim 1, wherein the level shifting stage comprises one or more low voltage depletion mode transistors; and wherein the level shifting stage is configured to amplify the input signal such that the level shifted signal corresponds to an amplified input signal.
However, it is commonly known and desirable to form isolated regions on substrates, including GaN, to reduce interference between devices, as exemplified in Udrea (Figs. 3, 4; para. [0064], [0131]. The skilled person incorporates into Udrea such measures in an obvious manner for their known effect (claim 4). Depletion mode devices are commonly used for level shifting due to their negative gate-source voltage in operation. Udrea (Fig. 3, Paragraph [0116] teaches depletion mode devices monolithically integrated on a GaN power FET substrate. The skilled person uses a depletion mode FET as a level shifter as a functional equivalent of, and an obvious alternative to the diode-connected FET M36 in Fig. 1 of Arnold, claims 8, 9).
Regarding claim 9, Arnold does not explicitly teach the heterojunction device of claim 8, wherein the one or more low voltage depletion mode transistors comprise a source terminal, a drain terminal, and a plurality of highly doped semiconductor regions spaced apart from each, the plurality of highly doped semiconductor regions positioned between the source terminal and the drain terminal; and wherein the plurality of highly doped semiconductor regions are configured to increase a length of a current path between the source terminal and the drain terminal.
However, it is commonly known and desirable to form isolated regions on substrates, including GaN, to reduce interference between devices, as exemplified in Udrea (Figs. 3, 4; para. [0064], [0131]. The skilled person incorporates into Udrea such measures in an obvious manner for their known effect (claim 4). Depletion mode devices are commonly used for level shifting due to their negative gate-source voltage in operation. Udrea (Fig. 3, Paragraph [0116] teaches depletion mode devices monolithically integrated on a GaN power FET substrate. The skilled person uses a depletion mode FET as a level shifter as a functional equivalent of, and an obvious alternative to the diode-connected FET M36 in Fig. 1 of Arnold, claims 8, 9).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Also, see US PGpub 2023/0314486.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897