DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed June 25, 2026 is acknowledged. New claim 18 has been added. Claim 9 has been amended. Non-elected Invention, Claims 1-8 have been withdrawn from consideration Claims 1-18 are pending.
Action on merits of claims follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 25, 2026 was filed after the mailing date of the Office Action on March 25, 2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The newly submitted title is not descriptive. The title is:
A PLIT-GATE MOSFET HAVING A FIRST TRENCH WITH TAPPER SIDEWALLS COMMUNICATED WITH A SECOND TRENCH WITH VERTICAL SIDEWALLS
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 10-11 and 16-17 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 10 recites: the split-gate MOSFET according to claim 9, wherein the inner diameter of the first trench gradually increases from bottom to top.
The claimed limitation bases on the disclosure as shown in FIG. 3b, as follows:
[0050] Further, as shown in FIG. 3b, a portion, which is located on a sidewall of the cavity 1124, of the semiconductor layer 111 is removed, so that a first trench 1121 is formed. For example, by performing an oxidation process, the portion, which is located on the sidewall of the cavity 1124, of the semiconductor layer 111 can be oxidized to form an oxide layer 1123, and then the oxide layer 1123 is removed. A thickness of the portion, which is located on the sidewall of the cavity and is to be removed by etching, of the semiconductor layer is controlled by adjusting oxidant and/or etchant concentration, so that an inner diameter of a bottom of the first trench 1121 is smaller than an inner diameter of a top of the first trench 1121. For example, when the oxidant concentration is controlled to gradually decrease from top to bottom, an inner diameter of the oxide layer 1123 gradually increases from bottom to top, so that the inner diameter of the first trench 1121 gradually increases from bottom to top.
The wedge shape oxide 1123 means the upper portion of the trench is oxidized more or faster than the lower portion.
Note that the oxidation of the trench 1124 would inherently oxidize all surfaces of the trench 1124 at the same rate, hence the thermal oxide layer would have the same thickness.
What kind of oxidation of a substrate results in the wedge shape 1123?
The process step “For example, when the oxidant concentration is controlled to gradually decrease from top to bottom, an inner diameter of the oxide layer 1123 gradually increases from bottom to top, so that the inner diameter of the first trench 1121 gradually increases from bottom to top.”
As discussed above, the oxidation is subjected the whole trench 1124 to a same concentration at the same time. The oxidation does not occur in sequence, from top to bottom or bottom to top. Rather the oxidation oxidizes the surfaces, bottom, sidewalls, top, simultaneously, at the same time.
The wedge shape oxide layer 1123 does not exist, or does not support the claimed limitation “wherein the inner diameter of the first trench gradually increases from bottom to top”
Therefore, the limitation “wherein the inner diameter of the first trench gradually increases from bottom to top” based on the disclosure, fails to enable.
Applicant cites an NPL to Y. XU et al. (on June 25, 2026) then concludes: due to 2-D oxidant flux spreading oxidation retardation increases with trench depth, resulting in a non-uniform oxide thickness that is thinner at the trench bottom and thicker at the trench top.
However, contrary to the applicant’s conclusion, XU explicitly teaches: “The sidewall oxide is visibly thinner than the oxide in the planar region”. (See FIG. 6).
Clearly XU does not support an oxidation of a trench resulting in a thinner oxide at the bottom and thicker oxide at the top of the trench.
The rejection is maintained.
Claim 11 recites: the split-gate MOSFET according to claim 9, wherein an inner diameter of a bottom of the first trench is smaller than an inner diameter of a top of the first trench, and an inner diameter of the second trench substantially equals to the inner diameter of the bottom of the first trench.
As discussed above, the “an inner diameter of a bottom of the first trench is smaller than an inner diameter of a top of the first trench” is based on the removal of the wedge shape oxide 1123.
Since the wedge shape oxide cannot be formed as discussed above, the limitation “an inner diameter of a bottom of the first trench is smaller than an inner diameter of a top of the first trench” fails to enable.
Similar to claims 10 and 11 above, the limitation of claim 16 is based on the process that is fail to enable.
Since the wedge shape oxide cannot be formed as discussed above, the limitation “wherein an outer sidewall of the second dielectric layer extends in a first direction which is not perpendicular to the upper surface of the semiconductor layer, to make the outer diameter of the top portion of the second dielectric layer larger than an outer diameter of a bottom portion of the second dielectric layer” fails to enable.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 16-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites: “the split-gate MOSFET according to claim 9, wherein an outer sidewall of the second dielectric layer extends in a first direction which is not perpendicular to the upper surface of the semiconductor layer, to make the outer diameter of the top portion of the second dielectric layer larger than an outer diameter of a bottom portion of the second dielectric layer; and
an outer sidewall of the first dielectric layer extends in a second direction which is different from the first direction”.
1) “an outer sidewall of the second dielectric layer” is the sidewall of the first trench 1121.
2) “an outer sidewall of the first dielectric layer” is the sidewall of the second trench 1122.
However, claim 9, lines 5, recites: “wherein the first trench and the second trench extend in a same direction”.
The limitation of claim 16: “an outer sidewall of the first dielectric layer extends in a second direction which is different from the first direction”.
Thus, claim 16 contravenes independent claim 9.
Therefore, claims 16 and 17 are indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YILMAZ et al. (US. Pub. No. 2006/0273386).
With respect to claim 1, YILMAZ ‘386 teaches a split-gate MOSFET, as claimed including:
a semiconductor layer (1302) of a first dopant type;
a first trench (upper portion) extending from an upper surface of the semiconductor layer (1302) to an interior of the semiconductor layer, a second trench (lower portion) communicated with a bottom of the first trench, wherein the first trench and the second trench extend in a same direction;
a first dielectric layer (1310) covering an inner surface of the second trench, a second dielectric layer (1318) covering an inner surface of the first trench (upper portion), and a third dielectric layer (1316) between the first dielectric layer (1310) and the second dielectric layer (1318);
a first conductor (1312) located in the second trench and a second conductor (1320) located in the first trench, wherein the first conductor (1312) is isolated from the semiconductor layer (1302) by the first dielectric layer (1310), the second conductor (1320) is isolated from the semiconductor layer by the second dielectric layer (1318), and the first conductor (1312) is isolated from the second conductor (1320) by the third dielectric layer (1316); and
a body region (1304) of a second dopant type which is located in the semiconductor layer (1302) and adjacent to the first trench (upper portion),
wherein at each depth level within the first trench, an outer diameter of the second dielectric layer (1318) is the same as an inner diameter of the first trench, and at each depth level within the second trench, and an outer diameter of the first dielectric layer (1312) is the same as an inner diameter of the second trench,
wherein a top portion of the second dielectric layer (1318) is located below the upper surface of the semiconductor layer (1302) and between the second conductor (1320) and the semiconductor layer, and has an outer diameter larger than an outer diameter of a top portion of the first dielectric layer (1310),
wherein an outer sidewall of the second conductor (1320) extends along a direction which is not perpendicular to the upper surface of the semiconductor layer (1302). (See FIG. 13L).
With respect to claim 10, the inner diameter of the first trench (upper portion) of YILMAZ gradually increases from bottom to top.
With respect to claim 11, an inner diameter of a bottom of the first trench (upper portion) of YILMAZ is smaller than an inner diameter of a top of the first trench, and an inner diameter of the second trench (lower portion) substantially equals to the inner diameter of the bottom of the first trench.
With respect to claim 12, a thickness of the first dielectric layer (1310) of YILMAZ is greater than a thickness of the second dielectric layer (1318).
With respect to claim 13, the split-gate MOSFET of YILMAZ further comprises: a source region (1322) of the first dopant type in the body region (1304);
an interlayer dielectric layer (1324) on the source region (1322); and
a source electrode (1330) located on the interlayer dielectric layer (1324).
With respect to claim 14, the split-gate MOSFET of YILMAZ further comprises:
a body contact region (1329) of the second dopant type in the body region (1304); and
a conductive channel penetrating the interlayer dielectric layer (1316) and the source region (1322) to reach the body contact region (1329), wherein the source electrode (1330) is connected to the body contact region (1329) via the conductive channel.
With respect to claim 15, the split-gate MOSFET of YILMAZ further comprises:
a semiconductor substrate (not shown) located on a lower surface of the semiconductor layer (1302), wherein the upper surface of the semiconductor layer (1302) is opposite to the lower surface of the semiconductor layer; and
a drain electrode (not shown) located on the lower surface of the semiconductor substrate (not shown).
With respect to claim 18, a height of the first trench (upper portion) is substantially equal to a sum of a height of the second conductor (1320) and a thickness of the third dielectric layer (1316).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over YILMAZ ‘386 as applied to claim 9 above, and further in view of RANADE et al. (US. Pub. No. 2004/0180510) of record.
With respect to claim 16, As best understood by the Examiner, YILMAZ ‘386 teaches the split-gate MOSFET as described in claim 9 above including: an outer sidewall of the second dielectric layer (1318) extends in a first direction which is not perpendicular to the upper surface of the semiconductor layer (1302), to make the outer diameter of the top portion of the second dielectric layer (1318) larger than an outer diameter of a bottom portion of the second dielectric layer (1318); and an outer sidewall of the first dielectric layer (1310) extends in a second direction.
Thus, YILMAZ is shown to teach all the features of the claim with the exception of explicitly disclosing the second direction which is different from the first direction.
However, RANADE teaches a trench structure including:
a first trench (106, upper portion) extending from an upper surface of semiconductor layer (100) to the interior of the semiconductor layer, the second trench (106, lower portion) communicated with a bottom of the first trench (upper portion), wherein the first trench (upper portion) and the second trench (lower portion) extend in a same direction,
wherein an outer sidewall of the second dielectric layer (208) extends in a first direction which is not perpendicular to the upper surface of the semiconductor layer (100), to make the outer diameter of the top portion of the second dielectric layer (208) larger than an outer diameter of a bottom portion of the second dielectric layer (208); and an outer sidewall of the first dielectric layer (110) extends in a second direction which is different from the first direction. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the trench of YILMAZ ‘386 having the outer sidewall of the first dielectric layer extends in a second direction which is different from the first direction as taught by RANADE for the same intended purpose of forming the second trench communicated with the bottom of the first trench.
With respect to claim 17, in view of RANADE, the second direction is perpendicular to the upper surface of the semiconductor layer.
Response to Arguments
Applicant's arguments filed June 29, 2026, regarding the rejection under 35 USC § 112(a) have been fully considered but they are not persuasive.
Regarding claim 10, as discussed above, Applicant cites an NPL to Y. XU et al. then concludes: due to 2-D oxidant flux spreading oxidation retardation increases with trench depth, resulting in a non-uniform oxide thickness that is thinner at the trench bottom and thicker at the trench top.
However, contrary to the applicant’s conclusion, XU explicitly teaches: “The sidewall oxide is visibly thinner than the oxide in the planar region”. (See FIG. 6).
Clearly XU does not support an oxidation of a trench resulting in a thinner oxide at the bottom and thicker oxide at the top of the trench.
The rejection is maintained.
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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