DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
3. Applicant’s election without traverse of Species I, identified as encompassing claims 1-12 and 15-20 is acknowledged.
Upon detailed consideration, claim 12 is directed towards non-elected species B represented by Fig. 6 wherein a top surface of the blocking layer element 50 is concave, and is hereby withdrawn. Furthermore claims 19-20 are directed towards non-elected species C represented by Figs. 8, 10A-D, 13 wherein at least a peripheral circuit structure that includes a peripheral gate structure on a substrate and a first interlayer dielectric covering the peripheral gate structure and a bit line on the peripheral circuit structure, and are hereby withdrawn.
Therefore, claims 1-11 and 15-18 are determined as encompassed by the elected Species I, and claims 12-14 and 19-20 are withdrawn as directed towards non-elected species.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-5, 7-10 and 15-17 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Ramaswamy (US 2021/0183864 A1), hereinafter as R1
5. Regarding Claim 1, R1 discloses a semiconductor device (see in particular Figs. 1-3 and [0025] “semiconductive/semiconductor/semiconducting”), comprising:
a first conductive line (element 32, see [0031] “columns 32 of digitlines 34 (e.g., metal material and/or conductively-doped semiconductor material)”) that extends in a first horizontal direction (see Fig. 2 in the cross sectional view);
a plurality of semiconductor patterns (element 14, see [0027] “semiconductor material 12 of stem 14 comprising a lower source/drain region 22 below channel region 20”) on the first conductive line and spaced apart from each other in the first horizontal direction (see Fig. 2), each semiconductor pattern of the plurality of semiconductor patterns including a first vertical part (first part left of element 14U) and a second vertical part (second part right of element 14U) that are opposite to each other in the first horizontal direction (opposite with respect to the element 14U);
a second conductive line (element 30, see [0031] “wordlines 30 (e.g., metal material and/or conductively-doped semiconductor material)”) that extends in a second horizontal direction (see Fig. 2 into and out of the page in the cross sectional view) between the first vertical part and the second vertical part of each semiconductor pattern of the plurality of semiconductor patterns (see Figs. 1-2), the second horizontal direction intersecting the first horizontal direction (see Fig. 2 left and right intersects into and out of the page);
a gate dielectric pattern (element 26 on both sides of element 14U, see [0029] “gate insulator 26”) between the first vertical part and the second vertical part and between the second vertical part and the second conductive line (see Fig. 2); and
a blocking pattern (portions of element 77 within elements 85 and a bottom portion between elements 85, see [0035] “dielectric material 77”; note, the manner in which the claim is currently recited does not provide a structural distinction with boundaries and/or material between the dielectric pattern and the blocking pattern such that they can be arbitrarily determined) between neighboring semiconductor patterns of the plurality of semiconductor patterns (see Fig. 2).
6. Regarding Claim 2, R1 discloses the semiconductor device of claim 1,
wherein the blocking pattern includes at least one selected from a dielectric material (element 77, see [0035] “dielectric material 77”) and a conductive material.
7. Regarding Claim 3, R1 discloses the semiconductor device of claim 1,
wherein, on the first conductive line, the blocking pattern is adjacent to lower portions of the neighboring semiconductor patterns (see Fig. 2).
8. Regarding Claim 4, R1 discloses the semiconductor device of claim 1, further comprising:
a dielectric pattern (element 77 between elements 85) between the neighboring semiconductor patterns (see Fig. 2),
wherein the blocking pattern vertically separates the dielectric pattern from the first conductive line (see Fig. 2).
9. Regarding Claim 5, R1 discloses the semiconductor device of claim 4, wherein the dielectric pattern includes an oxygen atom (see [0035] “silicon dioxide”).
10. Regarding Claim 7, R1 discloses the semiconductor device of claim 1, further comprising:
a lower pattern (element 17 portions left and right of element 14U, see [0027]) between the neighboring semiconductor patterns and between the first conductive line and the blocking pattern (see Fig. 2).
11. Regarding Claim 8, R1 discloses the semiconductor device of claim 7,
wherein the lower pattern is adjacent to lower portions of the neighboring semiconductor patterns (see Fig. 2).
12. Regarding Claim 9, R1 discloses the semiconductor device of claim 7, further comprising:
a dielectric pattern (upper portion of element 77 between elements 85) between the neighboring semiconductor patterns (see Fig. 2),
wherein the blocking pattern is between the lower pattern and the dielectric pattern (see Fig. 2).
13. Regarding Claim 10, R1 discloses the semiconductor device of claim 9, wherein the blocking pattern (further comprising the lower portion of element 77 between elements 85) and the lower pattern vertically separate the dielectric pattern from the first conductive line (see Fig. 2).
14. Regarding Claim 15, R1 discloses a semiconductor device (see in particular Figs. 1-3 and [0025] “semiconductive/semiconductor/semiconducting”), comprising:
a first conductive line (element 32, see [0031] “columns 32 of digitlines 34 (e.g., metal material and/or conductively-doped semiconductor material)”) that extends in a first horizontal direction (see Fig. 2 in the cross sectional view);
a semiconductor pattern (element 14, see [0027] “semiconductor material 12 of stem 14 comprising a lower source/drain region 22 below channel region 20”) that includes a first vertical part (first part left of element 14U) and a second vertical part (second part right of element 14U) that are opposite to each other in the first horizontal direction (opposite with respect to the element 14U) on the first conductive line (see Fig. 2);
a second conductive line (element 30, see [0031] “wordlines 30 (e.g., metal material and/or conductively-doped semiconductor material)”) that includes a first sub-conductive line (element 30 left of element 14U) covering an inner lateral surface of the first vertical part (see Fig. 2) and a second sub-conductive line (element 30 right of element 14U) covering an inner lateral surface of the second vertical part (see Fig. 2), the inner lateral surface of the first vertical part and the inner lateral surface of the second vertical part being opposite to each other in the first horizontal direction (opposite with respect to the element 14U);
a gate dielectric pattern (element 26 on both sides of element 14U, see [0029] “gate insulator 26”) between the inner lateral surface of the first vertical part and the first sub-conductive line (see Fig. 2) and between the inner lateral surface of the second vertical part and the second sub-conductive line (see Fig. 2); and
a pair of blocking patterns (portions of element 77 within elements 85 and a bottom portion between elements 85, see [0035] “dielectric material 77”; the manner in which the claim is currently recited does not provide a structural distinction with boundaries and/or material between the dielectric pattern and the blocking pattern) on the first conductive line,
wherein one of the pair of blocking patterns is adjacent to a lower portion of an outer lateral surface of the first vertical part (see Fig. 2) and the other of the pair of blocking patterns is adjacent to a lower portion of an outer lateral surface of the second vertical part (see Fig. 2).
15. Regarding Claim 16, R1 discloses the semiconductor device of claim 15,
wherein each blocking pattern of the pair of blocking patterns includes at least one selected from a dielectric material (element 77, see [0035] “dielectric material 77”) and a conductive material.
16. Regarding Claim 17, R1 discloses the semiconductor device of claim 15, further comprising:
a pair of dielectric patterns (upper left half and upper right half of element 77 between elements 85) on the outer lateral surface of the first vertical part (see Fig. 2) and the outer lateral surface of the second vertical part (see Fig. 2), respectively,
wherein each blocking pattern of the pair of blocking patterns vertically separates a corresponding dielectric pattern of the pair of dielectric patterns from the first conductive line (see Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
17. Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy (US 2021/0183864 A1), hereinafter as R1, in view of Tsai (US 2022/0130832 A1), hereinafter as T1
18. Regarding Claim 6, R1 discloses the semiconductor device of claim 1,
wherein each semiconductor pattern of the plurality of semiconductor patterns further includes a horizontal part (element 17 portions left and right of element 14U, see [0027]) that extend from the first vertical part and the second vertical part towards each other.
R1 does not explicitly disclose the horizontal part connects the first vertical part and the second vertical part with each other.
T1 discloses the horizontal part connects the first vertical part and the second vertical part with each other (see Figs. 2A-B element 122 horizontal member of the U-shaped active layer element 120 connects both vertical portions elements 124, see [0063] “the channel structure 120 is substantially a U-shaped structure including a horizontal member 122 and a pair of vertical members 124 on the horizontal member 122”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with R1 because the combination allows for reduced size and reduced current leakage, and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known channel structure for another in a similar device to obtain predictable results (see Tsai Fig. 2A-B the horizontal portion is fully connected together).
19. Regarding Claim 18, R1 discloses the semiconductor device of claim 15,
wherein the semiconductor pattern further includes a horizontal part that(element 17 portions left and right of element 14U, see [0027]) that extend from the first vertical part and the second vertical part towards each other.
R1 does not explicitly disclose the horizontal part connects the first vertical part and the second vertical part with each other.
T1 discloses the horizontal part connects the first vertical part and the second vertical part with each other (see Figs. 2A-B element 122 horizontal member of the U-shaped active layer element 120 connects both vertical portions elements 124, see [0063] “the channel structure 120 is substantially a U-shaped structure including a horizontal member 122 and a pair of vertical members 124 on the horizontal member 122”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with R1 because the combination allows for reduced size and reduced current leakage, and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known channel structure for another in a similar device to obtain predictable results (see Tsai Fig. 2A-B the horizontal portion is fully connected together).
20. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy (US 2021/0183864 A1), hereinafter as R1, in view of Cho et al., (KR 20190110921 A, see attached translation document), hereinafter as C1
21. Regarding Claim 11, R1 discloses the semiconductor device of claim 7.
R1 does not disclose wherein the lower pattern includes at least one selected from hydrogen and deuterium.
C1 discloses the active pattern of the active patterns may contain hydrogen, indium or a combination of dopants (see pg. 6 “A dopant implantation process may be performed on the active patterns ACT. The dopant may comprise hydrogen, indium or a combination thereof”)
The dopant of the active layer as taught by C1 is incorporated as a dopant of the active layer of R1.
It would have obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with R1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known channel dopant for another in a similar memory device to obtain predictable results (see C1 pg. 6 and R1 [0026] “semiconductor material 12 (e.g., variously-doped silicon)”)
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818