DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 9 June 2022. It is noted, however, that applicant has not filed a certified copy of the KR10-2022-0070131 and KR10-2022-0259121 application as required by 37 CFR 1.55.
As per the application data sheet (ADS) filed 15 November 2022, the information will be used by the Office to automatically attempt retrieval of the certified foreign priority documents. However, the applicant bears the ultimate responsibility for ensuring that a copy is received by the Office from the participating foreign intellectual property office, or a certified copy of each foreign priority application is filed within the time period specified in 37 CFR 1.55(g)(1). See MPEP 215.01 and 215.02.
Response to Arguments
Applicant's arguments filed 23 January 2026 have been fully considered but they are not persuasive.
Claims 1 and 3 were rejected under 35 U.S.C. 103 as being obvious over Park et al. (KR20210027995) in view of Sato et al. (U.S. Patent Application Publication 2023/0092244) or Zhu (U.S. Patent Application Publication 2021/0098484).
Claims 1 and 3 were rejected under 35 U.S.C. 103 as being obvious over Lee et al. (U.S. Patent Application Publication 2016/0133317) in view of Sato et al. (U.S. Patent Application Publication 2023/0092244) or Zhu (U.S. Patent Application Publication 2021/0098484).
The applicant argues the teachings of the Sato reference individually. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The applicant argues that the Sato reference merely discloses a conventional fin-shaped gate structure but does not show or teach the claimed overpass-type channel structure. The applicant also provides an annotated Fig. 2 derived from the Sato reference.
The examiner respectfully disagrees with applicant’s characterization of Sato’s transistor structure and contends that the applicant’s annotations of the source, drain and arrow added to Fig. 2 are inaccurate. It is noted that a source and drain are not defined in claim 1.
Sato’s transistor structure is not conventional FinFET transistor. In the previous office action, the examiner relied on the transistor structure of Sato as shown in Fig. 2-5. Sato shows the completed transistor in Fig. 5, wherein the source and drain contacts (510a and 510b) are laterally in the direction of the channel (208) overlapping the fin shaped first gate (204), and indicates the channel length by the dotted line (512) (par. 63 and 64). The source and drain regions of Sato’s transistor are not into and out of the page as annotated by the applicant. The channel length of Sato’s transistor is increased due to the fin shape of the first gate electrode (204) with respect to the channel material (208) that overlaps the fin shape as shown and described (par. 59, 63 and 64).
As it pertains to the Park reference, as modified, the channel layer (208) of Sato overpasses the fin of the first gate (204) in a direction from the source to drain (510). Park teaches the second gate (310) extends in a same direction from the source to drain (210 and 230). The combined teachings of the Park and Sato references teach that the second gate extends in a direction parallel to an overpassing direct of the channel layer. The modification to Park is the shape of the first gate (330) to be a fin-shaped first gate (204) as taught by Sato resulting in the transistor with gate insulator and channel shape that flow from that known gate shape and improvements associated therewith as taught. Examiner annotated portions of each figure from Park and Lee showing the same direction from source to drain are shown below.
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Fig. 3 of Park (left) and Fig. 5 of Sato (right)
The applicant does not provide any remarks with respect to the combination of the Park and Sato references, the combination of the Park and Zhu references, the combination of the Lee and Sato references or the combination of the Lee and Zhu references.
The examiner contends that claims 1 and 3 as amended are not patentable over Park in view of Sato or Zhu and are not patentable over Lee in view of Sato or Zhu.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being obvious over Park et al. (KR20210027995) in view of Sato et al. (U.S. Patent Application Publication 2023/0092244) or Zhu (U.S. Patent Application Publication 2021/0098484).
Referring to Claim 1, Park teaches in Fig. 3 for example, an overpass-type semiconductor device comprising: a first gate (330); a charge storage layer (430) formed on the first gate (330); a channel layer (100) formed on a part of the charge storage layer (430) and configured to overpass the first gate (330) in a direction between the source and drain (210 and 230); a gate insulating layer (410) formed on the channel layer (100); and a second gate (310) formed on the gate insulating layer (410) and configured to extend in a direction parallel to an overpassing direction (between the source and drain, 210 and 230) of the channel layer (100).
Park does not explicitly teach the claimed shape of the first gate (330) as including a fin having a preset height; wherein the fin protrudes in a height direction from a center of the first gate (330), and the channel overpasses the fin.
Zhu teaches an overpass-type semiconductor device comprising: a first gate (104) including a fin (raised central portion) having a preset height; a charge storage layer (108) formed on the first gate (104) and the fin (raised central portion); a channel layer (112) formed on a part of the charge storage layer (108) and configured to overpass the fin (raised central portion) of the first gate (104); wherein the fin (raised central portion) protrudes in a height direction from a center of the first gate (104).
Sato teaches in Fig. 2-5 for example an overpass-type semiconductor device comprising: a first gate (204) including a fin (210) having a preset height (Fig. 3; 306; par. 38); a dielectric layer (206) formed on the first gate (204) and the fin (210); a channel layer (208) formed on a part of the dielectric layer (206) and configured to overpass the fin (210) of the first gate (204); wherein the fin (210) protrudes in a height direction from a center of the first gate (204).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the first gate shape including a fin as taught by Zhu or Sato as the shape of the first gate of Park in order to mitigate charge spreading effects without increasing fabrication complexity and increase memory density without occupying more chip area (Zhu; par. 3, 4, 39 and 67) and/or to increase the channel length thereby mitigating the short channel effects thus reducing leakage current, improving reliability and maintaining high transistor density (Sato; par. 19-23)
Referring to Claim 3, as modified above, Park in view of Zhu or Sato further teach a tunneling insulating layer (420) formed between the channel layer (100) and the charge storage layer (430); and a blocking insulating layer (440) formed between the charge storage layer (430) and the first gate (330).
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being obvious over Lee et al. (U.S. Patent Application Publication 2016/0133317) in view of Sato et al. (U.S. Patent Application Publication 2023/0092244) or Zhu (U.S. Patent Application Publication 2021/0098484).
Referring to Claim 1, Lee teaches in Fig. 1 and 2 for example (par. 50), an overpass-type semiconductor device comprising: a first gate (BG1); a charge storage layer (of stack 120; par. 54-60) formed on the first gate (BG1); a channel layer (150) formed on a part of the charge storage layer (of stack 120) and configured to overpass the first gate (BG1) in a direction between the source and drain (S and D1/D2); a gate insulating layer (of stack 140; par. 50) formed on the channel layer (150); and a second gate (170) formed on the gate insulating layer (of stack 140) and configured to extend in a direction parallel to an overpassing direction (between the source and drain, S and D1/D2) of the channel layer (150).
Lee does not explicitly teach, per se, that the claimed shape of the first gate (BG1) as including a fin having a preset height; wherein the fin protrudes in a height direction from a center of the first gate (BG1), and the channel overpasses the fin.
Zhu teaches an overpass-type semiconductor device comprising: a first gate (104) including a fin (raised central portion) having a preset height; a charge storage layer (108) formed on the first gate (104) and the fin (raised central portion); a channel layer (112) formed on a part of the charge storage layer (108) and configured to overpass the fin (raised central portion) of the first gate (104); wherein the fin (raised central portion) protrudes in a height direction from a center of the first gate (104).
Sato teaches in Fig. 2-5 for example an overpass-type semiconductor device comprising: a first gate (204) including a fin (210) having a preset height (Fig. 3; 306; par. 38); a dielectric layer (206) formed on the first gate (204) and the fin (210); a channel layer (208) formed on a part of the dielectric layer (206); wherein the fin (210) protrudes in a height direction from a center of the first gate (204), and the channel (208) overpasses the fin (214).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the first gate shape including a fin as taught by Zhu or Sato as the shape of the first gate of Lee in order to mitigate charge spreading effects without increasing fabrication complexity and increase memory density without occupying more chip area (Zhu; par. 3, 4, 39 and 67) and/or to increase the channel length thereby mitigating the short channel effects thus reducing leakage current, improving reliability and maintaining high transistor density (Sato; par. 19-23)
Referring to Claim 3, as modified above, Lee further teaches a tunneling insulating layer formed between the channel layer (150) and the charge storage layer; and a blocking insulating layer formed between the charge storage layer and the first gate (BG1) (par. 54-56).
Allowable Subject Matter
Claims 2 and 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7-10 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the overpass-type semiconductor device comprising wherein the drain shares a same voltage line as the second gate in combination with all of the limitations of claims 1 and 2. Claims 4-6 include the limitations of claim 2.
Regarding Claim 7, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the synaptic array comprising the structure configured for wherein an event-driven operation of simultaneously receiving an input signal to the second gate lines and the drain lines and outputting an output signal from the first and second source lines is enabled in combination with all of the limitations of claim 7.
Referring to claim 8, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the control method of a synaptic array comprising setting a weight of the target semiconductor device by applying a second voltage to the second gate and a drain of the target semiconductor device in combination with all of the limitations of claims 7 and 8. Claims 9-10 include the limitations of claim 8.
Regarding claims 7 and 8, it is noted that Park (KR20210027995) teaches the synaptic array the synaptic array comprising: first to fourth semiconductor devices arranged in an array, each of the first to fourth semiconductor devices includes a first gate (330), a charge storage layer (400) formed on the first gate (330), a channel layer (100) formed on a part of the charge storage layer (400) and configured to overpass the first gate (330), a gate insulating layer (410) formed on the channel layer (400), and a second gate (310) formed on the gate insulating layer (410) and configured to extend in a direction parallel to an overpassing direction of the channel layer (100), one second gate line (2315) connecting the second gate (top gate) of the first semiconductor device to the second gate (top gate) of the second semiconductor device; another second gate line (1315) connecting the second gate (top gate) of the third semiconductor device to the second gate (top gate) of the fourth semiconductor device; one drain line (2235) shared by the first semiconductor device and the second semiconductor device; another drain line (1235) shared by the third semiconductor device and the fourth semiconductor device; one first gate line (1335) connecting the first gate (bottom gate) of the first semiconductor device to the first gate (bottom gate) of the third semiconductor device; another first gate line (2335) connecting the first gate (bottom gate) of the second semiconductor device to the first gate (bottom gate) of the fourth semiconductor device; one source line (1215) shared by the first semiconductor device and the third semiconductor device; and another source line (2215) shared by the second semiconductor device and the fourth semiconductor device. Park does not teach the shape of the first gate as having the fin shape, but that aspect would be obvious as provided above. The inventive distinction is that Park does not teach the synaptic array structure configured for simultaneously receiving an input signal to the second gate lines (2315 and 1315) and the drain lines (2235 and 1235) and outputting an output signal from the first and second source lines (1215 and 2215). In other words, the second gate lines are not electrically connected to the drain lines to have the same second voltage simultaneously.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896