Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 17/987628 has Claims 1-10 pending.
Priority / Filing Date
Applicant claimed priority from U.S. provisional application No. 63/345,751. The priority filing date of this application is May 25, 2022.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the Applicant’s submissions of the Information Disclosure Statements dated September 18, 2024 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of each of the PTOL-1449s initialed and dated by the Examiner is attached to the instant Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-10 are rejected under 35 U.S.C. 103 as being obvious over Windh et al. hereafter Windh (Pub. No.: US 2023/0305842 A1), in view of Zhang et al. hereafter Zhang (Pub. No.: US 2023/0281156 A1).
Regarding Claim 1, Windh disclose a computer-implemented method for optimizing buffer allocation within a contiguous area in an array of reconfigurable units including at least a first physical memory unit and a second physical memory unit (Windh: abstract; Fleming: abstract)), the method comprising:
temporarily assigning a (Windh: Figure 3, [0025]-[0026], [0041]-[0046]: The Coarse
Grained Reconfigurable Array (CGRA) can have a particular structure, e.g., a number of tiles and memory interfaces, and particular inter-connectivity of Synchronous Fabric (SF)
and/or Asynchronous Fabric (AF) among the tiles);
temporarily routing connections between the first physical memory unit, the second physical memory unit, and previously mapped reconfigurable units within the contiguous area (Windh: Figure 3, [0025]-[0026], [0041]-[0046], [0049], : A typical tile 141 includes tile memories 131, ..., 133 having synchronous connections 135 with a computing logic 137; The operations of the Coarse Grained Reconfigurable Array 103 can be described and/or scheduled as flows
of data among tile memories (e.g., 131, ... , 133) of tiles (e.g., 141, 143, ... , 145) through the connections 135, 129, and 127 and the computing logic 137 at various clock cycles);
(Windh: Figure 3, [0025]-[0026], [0041]-[0046], [0049], : A typical tile 141 includes tile memories 131, ..., 133 having synchronous connections 135 with a computing logic 137; The operations of the Coarse Grained Reconfigurable Array 103 can be described and/or scheduled as flows of data among tile memories (e.g., 131, ... , 133) of tiles (e.g., 141, 143, ... , 145) through the connections 135, 129, and 127 and the computing logic 137 at various clock cycles); determining one or more candidate third physical memory units within the contiguous area, wherein the size of each candidate third physical memory unit is larger than the size of (Windh: [0063], [0068], [0069], [0072]-[0074]: The properties (e.g., 157, ... , 167, 179, .. . , 189, 193, ... ) can identify the memory access types, sizes, etc. of the respective memory variables (e.g., 153, ... , 163,175, . . . , 185, 191, ...; The tile memory information 115 can further identify access types and sizes of the set of memory variables (e.g., 153, ... , 163, 175, ... , 185, 191, ... ) for implementation in the coarse grained reconfigurable array . The set of memory variables ( e.g., 153, ... , 163, 175, ... , 185, 191, ... ) can include the first memory variables ( e.g., 153, ... , 163) identified in the dispatch interface information 111, the second memory variables ( e.g., 175, ... , 185) identified in the memory interface information 113, and at least one third memory variable 191 referring to a memory location in one or more synchronous data flows to be implemented via the coarse grained reconfigurable array 103 );
initializing (Windh: [0087]);
for each candidate third physical memory unit:
temporarily reassigning (Windh: [0063], [0068], [0069], [0072]-[0074]: The properties (e.g., 157, ... , 167, 179, .. . , 189, 193, ... ) can identify the memory access types, sizes, etc. of the respective memory variables (e.g., 153, ... , 163,175, . . . , 185, 191, ...; The tile memory information 115 can further identify access types and sizes of the set of memory variables (e.g., 153, ... , 163, 175, ... , 185, 191, ... ) for implementation in the coarse grained reconfigurable array . The set of memory variables ( e.g., 153, ... , 163, 175, ... , 185, 191, ... ) can include the first memory variables ( e.g., 153, ... , 163) identified in the dispatch interface information 111, the second memory variables ( e.g., 175, ... , 185) identified in the memory interface information 113, and at least one third memory variable 191 referring to a memory location in one or more synchronous data flows to be implemented via the coarse grained reconfigurable array 103 ), and (Windh: [0063], [0068], [0069], [0072]-[0074], [0079]: map the one or more data flows specified in the assembly language program 101 to flows of data in the coarse grained reconfigurable
array 103, including mapping the set of memory variables (e.g., 153, ... , 163, 175, ... , 185,191, ... ) to tile memories (e.g., 131, 133) in the coarse grained reconfigurable array 103) ;
determining if the second cost is better than the best cost;
updating, in response (Windh: [0063], [0068], [0069], [0072]-[0074], [0079]: map the one or more data flows specified in the assembly language program 101 to flows of data in the coarse grained reconfigurable array 103, including mapping the set of memory variables (e.g., 153, ... , 163, 175, ... , 185,191, ... ) to tile memories (e.g., 131, 133) in the coarse grained reconfigurable array 103); and
creating a configuration file that assigns both (Windh: Figure 11, [0104]- [0114]: After identifying the tile memories used to implement the second memory locations, the configuration generator 229 can identify, based on the memory interface information 113, operating controls 247 of the memory interfaces (e.g., 123 or 125) of the coarse
grained reconfigurable array 103 to store or retrieve data at or from tile memories identified to implement the second memory location).
Windh do not explicitly disclose a cost function to calculate a cost and determine best cost based upon comparing first cost with second cost.
Zhang teaches a cost function to calculate a cost and determine best cost based upon comparing first cost with second cost (Zhang: Figures 8, 9A-9B, [0108]- [0115]: a resource cost function is invoked for the compute graph and the required resource cost is compared to the available hardware resources; Determining (850) whether the candidate partition has a lower resource cost may include conducting a weighted cost comparison of the resources required by the candidate partition with the current best weighted resource cost);
Windh and Zhang are analogous art because they are from the same field of endeavor. They both relate to reconfigurable computing system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above coarse grained reconfigurable array application, as taught by Windh, and incorporating the use of cost function, as taught by Zhang.
One of ordinary skill in the art would have been motivated to do this modification in order to selecting a best candidate partition based on resource cost, as suggested by Zhang (Zhang: abstract).
Windh do not explicitly disclose buffer portions containing a first buffer and a second buffer.
Zhang disclose buffer portions containing a first buffer and a second buffer (Zhang : [0041], [0042], [0083] : Each AGCU contains FIFOs (first-in-first-out buffers for organizing data) to buffer outgoing commands, data, and incoming responses from the off-chip memory);
Windh and Zhang are analogous art because they are from the same field of endeavor. They both relate to reconfigurable computing system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above coarse grained reconfigurable array application, as taught by Windh, and incorporating the use of buffers, as taught by Zhang.
One of ordinary skill in the art would have been motivated to do this modification in order to selecting a best candidate partition based on resource cost, as suggested by Zhang (Zhang: abstract).
Regarding Claims 7 and 9, the claims recite the same substantive limitations as Claim 1 and are rejected using the same teachings.
Regarding Claim 2, the combinations of Windh and Zhang further disclose the computer-implemented method of claim 1, wherein: the array of reconfigurable units is an array of coarse-grained reconfigurable (CGR) units (Windh: [0018]: Streaming Engine (SE) implemented via a Coarse Grained Reconfigurable Array (CGRA) having interconnected computing tiles).
Regarding Claims 8 and 10, the claims recite the same substantive limitations as Claim 2 and are rejected using the same teachings.
Regarding Claim 3, the combinations of Windh and Zhang further disclose the computer-implemented method of claim 1, wherein: the candidate third physical memory units include the first physical memory unit and/or the second physical memory unit. (Windh: Figure 1, Figure 6, [0032], [0033], [0036]: Tile memory information).
Regarding Claim 4, the combinations of Windh and Zhang further disclose the computer-implemented method of claim 1, wherein: determining if the second cost is better than the best cost comprises determining if the second cost is less than the best cost (Zhang, Figure 9A, 9B, [0116], [0127]: Note the pseudo-code 900 determination of updated best cost).
Regarding Claim 5, the combinations of Windh and Zhang further disclose the computer-implemented method of claim 1, wherein: parameters for the cost function include at least one of: a weight of an edge connected to a buffer node, a bandwidth of an edge connected to a buffer node, a traffic density of an available routing channel between a physical memory unit and a neighbor, a traffic latency in an available routing channel between a physical memory unit and a neighbor, a semiconductor die area usage, or an energy usage (Zhang: [0114]: conducting a weighted cost comparison of the resources required by the candidate partition with the current best weighted resource cost; [0120]: adjacent node/operation in the compute graph; [0060]: resources for routing data among nodes on the top-level network and nodes on the ALN in each tile; [0045]: Bandwidth calculations; [0040]: performance/latency estimation)
Regarding Claim 6, the combinations of Windh and Zhang further disclose the computer-implemented method of claim 1, wherein: the array of reconfigurable units is included in a CGR architecture (CGRA) processor (Windh: [0018]: a reconfigurable unit comprises a physical memory unit [0018]: Coarse Grained Reconfigurable Array (CGRA) having interconnected computing tiles); a physical memory unit is a pattern memory unit (PMU) (Zhang: [0066]: Pattern Memory Units (PMU)); and the best cost is initialized to equal the first cost (Zhang: Figure 9A, 9B).
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fleming et al. (Pub. No.: US 2020/0004538 A1) teaches conditional operations in a configurable spatial accelerator that includes an output buffer of a first processing element coupled to an input buffer of a second processing element via a first data path that is to send a first dataflow token from the output buffer of the first processing element to the input buffer of the second processing element when the first dataflow token is received in the output buffer of the first processing element.
Raumannet al. (Patent No.: US 11,237,880 B1) teaches a system for data parallel training of a neural network on multiple reconfigurable units configured by a host with dataflow pipelines to perform different steps in the training CGRA units are configured to evaluate first and second sequential sections of neural network layers based on a respective subset of training data, and to backpropagate the error through the sections to calculate parameter gradients for the respective subset.
Sousa et al. (Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays, 2015, IESS, pp 1-11) conceptually presents a reconfigurable buffer architecture for CGRAs which can be configured at runtime to select between different schemes for memory access, i. e., addressable RAMs or pixel buffers.
Kim et al. (Memory access optimization in compilation for coarse-grained reconfigurable architectures, 2011, ACM, pp 1-27) proposes a compiler optimization for CGRA mapping to reduce the number of memory operations by mapping application operations onto PEs and data into memory banks in a way that avoids such conflicts, thereby.exploiting data reuse.
6. Examiner’s Remarks: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IFTEKHAR A KHAN whose telephone number is (571)272-5699. The examiner can normally be reached on M-F from 9:00AM-6:00PM (CST). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emerson Puente can be reached on (571)272-3652. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center and the Private Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from Patent Center or Private PAIR. Status information for unpublished applications is available through Patent Center and Private PAIR to authorized users only. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/IFTEKHAR A KHAN/Primary Examiner, Art Unit 2187