Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/21/2023, and 04/19/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements mentioned above are being considered by the examiner.
Drawings
The drawings are objected to for the following reasons:
Color photographs and color drawings are not accepted in utility applications unless a petition filed under 37 CFR 1.84(a)(2) is granted. Any such petition must be accompanied by the appropriate fee set forth in 37 CFR 1.17(h), one set of color drawings or color photographs, as appropriate, if submitted via the USPTO patent electronic filing system or three sets of color drawings or color photographs, as appropriate, if not submitted via the via USPTO patent electronic filing system, and, unless already present, an amendment to include the following language as the first paragraph of the brief description of the drawings section of the specification:
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
Color photographs will be accepted if the conditions for accepting color drawings and black and white photographs have been satisfied. See 37 CFR 1.84(b)(2).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitation of: “receiving, by the computer system, a result from the quantum annealer system, wherein the result represents a solution to the particular optimization problem”. It is unclear if the result that is received is merely a representation of a solution in some manner, or the solution itself. For purposes of examination, the Examiner interprets the limitation to mean that the result is a solution to the optimization problem.
Furthermore, claim 1 recites the limitation of: “a particular optimization problem”. It is unclear if the “particular optimization problem” is meant to be understood as a specific optimization problem, or any particular optimization problem. For purposes of examination, the Examiner interprets the limitation to be about an optimization problem, (any optimization problem).
Furthermore, claim 1 recites the limitation of: “an input representing a particular optimization problem”. It is unclear if the input is a particular optimization problem, or if the input merely represents the optimization problem in some manner.
Claims 2-7 inherit the same deficiencies as claim 1 based on dependence.
Regarding claim 2, claim 2 recites the limitation of: “for each of a plurality of numbers (n), computing, by the computer system, an embedding in the target graph of a clique graph having the number n of nodes”. It is unclear if “n” is meant to be understood as a singular value, “the number n of nodes”, or if “n” is meant to be understood as a plurality of values, “for each of a plurality of numbers (n)”. For purposes of examination, the Examiner interprets the limitation to mean that “n” is a plurality of values.
Furthermore, claim 2 recites the limitation of: “for each of a plurality of numbers (n), computing, by the computer system, an embedding in the target graph of a clique graph having the number n of nodes”. It is unclear if it is meant to be understood as somehow a singular graph contains a plurality of total nodes, “an embedding in the target graph of a clique graph having the number n of nodes”, with “n” being interpreted as a plurality of values, “plurality of numbers (n)”, or if it is meant to be understood as a graph containing the number of nodes equal to one of the values found in the plurality of values, “n”, or if it is meant to be understood as the graph contains a number of nodes equal to the size of the set of numbers “n”.
Claim 3 inherits the same deficiency as claim 2 based on dependence.
Regarding claim 4, claim 4 recites the limitation of: “wherein the target graph is specific to a particular instance of a quantum processor”. It is unclear if the target graph is specific to a specific, “particular”, instance of a quantum processor, or if the target graph is specific to any singled out instance of a quantum processor. For purposes of examination, the Examiner interprets the limitation to mean that the target graph is specific to any singled out instance of a quantum processor.
Claim 5 inherits the same deficiency as claim 4 based on dependence.
Regarding claim 6, claim 6 recites the limitation of: “wherein the target graph is specific to a particular quantum processor architecture.” It is unclear if the target graph is specific to a specific, “particular”, architecture of a quantum processor, or if the target graph is specific to any singled out architecture of a quantum processor. For purposes of examination, the Examiner interprets the limitation to mean that the target graph is specific to any singled out architecture of a quantum processor.
Claim 7 inherits the same deficiency as claim 6 based on dependence.
Regarding claim 8, claim 8 recites the limitations of: “computing, by the computer system, a first set of optimized embeddings, wherein computing the first set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, by the computer system, an optimized embedding in the first target graph of a clique graph having the number n of nodes”. It is unclear if “n” is meant to be understood as a singular value, “the number n of nodes”, or if “n” is meant to be understood as a plurality of values, “for each of a plurality of integer numbers n”. For purposes of examination, the Examiner interprets the limitation to mean that “n” is a plurality of values.
Furthermore, claim 8 recites the limitations of: “computing, by the computer system, a first set of optimized embeddings, wherein computing the first set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, by the computer system, an optimized embedding in the first target graph of a clique graph having the number n of nodes” It is unclear if it is meant to be understood as somehow a singular graph contains a plurality of total nodes, “an optimized embedding in the first target graph of a clique graph having the number n of nodes”, with “n” being interpreted as a plurality of values, “plurality of integer numbers n”, or if it is meant to be understood as a graph containing the number of nodes equal to one of the values found in the plurality of values, “n”, or if it is meant to be understood as the graph contains a number of nodes equal to the size of the set of numbers “n”.
Claims 9-13 inherit the same deficiency as claim 8 based on dependence.
Regarding claim 10, claim 10 recites the limitations of: “computing a second set of optimized embeddings, wherein computing the second set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, by the computer system, an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes”. It is unclear if “n” is meant to be understood as a singular value, “the number n of nodes”, or if “n” is meant to be understood as a plurality of values, “for each of a plurality of integer numbers n”. For purposes of examination, the Examiner interprets the limitation to mean that “n” is a plurality of values.
Furthermore, claim 10 recites the limitations of: “computing a second set of optimized embeddings, wherein computing the second set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, by the computer system, an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes” It is unclear if it is meant to be understood as somehow a singular graph contains a plurality of total nodes, “an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes”, with “n” being interpreted as a plurality of values, “plurality of integer numbers n”, or if it is meant to be understood as a graph containing the number of nodes equal to one of the values found in the plurality of values, “n”, or if it is meant to be understood as the graph contains a number of nodes equal to the size of the set of numbers “n”.
Claim 11 inherits the same deficiency as claim 10 based on dependence.
Regarding claim 12, claim 12 recites the limitations of: “computing a second set of optimized embeddings, wherein computing the second set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, by the computer system, an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes”. It is unclear if “n” is meant to be understood as a singular value, “the number n of nodes”, or if “n” is meant to be understood as a plurality of values, “for each of a plurality of integer numbers n”. For purposes of examination, the Examiner interprets the limitation to mean that “n” is a plurality of values.
Furthermore, claim 12 recites the limitations of: “computing a second set of optimized embeddings, wherein computing the second set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, by the computer system, an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes” It is unclear if it is meant to be understood as somehow a singular graph contains a plurality of total nodes, “an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes”, with “n” being interpreted as a plurality of values, “plurality of integer numbers n”, or if it is meant to be understood as a graph containing the number of nodes equal to one of the values found in the plurality of values, “n”, or if it is meant to be understood as the graph contains a number of nodes equal to the size of the set of numbers “n”.
Claim 13 inherits the same deficiency as claim 12 based on dependence.
Regarding claim 14, claim 14 recites the limitation of: “receive a result from the quantum annealer, wherein the result represents a solution to the particular optimization problem”. It is unclear if the result that is received is merely a representation of a solution in some manner, or the solution itself. For purposes of examination, the Examiner interprets the limitation to mean that the result is a solution to the optimization problem.
Furthermore, claim 14 recites the limitation of: “a particular optimization problem”. It is unclear if the “particular optimization problem” is meant to be understood as a specific optimization problem, or any particular optimization problem. For purposes of examination, the Examiner interprets the limitation to be about an optimization problem, (any optimization problem).
Furthermore, claim 14 recites the limitation of: “an input representing a particular optimization problem”. It is unclear if the input is a particular optimization problem, or if the input merely represents the optimization problem in some manner.
Furthermore, claim 14 recites the limitation of: “a quantum annealer system having a quantum processor with the architecture represented by the target graph; and receive a result from the quantum annealer”. It is unclear if the “quantum annealer” is the same as “quantum annealer system”, or if the “quantum annealer” is part of the “quantum annealer system”, or if the “quantum annealer” is entirely different or part of a different system than the “quantum annealer system”. For purposes of examination, the Examiner interprets the “quantum annealer” to be the same as the “quantum annealer system”.
Furthermore, regarding claim 14, the bounds of the claim are unclear because the claim does not provide a discernable boundary on what structure in the claimed processor performs the claimed functions as recited the claim: “obtain an input representing a particular optimization problem, wherein the particular optimization problem maps to an input network graph having a number (no) of nodes; access a library of precomputed embeddings that includes a precomputed embedding of each of a plurality of clique graphs in a target graph representing an architecture of a quantum processor, wherein different clique graphs in the plurality of clique graphs have different numbers of nodes; retrieve from the library a first precomputed embedding of a clique graph having the number no of nodes; the first precomputed embedding based on the input network graph, thereby computing a problem-specific embedding; provide the problem-specific embedding to a quantum annealer system having a quantum processor with the architecture represented by the target graph; and receive a result from the quantum annealer, wherein the result represents a solution to the particular optimization problem.” The functions which the processor is claimed do not follow from the structure recited in the claim, so it is unclear whether the function requires some other structure or is simply a result of operating the processor in a certain manner. Therefore, one of ordinary skill in the art would not be able to draw a clear boundary between what is and is not covered by the claims. See MPEP 2173.05(g) for more information.
Claims 15-20 inherit the same deficiencies as claim 14 based on dependence.
Regarding claim 15, claim 15 recites the limitation of: “compute, for each of a plurality of numbers (n), an embedding in the target graph of a clique graph having the number n of nodes”. It is unclear if “n” is meant to be understood as a singular value, “the number n of nodes”, or if “n” is meant to be understood as a plurality of values, “for each of a plurality of numbers (n)”. For purposes of examination, the Examiner interprets the limitation to mean that “n” is a plurality of values.
Furthermore, claim 15 recites the limitation of: “compute, for each of a plurality of numbers (n), an embedding in the target graph of a clique graph having the number n of nodes”. It is unclear if it is meant to be understood as somehow a singular graph contains a plurality of total nodes, “an embedding in the target graph of a clique graph having the number n of nodes”, with “n” being interpreted as a plurality of values, “plurality of numbers (n)”, or if it is meant to be understood as a graph containing the number of nodes equal to one of the values found in the plurality of values, “n”, or if it is meant to be understood as the graph contains a number of nodes equal to the size of the set of numbers “n”.
Furthermore, regarding claim 15, the bounds of the claim are unclear because the claim does not provide a discernable boundary on what structure in the claimed processor performs the claimed functions as recited the claim: “wherein the processor is further configured to, prior to obtaining the input: compute, for each of a plurality of numbers (n), an embedding in the target graph of a clique graph having the number n of nodes; and store the computed embeddings in the library.” The functions which the processor is claimed do not follow from the structure recited in the claim, so it is unclear whether the function requires some other structure or is simply a result of operating the processor in a certain manner. Therefore, one of ordinary skill in the art would not be able to draw a clear boundary between what is and is not covered by the claims. See MPEP 2173.05(g) for more information.
Claim 16 inherits the same deficiency as claim 15 based on dependence.
Regarding claim 17, claim 17 recites the limitation of: “wherein the target graph is specific to a particular instance of a quantum processor”. It is unclear if the target graph is specific to a specific, “particular”, instance of a quantum processor, or if the target graph is specific to any singled out instance of a quantum processor. For purposes of examination, the Examiner interprets the limitation to mean that the target graph is specific to any singled out instance of a quantum processor.
Claim 18 inherits the same deficiency as claim 17 based on dependence.
Regarding claim 18, the bounds of the claim are unclear because the claim does not provide a discernable boundary on what structure in the claimed processor performs the claimed functions as recited the claim: “wherein the processor is further configured such that accessing the library includes specifying the particular instance of the quantum processor.” The functions which the processor is claimed do not follow from the structure recited in the claim, so it is unclear whether the function requires some other structure or is simply a result of operating the processor in a certain manner. Therefore, one of ordinary skill in the art would not be able to draw a clear boundary between what is and is not covered by the claims. See MPEP 2173.05(g) for more information.
Regarding claim 19, claim 19 recites the limitation of: “wherein the target graph is specific to a particular quantum processor architecture.” It is unclear if the target graph is specific to a specific, “particular”, architecture of a quantum processor, or if the target graph is specific to any singled out architecture of a quantum processor. For purposes of examination, the Examiner interprets the limitation to mean that the target graph is specific to any singled out architecture of a quantum processor.
Claim 20 inherits the same deficiency as claim 19 based on dependence.
Regarding claim 20, the bounds of the claim are unclear because the claim does not provide a discernable boundary on what structure in the claimed processor performs the claimed functions as recited the claim: “wherein the processor is further configured such that accessing the library includes specifying one particular quantum processor architecture.” The functions which the processor is claimed do not follow from the structure recited in the claim, so it is unclear whether the function requires some other structure or is simply a result of operating the processor in a certain manner. Therefore, one of ordinary skill in the art would not be able to draw a clear boundary between what is and is not covered by the claims. See MPEP 2173.05(g) for more information.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Regarding claim 1, under the Alice Framework Step 1, claim 1 falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 1 recites an abstract idea, including mathematical concepts. Specifically, claim 1 recites the following mental process, mathematical relationships, formulas, calculations:
A method comprising: an input representing a particular optimization problem, wherein the particular optimization problem maps to an input network graph having a number (no) of nodes; a library of precomputed embeddings that includes a precomputed embedding of each of a plurality of clique graphs in a target graph representing, wherein different clique graphs in the plurality of clique graphs have different numbers of nodes; from the library, a first precomputed embedding of a clique graph having the number no of nodes; an operation to modify the first precomputed embedding based on the input network graph, thereby computing a problem-specific embedding; providing, the problem-specific embedding having a represented by the target graph; a result from, wherein the result represents a solution to the particular optimization problem.
Under the Alice Framework Step 2A prong 2 analysis, claim 1 recites additional elements of, “computer system”, “accessing, by the computer system”, “quantum processor architecture”, “retrieving”, “receiving”, “obtaining”, “executing, by the computer system”, “quantum annealer system having a quantum processor with the architecture”, and “quantum annealer system”. The recited additional elements of “computer system”, “accessing, by the computer system”, and “executing, by the computer system” describe merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.04(d)(I), and 2106.05(f). Furthermore, the additional elements of “retrieving”, “receiving” and “obtaining” are mere data gathering, and considered insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). Furthermore, the additional elements of “quantum processor architecture”, “quantum annealer system having a quantum processor with the architecture”, and “quantum annealer system” are generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). Furthermore, the additional element of “quantum processor architecture” is merely a reference to which a mathematical concept represents, “clique graphs in a target graph representing a quantum processor architecture”. For these reasons, claim 1 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the recited additional elements of “computer system”, “accessing, by the computer system”, and “executing, by the computer system” is describing merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.05(f), 2106.05(I)(A). Furthermore, the additional elements of “retrieving”, “receiving ”, and “obtaining” are well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). Furthermore, the additional elements of “quantum processor architecture”, “quantum annealer system having a quantum processor with the architecture”, and “quantum annealer system” are merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For these reasons, claim 1 is not amounting to significantly more than an abstract idea.
Claim 2 is rejected for at least the reasons set forth with respect to claim 1. Claim 2 merely further limits the mathematical concept set forth in claim 1. Under the Alice Framework Step 2A prong 1, claim 2 recites an abstract idea, mathematical concepts. Specifically, claim 2 recites the following mathematical relationships, formulas, calculations:
further comprising, prior to the input: for each of a plurality of numbers (n), computing, an embedding in the target graph of a clique graph having the number n of nodes; and the computed embeddings in the library.
Under the Alice Framework Step 2A prong 2 analysis, claim 2 recites a further additional element of, “storing”. The additional element of “storing” is insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional element of claim 2, “storing”, is well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 3 is rejected for at least the reasons set forth with respect to claim 2. Claim 3 merely further limits the mathematical concept set forth in claim 2. Under the Alice Framework Step 2A prong 1, claim 3 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 3 recites the following mental process, mathematical formulas, mathematical relationships:
wherein the plurality of numbers n includes all integers n for which nmin
≤
n
≤
nmax, wherein: nmin is a preselected minimum number; and nmax is a largest number for which an embedding of a clique graph having nmax nodes in the target graph exists.
Claim 3 recites no further additional elements that would require further analysis under Step 2A prong 2 and Step 2B.
Claim 4 is rejected for at least the reasons set forth with respect to claim 1. Claim 4 merely further limits the mathematical concept set forth in claim 1. Under the Alice Framework Step 2A prong 1, claim 4 recites an abstract idea, mathematical concepts. Specifically, claim 4 recites the following mathematical formulas, mathematical relationships:
wherein the target graph is specific to a particular instance.
Under the Alice Framework Step 2A prong 2 analysis, claim 4 recites a further additional element of, “quantum processor”. The additional element of “quantum processor” is generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional element of claim 4, “quantum processor”, is merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 5 is rejected for at least the reasons set forth with respect to claim 4. Claim 5 merely further limits the mathematical concept set forth in claim 4. Under the Alice Framework Step 2A prong 1, claim 5 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 5 recites the following mental process, and mathematical relationships, formulas, calculations:
wherein the library includes precomputed embeddings for two or more different instances and wherein accessing the library includes specifying one particular instance.
Claim 5 recites no further additional elements that would require further analysis under Step 2A prong 2 and Step 2B.
Claim 6 is rejected for at least the reasons set forth with respect to claim 1. Claim 6 merely further limits the mathematical concept set forth in claim 1. Under the Alice Framework Step 2A prong 1, claim 6 recites an abstract idea, mathematical concepts. Specifically, claim 6 recites the following mathematical formulas, mathematical relationships:
wherein the target graph is specific to a particular.
Claim 6 recites no further additional elements that would require further analysis under Step 2A prong 2 and Step 2B.
Claim 7 is rejected for at least the reasons set forth with respect to claim 6. Claim 7 merely further limits the mathematical concept set forth in claim 6. Under the Alice Framework Step 2A prong 1, claim 7 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 7 recites the following mental process, and mathematical relationships, formulas, calculations:
wherein the library includes precomputed embeddings for two or more different and wherein accessing the library includes specifying one particular.
Claim 7 recites no further additional elements that would require further analysis under Step 2A prong 2 and Step 2B.
Regarding claim 8, under the Alice Framework Step 1, claim 8 falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 8 recites an abstract idea, including mathematical concepts. Specifically, claim 8 recites the following mathematical relationships, formulas, calculations:
A method comprising: a first target graph representing a first; computing, a first set of optimized embeddings, wherein computing the first set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, an optimized embedding in the first target graph of a clique graph having the number n of nodes; and the first set of optimized embeddings in a library.
Under the Alice Framework Step 2A prong 2 analysis, claim 8 recites additional elements of, “obtaining”, “computer system”, “quantum processor architecture”, and “storing”. The additional element of “computer system”, describe merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.04(d)(I), and 2106.05(f). Furthermore, the additional element of “quantum processor architecture” is generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). Furthermore, the additional elements of “obtaining”, “storing” are mere data gathering, and considered insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). For these reasons, claim 8 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the recited additional elements of “computer system” is describing merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.05(f), 2106.05(I)(A). Furthermore, the additional elements of “obtaining”, “storing” are well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). Furthermore, the additional element of “quantum processor architecture” is merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For these reasons, claim 8 is not amounting to significantly more than an abstract idea.
Claim 9 is rejected for at least the reasons set forth with respect to claim 8. Claim 9 merely further limits the mathematical concept set forth in claim 8. Under the Alice Framework Step 2A prong 1, claim 9 recites an abstract idea, mental process, mathematical concepts. Specifically, claim 9 recites the following mental process, mathematical formulas, mathematical relationships:
further comprising: a request from a client for a embedding, the request specifying a number n0 of nodes; the optimized embedding having the number n0 of nodes from the library; and the optimized embedding having the number n0 of nodes.
Under the Alice Framework Step 2A prong 2 analysis, claim 9 recites a further additional elements of, “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client”. The additional elements of “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client” is considered insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional elements of claim 9, “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client”, are well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). For this reason, the claim is not amounting to significantly more than an abstract idea. For these reasons, the claim is not amounting to significantly more than an abstract idea.
Claim 10 is rejected for at least the reasons set forth with respect to claim 8. Claim 10 merely further limits the mathematical concept set forth in claim 8. Under the Alice Framework Step 2A prong 1, claim 10 recites an abstract idea, mathematical concepts. Specifically, claim 10 recites the following mathematical relationships, formulas, calculations:
wherein the first target graph represents a first specific and wherein the method further comprises: a second target graph representing a second specific; computing a second set of optimized embeddings, wherein computing the second set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes; and the second set of optimized embeddings in the library.
Under the Alice Framework Step 2A prong 2 analysis, the further additional element of claim 10, “quantum processor having the first quantum processor architecture” is generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). Furthermore, the additional element of “quantum processor having the first quantum processor architecture” is merely a reference to which a mathematical concept represents, “the first target graph represents a first specific quantum processor having the first quantum processor architecture”. For these reasons, claim 10 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional element of claim 10, “quantum processor having the first quantum processor architecture” is merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 11 is rejected for at least the reasons set forth with respect to claim 10. Claim 11 merely further limits the mathematical concept set forth in claim 10. Under the Alice Framework Step 2A prong 1, claim 11 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 11 recites the following mental process, mathematical formulas, mathematical relationships:
further comprising: a request from a client for a embedding, the request specifying a number n0 of nodes and a particular; selecting, one of the first set or the second set of optimized embeddings based on the particular specified in the request; the optimized embedding having the number n0 of nodes from the selected set of optimized embeddings; and the optimized embedding having the number n0 of nodes.
Under the Alice Framework Step 2A prong 2 analysis, claim 11 recites a further additional elements of, “receiving”, “retrieving”, “stored”, “quantum processor” and “communicating, from the computer system to the client”. The additional elements of “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client” is considered insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). Furthermore, the additional element of “quantum processor” is generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). For these reasons, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional elements of claim 11, “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client”, are well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). Furthermore, the additional element of “quantum processor” is merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 12 is rejected for at least the reasons set forth with respect to claim 8. Claim 12 merely further limits the mathematical concept set forth in claim 8. Under the Alice Framework Step 2A prong 1, claim 12 recites an abstract idea, mathematical concepts. Specifically, claim 12 recites the following mathematical relationships, formulas, calculations:
further comprising: a second target graph representing a second; computing a second set of optimized embeddings, wherein computing the second set of optimized embeddings includes, for each of a plurality of integer numbers n, computing, an optimized embedding in the second target graph of a fully connected network graph having the number n of nodes; and the second set of optimized embeddings in the library.
Claim 12 recites no further additional elements that would require further analysis under Step 2A prong 2 and Step 2B.
Claim 13 is rejected for at least the reasons set forth with respect to claim 12. Claim 13 merely further limits the mathematical concept set forth in claim 12. Under the Alice Framework Step 2A prong 1, claim 13 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 13 recites the following mental process, mathematical formulas, mathematical relationships:
further comprising: a request from a client for a embedding, the request specifying a number n0 of nodes and a particular; selecting, one of the first set or the second set of optimized embeddings based on the particular specified in the request; the optimized embedding having the number n0 of nodes from the selected set of optimized embeddings; and the optimized embedding having the number n0 of nodes.
Under the Alice Framework Step 2A prong 2 analysis, claim 13 recites a further additional elements of, “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client”. The additional elements of “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client” is considered insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). For these reasons, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional elements of claim 13, “receiving”, “retrieving”, “stored”, and “communicating, from the computer system to the client”, are well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). For this reason, the claim is not amounting to significantly more than an abstract idea.
Regarding claim 14, under the Alice Framework Step 1, claim 14 falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 14 recites an abstract idea, including mathematical concepts. Specifically, claim 14 recites the following mathematical relationships, formulas, calculations:
A comprising: and configured to: an input representing a particular optimization problem, wherein the particular optimization problem maps to an input network graph having a number (n0) of nodes; access a library of precomputed embeddings that includes a precomputed embedding of each of a plurality of clique graphs in a target graph representing an, wherein different clique graphs in the plurality of clique graphs have different numbers of nodes; from the library a first precomputed embedding of a clique graph having the number n0 of nodes; the first precomputed embedding based on the input network graph, thereby computing a problem-specific embedding; provide the problem-specific embedding to a having a represented by the target graph; and a result from the, wherein the result represents a solution to the particular optimization problem.
Under the Alice Framework Step 2A prong 2 analysis, claim 14 recites additional elements of, “system”, “memory”, “processor coupled to the memory”, “obtain”, “architecture of a quantum processor”, “retrieve”, “quantum annealer system”, “quantum processor with the architecture”, “receive”, “quantum annealer”. The recited additional elements of “system”, “memory”, “processor coupled to the memory” describe merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.04(d)(I), and 2106.05(f). Furthermore, the additional elements of “retrieve”, “receive” and “obtain” are mere data gathering, and considered insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). Furthermore, the additional elements of “architecture of a quantum processor”, “quantum annealer system”, “quantum processor with the architecture”, “quantum annealer”, are generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). Furthermore, the additional elements of “quantum processor with the architecture”, “architecture of a quantum processor” is merely a reference to which a mathematical concept represents, “a quantum processor with the architecture represented by the target graph”. For these reasons, claim 14 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the recited additional elements of “system”, “memory”, “processor coupled to the memory” is describing merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.05(f), 2106.05(I)(A). Furthermore, the additional elements of “retrieve”, “receive” and “obtain” are well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). Furthermore, the additional elements of “architecture of a quantum processor”, “quantum annealer system”, “quantum processor with the architecture”, “quantum annealer”, are merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For these reasons, claim 14 is not amounting to significantly more than an abstract idea.
Claim 15 is rejected for at least the reasons set forth with respect to claim 14. Claim 15 merely further limits the mathematical concept set forth in claim 14. Under the Alice Framework Step 2A prong 1, claim 15 recites an abstract idea, mathematical concepts. Specifically, claim 15 recites the following mathematical relationships, formulas, calculations:
wherein the is further configured to, prior to the input: compute, for each of a plurality of numbers (n), an embedding in the target graph of a clique graph having the number n of nodes; and the computed embeddings in the library.
Under the Alice Framework Step 2A prong 2 analysis, claim 15 recites further additional elements of, “processor”, “obtaining”, and “store”. The additional elements of “obtaining”, and “store” are insignificant extra-solution activity, see MPEP 2106.04(d), 2106.05(g). Furthermore, the additional element of “processor” describes merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.04(d)(I), and 2106.05(f). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional elements of claim 15, “obtaining”, and “store” are well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i), 2106.05(d)(II)(iv). Furthermore, the additional element of “processor” is describing merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.05(f), 2106.05(I)(A). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 16 is rejected for at least the reasons set forth with respect to claim 15. Claim 16 merely further limits the mathematical concept set forth in claim 15. Under the Alice Framework Step 2A prong 1, claim 16 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 16 recites the following mental process, mathematical formulas, mathematical relationships:
wherein the plurality of numbers n includes all integers n for which nmin
≤
n
≤
nmax, wherein: nmin is a preselected minimum number; and nmax is a largest number for which an embedding of a clique graph having nmax nodes in the target graph exists.
Claim 16 recites no further additional elements that would require further analysis under Step 2A prong 2 and Step 2B.
Claim 17 is rejected for at least the reasons set forth with respect to claim 14. Claim 17 merely further limits the mathematical concept set forth in claim 14. Under the Alice Framework Step 2A prong 1, claim 17 recites an abstract idea, mathematical concepts. Specifically, claim 17 recites the following mathematical formulas, mathematical relationships:
wherein the target graph is specific to a particular instance.
Under the Alice Framework Step 2A prong 2 analysis, claim 17 recites a further additional element of, “quantum processor”. The additional element of “quantum processor” is generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional element of claim 17, “quantum processor”, is merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 18 is rejected for at least the reasons set forth with respect to claim 17. Claim 18 merely further limits the mathematical concept set forth in claim 17. Under the Alice Framework Step 2A prong 1, claim 18 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 18 recites the following mental process, mathematical relationships, formulas, calculations:
wherein the library includes precomputed embeddings for two or more different instances of the and wherein the is further configured such that accessing the library includes specifying the particular instance.
Under the Alice Framework Step 2A prong 2 analysis, claim 18 recites a further additional element of, “processor”. The additional element of “processor” describes merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.04(d)(I), and 2106.05(f). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional elements of claim 18, the additional element of “processor” is describing merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.05(f), 2106.05(I)(A). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 19 is rejected for at least the reasons set forth with respect to claim 14. Claim 19 merely further limits the mathematical concept set forth in claim 14. Under the Alice Framework Step 2A prong 1, claim 19 recites an abstract idea, mathematical concepts. Specifically, claim 19 recites the following mathematical formulas, mathematical relationships:
wherein the target graph is specific to a particular.
Under the Alice Framework Step 2A prong 2 analysis, claim 19 recites a further additional element of, “quantum processor architecture”. The additional element of “quantum processor architecture” is generally linking to a particular technological environment, see 2106.04(d)(I), 2106.05(h), and 2106.05(A). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional element of claim 19, “quantum processor architecture”, is merely generally linking to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim 20 is rejected for at least the reasons set forth with respect to claim 19. Claim 20 merely further limits the mathematical concept set forth in claim 19. Under the Alice Framework Step 2A prong 1, claim 20 recites an abstract idea, mental process, and mathematical concepts. Specifically, claim 20 recites the following mathematical relationships, formulas, calculations:
wherein the library includes precomputed embeddings for two or more different and wherein the is further configured such that accessing the library includes specifying one particular.
Under the Alice Framework Step 2A prong 2 analysis, claim 20 recites a further additional element of, “processor”. The additional element of “processor” describes merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.04(d)(I), and 2106.05(f). For this reason, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the further additional element of claim 20, the additional element of “processor” is describing merely a generic computing device upon which the abstract idea is applied, see MPEP 2106.05(f), 2106.05(I)(A). For this reason, the claim is not amounting to significantly more than an abstract idea.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-7, 14, and 17-20 are rejected under 35 U.S.C. 102(a)(1), and 102(a)(2) as being anticipated by Brahm et al. (Patent Application Publication 2018/0349282 A1), hereinafter, “Brahm”.
With regards to claim 14, Brahm teaches:
A system comprising: a memory; ([0048] regarding a processor receiving instructions from memory);
a processor coupled to the memory and configured to: obtain an input representing a particular optimization problem, ([0048] regarding a processor receiving instructions from memory; Fig. 1 regarding items 110 (Problem, as optimization problem), 120 (computer system); [0039], [0041] regarding the problem as an optimization problem);
wherein the particular optimization problem maps to an input network graph having a number (n0) of nodes; ([0027] regarding the problem being represented as a graph; [0029] regarding the graphs having a number of nodes);
access a library of precomputed embeddings that includes a precomputed embedding of each of a plurality of clique graphs in a target graph representing an architecture of a quantum processor, ([0029] regarding a database search for embeddings on the data structure, as an example, a search by number of nodes; [0004] regarding embedding mapping the problem onto the chimera graph architecture of a quantum processing device; [0005] regarding embedding of a problem on hardware such that logical variables that are related to each are mapped coupled to each other; [0007] regarding for a given problem and given hardware, there may be a large number of embeddings; [0010] regarding the data structure stores problems and their corresponding embeddings; [0021] regarding the data structure contains known pairs of problems and their corresponding embeddings (plural));
wherein different clique graphs in the plurality of clique graphs have different numbers of nodes; ([0005] regarding embedding of a problem on hardware such that logical variables that are related to each are mapped coupled to each other; [0029] regarding a database search for embeddings on the data structure, as an example, a search by number of nodes. Furthermore regarding, graphs with similar sizes. As interpreted by the Examiner, graphs having similar sizes, and a search by a number of nodes indicates that the graphs have different numbers of nodes);
retrieve from the library a first precomputed embedding of a clique graph having the number n0 of nodes; ([0029] regarding a database search for embeddings on the data structure, as an example, a search by number of nodes; [0005] regarding embedding of a problem on hardware such that logical variables that are related to each are mapped coupled to each other; [0030] regarding precomputed embeddings are returned for a successful search query);
the first precomputed embedding based on the input network graph, thereby computing a problem-specific embedding; ([0031] regarding embedding(s) for similar problems returned by the search query. Furthermore regarding evolving a population of embeddings to generate a suitable embedding for the current problem. Furthermore regarding the embedding algorithm making use of known embedding(s) for similar problems to accelerate a viable embedding for the current problem);
provide the problem-specific embedding to a quantum annealer system having a quantum processor with the architecture represented by the target graph; (Fig. 1 regarding items 127 (return embedding), 128 (compute new embedding store in data structure), 120 (computer system), 150 (Quantum computer), 152 (Embed problem), 154 (solve problem), and 160 (solution); [0004] regarding embedding mapping the problem onto the chimera graph architecture of a quantum processing device; [0019] regarding quantum annealer to solve problems; [0024] regarding the quantum computer (as quantum annealer system) having a quantum processing device that solves the embedded problem);
and receive a result from the quantum annealer, (Fig. 1 regarding items 127 (return embedding), 128 (compute new embedding store in data structure), 120 (computer system), 150 (Quantum computer), 152 (Embed problem), 154 (solve problem), and 160 (solution); [0019] regarding quantum annealer to solve problems; [0024] regarding the quantum computer (as quantum annealer system) having a quantum processing device that solves the embedded problem. Furthermore regarding the quantum computer being remote to the digital computer and user, and the quantum computer returning the solution to the user);
wherein the result represents a solution to the particular optimization problem. (Fig. 1 regarding items 127 (return embedding), 128 (compute new embedding store in data structure), 120 (computer system), 150 (Quantum computer), 152 (Embed problem), 154 (solve problem), and 160 (solution)).
With regards to claim 17, Brahm teaches the system of claim 14, as referenced above.
Brahm further teaches:
wherein the target graph is specific to a particular instance of a quantum processor. ([0004] regarding embedding mapping the problem onto the chimera graph architecture of a quantum processing device; [0027] regarding the problem being represented as a graph; [0041] regarding fitting the problem onto a model of the particular architecture of a target quantum processing device).
With regards to claim 18, Brahm teaches the system of claim 17, as referenced above.
Brahm further teaches:
wherein the library includes precomputed embeddings for two or more different instances of the quantum processor ([0041] regarding an embedding tool fitting the problem onto a model of the particular hardware architecture of a target quantum processing device; [0042] regarding an embedding optimizer running the embedding tool multiple times, different outputs for different executions);
and wherein the processor is further configured such that accessing the library includes specifying the particular instance of the quantum processor. ([0048] regarding a processor receiving instructions from memory; [0025] regarding a data structure containing previous problems that have a similar graph structure as the current problem; [0041] regarding an embedding tool fitting the problem onto a model of the particular hardware architecture of a target quantum processing device; [0042] regarding an embedding optimizer running the embedding tool multiple times, different outputs for different executions; [0043] regarding the embedded problem optimized for execution on a specific device).
With regards to claim 19, Brahm teaches the system of claim 14, as referenced above.
Brahm further teaches:
wherein the target graph is specific to a particular quantum processor architecture. ([0004] regarding embedding mapping the problem onto the chimera graph architecture of a quantum processing device; [0027] regarding the problem being represented as a graph; [0041] regarding fitting the problem onto a model of the particular architecture of a target quantum processing device).
With regards to claim 20, Brahm teaches the system of claim 19, as referenced above.
Brahm further teaches:
wherein the library includes precomputed embeddings for two or more different quantum processor architectures ([0004] regarding embedding mapping the problem onto the chimera graph architecture of a quantum processing device; [0027] regarding the problem being represented as a graph; [0041] regarding fitting the problem onto a model of the particular architecture of a target quantum processing device; [0036] regarding the backend server containing one or more domain specific libraries useful for solving problems on quantum processing devices (plural));
and wherein the processor is further configured such that accessing the library includes specifying one particular quantum processor architecture. ([0048] regarding a processor receiving instructions from memory; [0004] regarding embedding mapping the problem onto the chimera graph architecture of a quantum processing device; [0027] regarding the problem being represented as a graph; [0041] regarding fitting the problem onto a model of the particular architecture of a target quantum processing device).
Claims 1, and 4-7 are directed to a method that would be practiced by the apparatus as in claims 14, and 17-20 respectively. All steps performed by the method as in claims 1, and 4-7 would be practiced by the apparatus as in claims 14, and 17-20 respectively as configured. The claim 14, and 17-20 analysis applies equally to claim 1, and 4-7 respectively.
Deferring of Indication of Allowable Subject Matter
Due to the 35 U.S.C 101 rejections, as well as the 35 U.S.C. 112(b) rejections made, regarding claims 2-3, 8-13, and 15-16, rendering the Examiner unable to reasonably discern many of the limitations claimed, the Examiner is deferring decision, regarding 2-3, 8-13, and 15-16, as to prior art and/or indication of allowable subject matter over prior art pending resolution of the 35 U.S.C. 112(b), and 101 rejections made.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Pelofske, E., Hahn, G. & Djidjev, H.N. Parallel quantum annealing. Sci Rep 12, 4499 ( March 2022). doi.org/10.1038/s41598-022-08394-8
Discusses quantum annealing, and embedding for an optimization problem. Furthermore, discusses computing full clique embeddings and saving them for re-use later. (page 4, paragraph 4)
Seemingly does not explicitly teach many of the specific details of storing/accessing stored embeddings
Date, P., Patton, R., Schuman, C. et al. Efficiently embedding QUBO problems on adiabatic quantum computers. Quantum Inf Process 18, 117 (2019). doi.org/10.1007/s11128-019-2236-3
Discusses solving a QUBO problem, as well as precomputing mappings of embeddings, storing the mappings as a hash map, and looking up the embeddings in the hash map. (page 19 of 31)
Seemingly does not explicitly teach features regarding a specific or particular quantum processor
Thom et al. (U.S. Patent Application Publication 2022/0391081 A1)
Discusses a graph of a problem may be stored ([0080])
Discusses an embedding on a target graph of a representation of a problem stored in a data structure ([0081])
Discusses different instances of a QUBO problem, different embeddings for the different instances, and different representations of a QUBO problem, all of which may be stored on a data structure (Fig. 3)
Discusses accessing a representation of an instance of a solution to a problem ([0181])
Seemingly does not explicitly teach many of the specific details of storing/accessing stored embeddings
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME ANTHONY KLOSTERMAN II whose telephone number is (571)272-0541. The examiner can normally be reached Monday - Friday 8:30am - 3:30pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at 571-272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/Primary Examiner, Art Unit 2182 /EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
Prosecution Insights