DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed July 22, 2026. Claims 1, 4, 11-12, 15, and 22-24 have been amended. No claims have been added. Claims 19-20 have been canceled. Currently, claims 1-18, and 22-24 are pending.
Applicant’s amendments to claim 12 overcome the 112(b) rejection outlined in the previous Office Action. The 112(b) rejection of claims 12-20, and 22-24 is withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 20: “electrode is vertically overlaps” should read -- electrode vertically overlaps”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 20230397403 A1) in view of Oh et al. (US 20160300886 A1) herein after “Oh”.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Figs. 1A-1C of Cho disclose a semiconductor device (Fig. 1A, memory cell MC, ¶ [0026]), comprising:
a vertical conductive line (Fig. 1A, vertical conductive line BL, ¶ [0026]) oriented in a first direction which is vertical to a substrate;
a data storage element (Fig. 1A, data storage element CAP, ¶ [0026]) spaced horizontally from the vertical conductive line (BL);
a horizontal layer (Fig. 1A, lateral layer ACT, ¶ [0026]) oriented in a second direction which is horizontal to the substrate from the vertical conductive line (BL) and between the vertical conductive line (BL) and the data storage element (CAP); and
a horizontal conductive line (Fig. 1A, lateral conductive line DWL, ¶ [0026]) oriented horizontally in a third direction intersecting with the horizontal layer (ACT), wherein the horizontal conductive line (DWL) includes:
a high work function electrode (Fig. 1C, first work function electrode G1, ¶ [0037]) including a material having a higher work function than titanium nitride (“the high work function material may have a work function which is higher than approximately 4.5 eV”, ¶ [0038]); and
a low work function electrode (Fig. 1C, third work function electrode G3, ¶ [0037]) including a semiconductor material (“the second and third work function electrodes G2 and G3 may include a semiconductor material”, ¶ [0038]),
wherein the high work function electrode (G1) and the low work function electrode (G3) are arranged in parallel at a same level along the second direction (D2), and
wherein the low work function electrode (G3) is adjacent to the data storage element (CAP) coupled to a first doped region (Fig. 1B, second doped region DR, ¶ [0033]) of the horizontal layer (ACT),
wherein the high work function electrode (G1) is adjacent to the vertical conductive line (BL) wherein a width of the high work function electrode (G1) is greater than a width of the low work function electrode (G3).
Cho fails to disclose wherein the low work function electrode is vertically overlaps only with the first doped region.
In the similar field of endeavor of transistor devices, Fig. 11 of Oh discloses wherein the low work function electrode (Fig. 11, second gate 130b, “The second gate 130b may include a material having a second work function less than the first work function”, ¶ [0060-0061]) is vertically overlaps only with the first doped region (Fig. 11, drain D, ¶ [0044]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Cho with the electrode arrangement as disclosed by Oh, to obtain the desired electric field (see Oh, ¶ [0061]).
Regarding claim 2, Cho and Oh together disclose the semiconductor device of claim 1 as applied above, and Figs. 1A-1C of Cho further disclose wherein the low work function electrode (G3) has a lower work function than the high work function electrode (G1) (“The first work function electrode G1 may have a higher work function than the second and third work function electrodes G2 and G3”, ¶ [0038]).
Regarding claim 3, Cho and Oh together disclose the semiconductor device of claim 1 as applied above, and Figs. 1A-1C of Cho further disclose wherein the high work function electrode (G1) includes a molybdenum-based material (“the first work function electrode G1 may include a stack in which a metal nitride liner G1L and a metal bulk layer G1B…, the metal nitride liner GIL may include… molybdenum nitride. The metal bulk layer G1B may include… molybdenum”, ¶ [0042]).
Regarding claim 4, Cho and Oh together disclose the semiconductor device of claim 1 as applied above, and Figs. 1A-1C of Cho further disclose wherein the high work function electrode (G1) includes:
a first molybdenum-based electrode (Fig. 1C, metal bulk layer G1B, ¶ [0042]) (“The metal bulk layer G1B may include… molybdenum”, ¶ [0042]; and
a second molybdenum-based electrode (Fig. 1C, metal nitride liner G1L, ¶ [0042]) (“the metal nitride liner GIL may include… molybdenum nitride”, ¶ [0042]) disposed between the first molybdenum-based electrode (G1B) and the horizontal layer (ACT), and
wherein the first molybdenum-based electrode (G1B) and the second molybdenum-based electrode (G1L) are different.
Regarding claim 5, Cho and Oh together disclose the semiconductor device of claim 1 as applied above, and Figs. 1A-1C of Cho further disclose wherein the high work function electrode (G1) includes:
a molybdenum bulk electrode (G1B) (“The metal bulk layer G1B may include… molybdenum”, ¶ [0042]; and
a molybdenum nitride liner electrode (G1L) (“the metal nitride liner GIL may include… molybdenum nitride”, ¶ [0042]) disposed between the molybdenum bulk electrode (G1B) and the horizontal layer (ACT).
Regarding claim 6, Figs. 1A-1C of Cho disclose the semiconductor device of claim 5 as applied above, and Figs. 1A-1C of Cho further disclose wherein the molybdenum nitride liner (G1L) electrode partially surrounds the molybdenum bulk electrode (G1B).
Regarding claim 7, Cho and Oh together disclose the semiconductor device of claim 1 as applied above, and Figs. 1A-1C of Cho further disclose wherein the low work function electrode (G3) includes doped polysilicon (“G3 may include doped polysilicon”, ¶ [0039]).
Regarding claim 8, Cho and Oh together disclose the semiconductor device of claim 1 as applied above, and Figs. 1A-1C of Cho further disclose wherein the high work function electrode (G1) and the low work function electrode (G3) are oriented horizontally in the third direction.
Regarding claim 11, Cho and Oh together disclose the semiconductor device of claim 1 as applied above, and Figs. 1A-1C of Cho further disclose wherein the vertical conductive line (BL) coupled to a second doped region (Fig. 1B, first doped region SR, ¶ [0033]) of the horizontal layer (ACT).
Claims 12-18, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 20230397403 A1) in view of Lee et al. (US 20230063527 A1) herein after “Lee”.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 12, Figs. 1A-1C of Cho disclose a semiconductor device (MC), comprising:
a vertical conductive line (BL) oriented in a first direction which is vertical to a substrate;
a data storage element (CAP) spaced horizontally from the vertical conductive line (BL);
a horizontal layer (ACT) oriented in a second direction which is horizontal to the substrate from the vertical conductive line (BL) and between the vertical conductive line (BL) and the data storage element (CAP); and
a horizontal conductive line (DWL) oriented horizontally in a third direction intersecting with the horizontal layer (ACT), wherein the horizontal conductive line (DWL) includes:
a high work function electrode (G1) including a molybdenum-based material (“the first work function electrode G1 may include a stack in which a metal nitride liner G1L and a metal bulk layer G1B…, the metal nitride liner GIL may include… molybdenum nitride. The metal bulk layer G1B may include… molybdenum”, ¶ [0042]);
a first low work function electrode (Fig. 1B, second work function electrode G2, ¶ [0037]) disposed on a first side of the high work function electrode (G1); and
a second low work function electrode (G3) disposed on a second side of the high work function electrode (G1),
wherein the high work function electrode (G1) and the first (G2) and second low work function electrodes (G3) are arranged in parallel at a same level along the second direction, and
wherein the high work function electrode (G1) and the first and second low work function electrodes (G3) are formed to have a same thickness at the first direction,
wherein the first low work function electrode (G2) is adjacent to the data storage element (CAP), wherein the second low work function electrode (G3) is adjacent to the vertical conductive line (BL),
wherein the horizontal conductive line (DWL) further includes:
the high work function electrode (G1) and the first low work function electrode (G2) vertically overlapped with a first doped region (SR) of the horizontal layer (ACT),
wherein the first doped region (SR) is coupled to the vertical conductive line (BL).
Cho fails to disclose a capping electrode including molybdenum nitride disposed between the high work function electrode and the first low work function electrode.
In the similar field of endeavor of memory devices, Fig. 7 of Lee discloses a capping electrode (Fig. 7, first gate barrier pattern 155, ¶ [0034]) including molybdenum nitride (“the first gate barrier layer 150 may include a metal nitride, e.g.…, molybdenum nitride”, “an upper portion of the first gate barrier layer 150 may be removed by, e.g., an etch back process so that a first gate barrier pattern 155 having a flat upper surface may be formed”, ¶ [0031] and [0034]) disposed between the high work function electrode (Fig. 7, first gate electrode 145, ¶ [0027]) and the first low work function electrode (Fig. 7, second gate electrode 175, ¶ [0035]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Cho with the capping layer as disclosed by Lee, to prevent diffusion between the electrodes (see Lee, ¶ [0016]).
Regarding claim 13, Cho and Lee together disclose the semiconductor device of claim 12 as applied above, and Figs. 1A-1C of Cho further disclose wherein the first (G3) and second low work function electrodes (G2) have a lower work function than the high work function electrode (G1) (“The first work function electrode G1 may have a higher work function than the second and third work function electrodes G2 and G3”, ¶ [0038]).
Regarding claim 14, Cho and Lee together disclose the semiconductor device of claim 12 as applied above, and Figs. 1A-1C of Cho further disclose wherein the high work function electrode (G1) includes:
a first molybdenum-based electrode (G1B) (“The metal bulk layer G1B may include… molybdenum”, ¶ [0042]; and
a second molybdenum-based electrode (G1L) (“the metal nitride liner GIL may include… molybdenum nitride”, ¶ [0042]) disposed between the first molybdenum-based electrode (G1B) and the horizontal layer (ACT), wherein the first molybdenum-based electrode (G1B) and the second molybdenum-based electrode (G1L) are different.
Regarding claim 15, Cho and Lee together disclose the semiconductor device of claim 12 as applied above, and Figs. 1A-1C of Cho further disclose wherein the high work function electrode (G1) includes:
a molybdenum bulk electrode (G1B); and
wherein a molybdenum nitride liner (G1L) electrode disposed between the molybdenum bulk electrode (G1B) and the horizontal layer (ACT).
Regarding claim 16, Cho and Lee together disclose the semiconductor device of claim 15 as applied above, and Figs. 1A-1C of Cho further disclose wherein the molybdenum nitride liner (G1L) electrode partially surrounds the molybdenum bulk electrode (G1B).
Regarding claim 17, Cho and Lee together disclose the semiconductor device of claim 12 as applied above, and Figs. 1A-1C of Cho further disclose wherein the first (G3) and second low work function electrodes (G2) include doped polysilicon (“G2 and G3 may include doped polysilicon”, ¶ [0039]).
Regarding claim 18, Cho and Lee together disclose the semiconductor device of claim 12 as applied above, and Figs. 1A-1C of Cho further disclose wherein the first low work function electrode (G2), the high work function electrode (G1), and the second low work function electrode (G3) are oriented horizontally in the third direction.
Regarding claim 22, Cho and Lee together disclose the semiconductor device of claim 12 as applied above, and Figs. 1A-1C of Cho further disclose wherein the horizontal layer (ACT) further includes;
a second doped region (DR), and
a channel (CH) between the first doped region (SR) and the second doped region (DR).
Regarding claim 23, Cho and Lee together disclose the semiconductor device of claim 12 as applied above, and Figs. 1A-1C of Cho further disclose wherein the channel (CH) and the high work function electrode (G1) vertically overlap with each other, and
the second low work function electrode (G3) vertically overlaps with the second doped region (DR).
Regarding claim 24, Cho and Lee together disclose the semiconductor device of claim 22 as applied above, and Figs. 1A-1C of Cho further disclose wherein the data storage element (CAP) coupled to the second doped region (DR).
Claims 1, 7-9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20220173106 A1) herein after “Choi” in view of Oh (US 20160300886 A1).
Regarding claim 1, Figs. 16B and 17B of Choi disclose a semiconductor device (Fig. 17B, semiconductor memory device 1b, ¶ [0101]), comprising:
a vertical conductive line (Fig. 16B, bit lines 194, ¶ [0071]) oriented in a first direction which is vertical to a substrate (Fig. 16B, substrate 102, ¶ [0017]);
a data storage element (Fig. 17B, cell capacitor 200, ¶ [0082]) spaced horizontally from the vertical conductive line (194);
a horizontal layer (Fig. 17B, transistor body parts 120BD, ¶ [0088]) oriented in a second direction which is horizontal to the substrate (102) from the vertical conductive line (194) and between the vertical conductive line (194) and the data storage element (200); and
a horizontal conductive line (Fig. 17B, gate electrode layer 184a, ¶ [0101]) oriented horizontally in a third direction intersecting with the horizontal layer (120BD), wherein the horizontal conductive line (184a) includes:
a high work function electrode (Fig. 17B, gate body layer 186a, ¶ [0101]) including a material having a higher work function than titanium nitride (“the gate body layer 186a may include Ru, RuO, Pt, PtO…”, ¶ [0102]); and
a low work function electrode (Fig. 17B, work function control layer 185a, ¶ [0101]) including a semiconductor material (“the work function control layer 185a may include impurity-doped polysilicon”, ¶ [0102]),
wherein the high work function electrode (186a) and the low work function electrode (185a) are arranged in parallel at a same level along the second direction (D1), and
wherein the low work function electrode (185a) is adjacent to the data storage element (200) coupled to a first doped region (Fig. 17B, second source-drain regions 126, ¶ [0078]) of the horizontal layer (120BD),
wherein the high work function electrode (186a) is adjacent to the vertical conductive line (194) wherein a width of the high work function electrode (186a) is greater than a width of the low work function electrode (185a).
Choi fails to disclose wherein the low work function electrode is vertically overlaps only with the first doped region.
In the similar field of endeavor of transistor devices, Fig. 11 of Oh discloses wherein the low work function electrode (130b) is vertically overlaps only with the first doped region (D).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Choi with the electrode arrangement as disclosed by Oh, to obtain the desired electric field (see Oh, ¶ [0061]).
Regarding claim 7, Choi and Oh disclose the semiconductor device of claim 1 as applied above, and Fig. 17B of Choi further discloses wherein the low work function electrode (185a) includes doped polysilicon (“the work function control layer 185a may include impurity-doped polysilicon”, ¶ [0102]).
Regarding claim 8, Choi and Oh disclose the semiconductor device of claim 1 as applied above, and Fig. 17B of Choi further discloses wherein the high work function electrode (186a) and the low work function electrode (185a) are oriented horizontally in the third direction (D3).
Regarding claim 9, Choi and Oh disclose the semiconductor device of claim 1 as applied above, and Fig. 17B of Choi further discloses wherein the horizontal conductive line (184a) further includes a capping electrode (Fig. 17B, spacer capping layers 192, ¶ [0069]) in contact with the high work function electrode (186a).
Regarding claim 11, Choi and Oh disclose the semiconductor device of claim 1 as applied above, and Fig. 16B of Choi further discloses wherein the vertical conductive line (194) coupled to a second doped region (Fig. 16B, source-drain regions 122, ¶ [0078]) of the horizontal layer (120BD).
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20220173106 A1) and Oh (US 20160300886 A1) in further view of Kang et al. (US 20200176451 A1) herein after “Kang”.
Regarding claim 2, Choi and Oh disclose the semiconductor device of claim 1 as applied above, but Choi fails to explicitly disclose wherein the low work function electrode has a lower work function than the high work function electrode.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses wherein the low work function electrode (Fig. 9, second work-function metal layer 116, ¶ [0043]) has a lower work function than the high work function electrode (Fig. 9, first work-functional metal layer 112, buried word line 115, ¶ [0031] and [0041]) (“the second work-function metal layer 116 has a work-function that is less than the work-function of the first work-function layer”, ¶ [0044]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to reduce resistance and drain leakage (see Kang, ¶ [0023]).
Regarding claim 3, Choi and Oh disclose the semiconductor device of claim 1 as applied above, but Choi fails to explicitly disclose wherein the high work function electrode includes a molybdenum-based material.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses wherein the high work function electrode (112, 115) includes a molybdenum-based material (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, “the buried word line 115… molybdenum (Mo)”, ¶ [0039] and [0042]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to obtain the desired work function (see Kang, ¶ [0037]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 4, Choi and Oh disclose the semiconductor device of claim 1 as applied above, but Choi fails to explicitly disclose wherein the high work function electrode includes:
a first molybdenum-based electrode; and
a second molybdenum-based electrode disposed between the first molybdenum-based electrode and the horizontal layer, and
the first molybdenum-based electrode and the second molybdenum-based electrode are different.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses wherein the high work function electrode (112, 115) includes:
a first molybdenum-based electrode (115) (“the buried word line 115 (i.e. the recessed bulk metal layer 115) comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo)”, ¶ [0042]); and
a second molybdenum-based electrode (112) (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, ¶ [0039]), electrode disposed between the molybdenum bulk electrode (115) and the horizontal layer (HL) disposed between the first molybdenum-based electrode (115) and the horizontal layer (HL), and
wherein the first molybdenum-based electrode (115) and the second molybdenum-based electrode (112) are different.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the second electrode as disclosed by Kang, to reduce resistance and drain leakage (see Kang, ¶ [0023]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 5, Choi and Oh disclose the semiconductor device of claim 1 as applied above, and Fig. 17B of Choi further discloses wherein the high work function electrode (186a) includes:
a bulk electrode (186a); and
a nitride liner (182) electrode disposed between the molybdenum bulk electrode (186a) and the horizontal layer (120BD).
Choi fails to disclose that the bulk electrode and nitride liner are molybdenum.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses the bulk electrode (115) (“the buried word line 115 (i.e. the recessed bulk metal layer 115) comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo)”, ¶ [0042]) and nitride liner (112) (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, ¶ [0039]) are molybdenum.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to obtain the desired work function (see Kang, ¶ [0037]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 6, Choi, Oh and Kang together disclose the semiconductor device of claim 5 as applied above, and Fig. 17B of Choi further discloses wherein the nitride liner (182) electrode partially surrounds the bulk electrode (186a).
Choi fails to disclose that the bulk electrode and nitride liner are molybdenum.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses the bulk electrode (115) (“the buried word line 115 (i.e. the recessed bulk metal layer 115) comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo)”, ¶ [0042]) and nitride liner (112) (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, ¶ [0039]) are molybdenum.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to obtain the desired work function (see Kang, ¶ [0037]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20220173106 A1) and Oh (US 20160300886 A1) in further view of Song et al. (US 20230402523 A1) herein after “Song”.
Regarding claim 10, Choi and Oh together disclose semiconductor device of claim 9 as applied above, but the combination fails to disclose wherein the capping electrode includes molybdenum nitride.
In the similar field of endeavor of semiconductor devices, Fig. 6A of Song discloses wherein the capping electrode (Fig. 6A, capping pattern CAM, ¶ [0100]) includes molybdenum nitride (Fig. 6A, “The capping pattern CAM may include a metal nitride layer. The capping pattern CAM may be formed of or include at least one metal, which is selected from the group consisting of… molybdenum (Mo)”, ¶ [0109]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Choi with the capping layer disclosed by Song, to separate the metal patterns (see Song, ¶ [0101]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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