DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 15, 2025 has been entered.
Response to Amendment
This Office Action is in response to Applicant's amendments filed December 15, 2025. Claims 1, 11-12, and 24 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-20, and 22-24 are pending.
Applicant’s amendments to claim 12 do not overcome the 112(b) rejection outlined in the previous Office Action. The 112(b) rejection of claims 12-20, and 22-24 is maintained and presented in full below.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-20, and 22-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, the recites the limitation "the low work function electrode" in line 17. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite whether the low work function electrode of claim 12, line 17 refers to the first low work function electrode of claim 12, line 11 or the second low work function electrode of claim 12, line 13. For the purposes of examination the former interpretation will be used.
Claims 13-20, and 22-24 depend upon claim 12 and do not rectify the problem. Therefore, they are rejected on at least the same basis as claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11-18, and 22-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cho (US 20230397403 A1).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Figs. 1A-1C of Cho disclose a semiconductor device (Fig. 1A, memory cell MC, ¶ [0026]), comprising:
a vertical conductive line (Fig. 1A, vertical conductive line BL, ¶ [0026]) oriented in a first direction which is vertical to a substrate;
a data storage element (Fig. 1A, data storage element CAP, ¶ [0026]) spaced horizontally from the vertical conductive line (BL);
a horizontal layer (Fig. 1A, lateral layer ACT, ¶ [0026]) oriented in a second direction which is horizontal to the substrate from the vertical conductive line (BL) and between the vertical conductive line (BL) and the data storage element (CAP); and
a horizontal conductive line (Fig. 1A, lateral conductive line DWL, ¶ [0026]) oriented horizontally in a third direction intersecting with the horizontal layer (ACT), wherein the horizontal conductive line (DWL) includes:
a high work function electrode (Fig. 1C, first work function electrode G1, ¶ [0037]) including a material having a higher work function than titanium nitride (“the high work function material may have a work function which is higher than approximately 4.5 eV”, ¶ [0038]); and
a low work function electrode (Fig. 1C, third work function electrode G3, ¶ [0037]) including a semiconductor material (“the second and third work function electrodes G2 and G3 may include a semiconductor material”, ¶ [0038]),
wherein the high work function electrode (G1) and the low work function electrode (G3) are arranged in parallel at a same level along the second direction (D2), and
wherein the low work function electrode (G3) is adjacent to the data storage element (CAP),
wherein the high work function electrode (G1) is adjacent to the vertical conductive line (BL) wherein a width of the high work function electrode (G1) is greater than a width of the low work function electrode (G3).
Regarding claim 2, Figs. 1A-1C of Cho disclose the semiconductor device of claim 1 as applied above, and further disclose wherein the low work function electrode (G3) has a lower work function than the high work function electrode (G1) (“The first work function electrode G1 may have a higher work function than the second and third work function electrodes G2 and G3”, ¶ [0038]).
Regarding claim 3, Figs. 1A-1C of Cho disclose the semiconductor device of claim 1 as applied above, and further disclose wherein the high work function electrode (G1) includes a molybdenum-based material (“the first work function electrode G1 may include a stack in which a metal nitride liner G1L and a metal bulk layer G1B…, the metal nitride liner GIL may include… molybdenum nitride. The metal bulk layer G1B may include… molybdenum”, ¶ [0042]).
Regarding claim 4, Figs. 1A-1C of Cho disclose the semiconductor device of claim 1 as applied above, and further disclose wherein the high work function electrode (G1) includes:
a first molybdenum-based electrode (Fig. 1C, metal bulk layer G1B, ¶ [0042]) (“The metal bulk layer G1B may include… molybdenum”, ¶ [0042]; and
a second molybdenum-based electrode (Fig. 1C, metal nitride liner G1L, ¶ [0042]) (“the metal nitride liner GIL may include… molybdenum nitride”, ¶ [0042]) disposed between the first molybdenum-based electrode (G1B) and the horizontal layer (ACT), and
the first molybdenum-based electrode (G1B) and the second molybdenum-based electrode (G1L) are different.
Regarding claim 5, Figs. 1A-1C of Cho disclose the semiconductor device of claim 1 as applied above, and further disclose wherein the high work function electrode (G1) includes:
a molybdenum bulk electrode (G1B) (“The metal bulk layer G1B may include… molybdenum”, ¶ [0042]; and
a molybdenum nitride liner electrode (G1L) (“the metal nitride liner GIL may include… molybdenum nitride”, ¶ [0042]) disposed between the molybdenum bulk electrode (G1B) and the horizontal layer (ACT).
Regarding claim 6, Figs. 1A-1C of Cho disclose the semiconductor device of claim 5 as applied above, and further disclose wherein the molybdenum nitride liner (G1L) electrode partially surrounds the molybdenum bulk electrode (G1B).
Regarding claim 7, Figs. 1A-1C of Cho disclose the semiconductor device of claim 1 as applied above, and further disclose wherein the low work function electrode (G3) includes doped polysilicon (“G3 may include doped polysilicon”, ¶ [0039]).
Regarding claim 8, Figs. 1A-1C of Cho disclose the semiconductor device of claim 1 as applied above, and further disclose wherein the high work function electrode (G1) and the low work function electrode (G3) are oriented horizontally in the third direction.
Regarding claim 11, Figs. 1A-1C of Cho disclose the semiconductor device of claim 1 as applied above, and further disclose wherein the vertical conductive line (BL) coupled to a first-side end of the horizontal layer (ACT); and
wherein the data storage element (CAP) coupled to a second-side end of the horizontal layer (ACT).
Regarding claim 12, Figs. 1A-1C of Cho disclose a semiconductor device (MC), comprising:
a vertical conductive line (BL) oriented in a first direction which is vertical to a substrate;
a data storage element (CAP) spaced horizontally from the vertical conductive line (BL);
a horizontal layer (ACT) oriented in a second direction which is horizontal to the substrate from the vertical conductive line (BL) and between the vertical conductive line (BL) and the data storage element (CAP); and
a horizontal conductive line (DWL) oriented horizontally in a third direction intersecting with the horizontal layer (ACT), wherein the horizontal conductive line (DWL) includes:
a high work function electrode (G1) including a molybdenum-based material (“the first work function electrode G1 may include a stack in which a metal nitride liner G1L and a metal bulk layer G1B…, the metal nitride liner GIL may include… molybdenum nitride. The metal bulk layer G1B may include… molybdenum”, ¶ [0042]);
a first low work function electrode (G2) disposed on a first side of the high work function electrode (G1); and
a second low work function electrode (G3) disposed on a second side of the high work function electrode (G1),
wherein the high work function electrode (G1) and the first and second low work function electrode (G3) are arranged in parallel at a same level along the second direction, and
wherein the high work function electrode (G1) and the low work function electrode (G3) are formed to have a same thickness at the first direction,
wherein the first low work function electrode (G2) is adjacent to the data storage element (CAP), wherein the second low work function electrode (G3) is adjacent to the vertical conductive line (BL).
Regarding claim 13, Figs. 1A-1C of Cho disclose the semiconductor device of claim 12 as applied above, and further disclose wherein the first (G3) and second low work function electrodes (G2) have a lower work function than the high work function electrode (G1) (“The first work function electrode G1 may have a higher work function than the second and third work function electrodes G2 and G3”, ¶ [0038]).
Regarding claim 14, Figs. 1A-1C of Cho disclose the semiconductor device of claim 12 as applied above, and further disclose wherein the high work function electrode (G1) includes:
a first molybdenum-based electrode (G1B) (“The metal bulk layer G1B may include… molybdenum”, ¶ [0042]; and
a second molybdenum-based electrode (G1L) (“the metal nitride liner GIL may include… molybdenum nitride”, ¶ [0042]) disposed between the first molybdenum-based electrode (G1B) and the horizontal layer (ACT), wherein the first molybdenum-based electrode (G1B) and the second molybdenum-based electrode (G1L) are different.
Regarding claim 15, Figs. 1A-1C of Cho disclose the semiconductor device of claim 12 as applied above, and further disclose wherein the high work function electrode (G1) includes:
a molybdenum bulk electrode (G1B); and
a molybdenum nitride liner (G1L) electrode disposed between the molybdenum bulk electrode (G1B) and the horizontal layer (ACT).
Regarding claim 16, Figs. 1A-1C of Cho disclose the semiconductor device of claim 15 as applied above, and further disclose wherein the molybdenum nitride liner (G1L) electrode partially surrounds the molybdenum bulk electrode (G1B).
Regarding claim 17, Figs. 1A-1C of Cho disclose the semiconductor device of claim 12 as applied above, and further disclose wherein the first (G3) and second low work function electrodes (G2) include doped polysilicon (“G2 and G3 may include doped polysilicon”, ¶ [0039]).
Regarding claim 18, Figs. 1A-1C of Cho disclose the semiconductor device of claim 12 as applied above, and further disclose wherein the first low work function electrode (G2), the high work function electrode (G1), and the second low work function electrode (G3) are oriented horizontally in the third direction.
Regarding claim 22, Figs. 1A-1C of Cho disclose the semiconductor device of claim 12 as applied above, and further disclose wherein the horizontal layer (ACT) includes a first doped region (SR), a second doped region (DR), and
a channel (CH) between the first doped region (SR) and the second doped region (DR).
Regarding claim 23, Figs. 1A-1C of Cho disclose the semiconductor device of claim 12 as applied above, and further disclose wherein the channel (CH) and the high work function electrode (G1) vertically overlap with each other, and
the first low work function electrode (G2) vertically overlaps with the first doped region (SR), and
the second low work function electrode (G3) vertically overlaps with the second doped region (DR).
Regarding claim 24, Figs. 1A-1C of Cho disclose the semiconductor device of claim 22 as applied above, and further disclose wherein the a vertical conductive line (BL) coupled to the first doped region (SR);
wherein the data storage element (CAP) coupled to the second doped region (DR).
Claims 1, 7-9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 20220173106 A1) herein after “Choi”.
Regarding claim 1, Figs. 16B and 17B of Choi disclose a semiconductor device (Fig. 17B, semiconductor memory device 1b, ¶ [0101]), comprising:
a vertical conductive line (Fig. 16B, bit lines 194, ¶ [0071]) oriented in a first direction which is vertical to a substrate (Fig. 16B, substrate 102, ¶ [0017]);
a data storage element (Fig. 17B, cell capacitor 200, ¶ [0082]) spaced horizontally from the vertical conductive line (194);
a horizontal layer (Fig. 17B, transistor body parts 120BD, ¶ [0088]) oriented in a second direction which is horizontal to the substrate (102) from the vertical conductive line (194) and between the vertical conductive line (194) and the data storage element (200); and
a horizontal conductive line (Fig. 17B, gate electrode layer 184a, ¶ [0101]) oriented horizontally in a third direction intersecting with the horizontal layer (120BD), wherein the horizontal conductive line (184a) includes:
a high work function electrode (Fig. 17B, gate body layer 186a, ¶ [0101]) including a material having a higher work function than titanium nitride (“the gate body layer 186a may include Ru, RuO, Pt, PtO…”, ¶ [0102]); and
a low work function electrode (Fig. 17B, work function control layer 185a, ¶ [0101]) including a semiconductor material (“the work function control layer 185a may include impurity-doped polysilicon”, ¶ [0102]),
wherein the high work function electrode (186a) and the low work function electrode (185a) are arranged in parallel at a same level along the second direction (D1), and
wherein the low work function electrode (185a) is adjacent to the data storage element (200),
wherein the high work function electrode (186a) is adjacent to the vertical conductive line (194) wherein a width of the high work function electrode (186a) is greater than a width of the low work function electrode (185a).
Regarding claim 7, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, and Fig. 17B further discloses wherein the low work function electrode (185a) includes doped polysilicon (“the work function control layer 185a may include impurity-doped polysilicon”, ¶ [0102]).
Regarding claim 8, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, and Fig. 17B further discloses wherein the high work function electrode (186a) and the low work function electrode (185a) are oriented horizontally in the third direction (D3).
Regarding claim 9, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, and Fig. 17B further discloses wherein the horizontal conductive line (184a) further includes a capping electrode (Fig. 17B, spacer capping layers 192, ¶ [0069]) in contact with the high work function electrode (186a).
Regarding claim 11, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, and Fig. 16B further discloses wherein the vertical conductive line (194) coupled to a first-side end (Fig. 16B, source-drain regions 122, ¶ [0078]) of the horizontal layer (120BD); and
wherein the data storage element (200) coupled to a second-side end (Fig. 16B, source-drain region 126, ¶ [0078]) of the horizontal layer (120BD).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20220173106 A1) in view of Kang et al. (US 20200176451 A1) herein after “Kang”.
Regarding claim 2, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, but Choi fails to explicitly disclose wherein the low work function electrode has a lower work function than the high work function electrode.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses wherein the low work function electrode (Fig. 9, second work-function metal layer 116, ¶ [0043]) has a lower work function than the high work function electrode (Fig. 9, first work-functional metal layer 112, buried word line 115, ¶ [0031] and [0041]) (“the second work-function metal layer 116 has a work-function that is less than the work-function of the first work-function layer”, ¶ [0044]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to reduce resistance and drain leakage (see Kang, ¶ [0023]).
Regarding claim 3, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, but Choi fails to explicitly disclose wherein the high work function electrode includes a molybdenum-based material.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses wherein the high work function electrode (112, 115) includes a molybdenum-based material (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, “the buried word line 115… molybdenum (Mo)”, ¶ [0039] and [0042]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to obtain the desired work function (see Kang, ¶ [0037]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 4, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, but Choi fails to explicitly disclose wherein the high work function electrode includes:
a first molybdenum-based electrode; and
a second molybdenum-based electrode disposed between the first molybdenum-based electrode and the horizontal layer, and
the first molybdenum-based electrode and the second molybdenum-based electrode are different.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses wherein the high work function electrode (112, 115) includes:
a first molybdenum-based electrode (115) (“the buried word line 115 (i.e. the recessed bulk metal layer 115) comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo)”, ¶ [0042]); and
a second molybdenum-based electrode (112) (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, ¶ [0039]), electrode disposed between the molybdenum bulk electrode (115) and the horizontal layer (HL) disposed between the first molybdenum-based electrode (115) and the horizontal layer (HL), and
the first molybdenum-based electrode (115) and the second molybdenum-based electrode (112) are different.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the second electrode as disclosed by Kang, to reduce resistance and drain leakage (see Kang, ¶ [0023]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 5, Figs. 16B and 17B of Choi disclose semiconductor device of claim 1 as applied above, and Fig. 17B of Choi further discloses wherein the high work function electrode (186a) includes:
a bulk electrode (186a); and
a nitride liner (182) electrode disposed between the molybdenum bulk electrode (186a) and the horizontal layer (120BD).
Choi fails to disclose that the bulk electrode and nitride liner are molybdenum.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses the bulk electrode (115) (“the buried word line 115 (i.e. the recessed bulk metal layer 115) comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo)”, ¶ [0042]) and nitride liner (112) (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, ¶ [0039]) are molybdenum.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to obtain the desired work function (see Kang, ¶ [0037]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 6, Choi and Kang together disclose the semiconductor device of claim 5 as applied above, and Fig. 17B of Choi further discloses wherein the nitride liner (182) electrode partially surrounds the bulk electrode (186a).
Choi fails to disclose that the bulk electrode and nitride liner are molybdenum.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses the bulk electrode (115) (“the buried word line 115 (i.e. the recessed bulk metal layer 115) comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo)”, ¶ [0042]) and nitride liner (112) (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, ¶ [0039]) are molybdenum.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to obtain the desired work function (see Kang, ¶ [0037]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20220173106 A1) in view of Song et al. (US 20230402523 A1) herein after “Song”.
Regarding claim 10, Fig. 17B of Choi disclose semiconductor device of claim 9 as applied above, but Choi fails to disclose wherein the capping electrode includes molybdenum nitride.
In the similar field of endeavor of semiconductor devices, Fig. 6A of Song discloses wherein the capping electrode (Fig. 6A, capping pattern CAM, ¶ [0100]) includes molybdenum nitride (Fig. 6A, “The capping pattern CAM may include a metal nitride layer. The capping pattern CAM may be formed of or include at least one metal, which is selected from the group consisting of… molybdenum (Mo)”, ¶ [0109]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Kang810 with the capping layer disclosed by Song, to separate the metal patterns (see Song, ¶ [0101]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 12-18, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20220173106 A1) in view of Kang (US 20200176451 A1), Jang et al. (US 20180174845 A1) herein after “Jang” and Lee et al. (US 20220375941 A1) herein after “Lee”.
Regarding claim 12, Figs. 16B and 17B of Choi disclose a semiconductor device (1b), comprising:
a vertical conductive line (194) oriented in a first direction which is vertical to a substrate (102);
a data storage element (200) spaced horizontally from the vertical conductive line (194);
a horizontal layer (120BD) oriented in a second direction which is horizontal to the substrate (102) from the vertical conductive line (194) and between the vertical conductive line (194) and the data storage element (200); and
a horizontal conductive line (184a) oriented horizontally in a third direction intersecting with the horizontal layer (120BD), wherein the horizontal conductive line (184a) includes:
a high work function electrode (186a); and
a first low work function electrode (185a) disposed on a first side of the high work function electrode (186a),
wherein the high work function electrode (186a) and the first low work function electrode (185a) are arranged in parallel at a same level along the second direction, and
wherein the high work function electrode (186a) and the low work function electrode (185a) are formed to have a same thickness at the first direction,
wherein the first low work function electrode (185a) is adjacent to the data storage element (200).
Choi fails to disclose a high work function electrode including a molybdenum-based material;
a second low work function electrode disposed on a second side of the high work function electrode,
wherein the high work function electrode and the second low work function electrodes are arranged in parallel at a same level along the second direction, and
wherein the second low work function electrode is adjacent to the vertical conductive line.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses wherein the high work function electrode (112, 115) including a molybdenum based material (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, “the buried word line 115… molybdenum (Mo)”, ¶ [0039] and [0042]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Kang, to obtain the desired work function (see Kang, ¶ [0037]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Kang fails to disclose a second low work function electrode disposed on a second side of the high work function electrode,
wherein the high work function electrode and the second low work function electrodes are arranged in parallel at a same level along the second direction, and
wherein the second low work function electrode is adjacent to the vertical conductive line.
In the similar field of endeavor of semiconductor devices, Fig. 5A of Jang discloses a second low work function electrode (Fig. 5A, doped low work function layer 107L′, ¶ [0063]) disposed on a second side (portion of 107L’ on the right side of 107H in Fig. 5A) of the high work function electrode (Fig. 5A, gate conductive layer 108, ¶ [0063]), and
wherein the high work function electrode (108) and the second low work function electrodes (107L’) are arranged in parallel at a same level along the second direction (shown in Fig. 5A).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Choi with the low work function electrodes as disclosed by Jang, to control the threshold voltage (see Jang, ¶ [0082]).
Jang fails to disclose wherein the second low work function electrode is adjacent to the vertical conductive line.
In the similar field of endeavor of semiconductor memory devices, Fig. 30 of Lee discloses wherein the second low work function electrode (Fig. 30, first conductive line CDL1, ¶ [0032]) is adjacent to the vertical conductive line (Fig. 30, bit line BL, ¶ [0027]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Lee, to increase device reliability (see Lee, ¶ [0129]).
Regarding claim 13, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 12 as applied above, but Choi, Kang and Lee fail to disclose wherein the first and second low work function electrodes have a lower work function than the high work function electrode.
In the similar field of endeavor of semiconductor devices, Fig. 5A of Jang discloses wherein the first (107L’ left side) and second low work function electrodes (107L’ right side) have a lower work function than the high work function electrode (108) (“The gate conductive layer 108 may include a tungsten (W)”, “the low work function may have a work function lower than approximately 4.5 eV”, ¶ [0075] and [0078]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Choi with the low work function electrodes as disclosed by Jang, to control the threshold voltage (see Jang, ¶ [0082]).
Regarding claim 14, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 12 as applied above, but Choi, Jang and Lee fail to disclose wherein the high work function electrode includes:
a first molybdenum-based electrode; and
a second molybdenum-based electrode disposed between the first molybdenum-based electrode and the horizontal layer,
wherein the first molybdenum-based electrode and the second molybdenum-based electrode are different.
In the similar field of endeavor of memory devices, Figs. 1 and 9 Kang discloses wherein the high work function electrode (112, 115) includes:
a first molybdenum-based electrode (115); and
a second molybdenum-based electrode (112) disposed between the first molybdenum-based electrode (115) and the horizontal layer (Fig. 1, word lines 52a, 52b, ¶ [0021]), wherein the first molybdenum-based electrode (115) and the second molybdenum-based electrode (112) are different (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, “the buried word line 115… molybdenum (Mo)”, ¶ [0039] and [0042]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the second electrode as disclosed by Kang, to reduce resistance and drain leakage (see Kang, ¶ [0023]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 15, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 12 as applied above, and Fig. 17B of Choi further discloses wherein the high work function electrode (186a) includes:
a bulk electrode (186a); and
a nitride liner (Fig. 17B, gate dielectric layer 182, ¶ [0065]) electrode disposed between the molybdenum bulk electrode (186a) and the horizontal layer (120BD).
Choi, Jang and Lee fail to disclose the electrode and nitride liner include molybdenum.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses the electrode (115) and nitride liner (112) include molybdenum (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, “the buried word line 115… molybdenum (Mo)”, ¶ [0039] and [0042]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the second electrode as disclosed by Kang, to reduce resistance and drain leakage (see Kang, ¶ [0023]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 16, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 15 as applied above, and Fig. 17B of Choi further discloses wherein the nitride liner (182) electrode partially surrounds the bulk electrode (186a).
Choi, Jang and Lee fail to disclose the electrode and nitride liner include molybdenum.
In the similar field of endeavor of memory devices, Fig. 9 Kang discloses the electrode (115) and nitride liner (112) include molybdenum (“the first work-function metal layer comprises… molybdenum nitride (MoN)”, “the buried word line 115… molybdenum (Mo)”, ¶ [0039] and [0042]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the second electrode as disclosed by Kang, to reduce resistance and drain leakage (see Kang, ¶ [0023]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 17, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 12 as applied above, but Choi, Kang and Lee fail to disclose wherein the first and second low work function electrodes include doped polysilicon.
In the similar field of endeavor of semiconductor devices, Fig. 5A of Jang discloses wherein the first (107L’) and second low work function electrodes (107L’) include doped polysilicon (Fig. 5A, “The silicon-based low work function layer 107L’ may include a polysilicon”, ¶ [0117], “the work function layer 107 may include… the doped low work function layer 107L′”, ¶ [0079]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Kang810 with the low work function electrodes as disclosed by Jang, to control the threshold voltage (see Jang, ¶ [0082]).
Regarding claim 18, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 12 as applied above, and Fig. 17B of Choi further discloses wherein the first low work function electrode (185a) and the high work function electrode (186a) are oriented horizontally in the third direction.
Choi, Kang and Jang fail to disclose the high work function electrode and the second low work function electrode are oriented horizontally in the third direction.
In the similar field of endeavor of semiconductor memory devices, Fig. 30 of Lee discloses the high work function electrode (GE) and the second low work function electrode (CDL1) are oriented horizontally in the third direction.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the electrodes as disclosed by Lee, to increase device reliability (see Lee, ¶ [0129]).
Regarding claim 22, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 12 as applied above, and Fig. 17B of Choi further discloses wherein the horizontal layer (120BD) includes a first doped region (Fig. 17B, first source-drain regions 122, ¶ [0070]), a second doped region (Fig. 17B, second source-drain regions 126, ¶ [0078]), and
a channel (Fig. 17B, channel layers 124¸¶ [0078]) between the first doped region (122) and the second doped region (126).
Regarding claim 24, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 22 as applied above, and Fig. 17B of Choi further discloses wherein the a vertical conductive line (194) coupled to the first doped region (122);
wherein the data storage element (200) coupled to the second doped region (126).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20220173106 A1), Kang (US 20200176451 A1), Jang (US 20180174845 A1) and Lee (US 20220375941 A1) in further view of Song et al. (US 20230402523 A1) herein after “Song”.
Regarding claim 19, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 12 as applied above, but the combination fails to disclose wherein the horizontal conductive line further includes a capping electrode in contact with the high work function electrode.
In the similar field of endeavor of semiconductor devices, Fig. 6A of Song discloses wherein the horizontal conductive line (Fig. 6A, fin structure FST, ¶ [0098]) further includes a capping electrode (Fig. 6A, capping pattern CAM, ¶ [0101]) in contact with the high work function electrode (Fig. 6A, gate electrode IGEa, ¶ [0093]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Kang810 with the capping layer disclosed by Song, to separate the metal patterns (see Song, ¶ [0101]).
Regarding claim 20, Choi, Kang, Jang, Lee and Song together disclose the semiconductor device of claim 19 as applied above, but Choi, Kang, Jang and Lee fail to disclose wherein the capping electrode includes molybdenum nitride.
In the similar field of endeavor of semiconductor devices, Fig. 6A of Song discloses wherein the capping electrode (CAM) includes molybdenum nitride (Fig. 6A, “The capping pattern CAM may include a metal nitride layer. The capping pattern CAM may be formed of or include at least one metal, which is selected from the group consisting of… molybdenum (Mo)”, ¶ [0109]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Kang810 with the capping layer disclosed by Song, to separate the metal patterns (see Song, ¶ [0101]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20220173106 A1), Kang (US 20200176451 A1), Jang (US 20180174845 A1) and Lee (US 20220375941 A1) in further view of Srinivasan (Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors).
Regarding claim 23, Choi, Kang, Jang and Lee together disclose the semiconductor device of claim 22 as applied above, and Fig. 17B of Choi discloses wherein the channel (124) and the high work function electrode (186a) vertically overlap with each other, but Choi, Kang and Lee fail to disclose the first low work function electrode vertically overlaps with the first doped region, and the low second work function electrode vertically overlaps with the second doped region.
In the similar field of endeavor of semiconductor field effect transistors, Fig. 1(a) of Srinivasan discloses the first side of the electrode (Fig. 1(a), “poly”, section II, line 8) vertically overlaps (Fig. 1(a), LOV, section I, lines 5-6) with the first doped region (see Annotation 2, Fig. 1(a) of Srinivasan, “FR”), and the second side of the electrode (poly) vertically overlaps with the second doped region (see Annotation 2, Fig. 1(a) of Srinivasan, “SR”).
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Annotation 2, Fig. 1(a) of Srinivasan
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device disclosed by Choi with the overlap as disclosed by Srinivasan, to reduce series resistance (see Srinivasan, section V, lines 7-8).
Srinivasan fails to disclose a first low work function electrode disposed on a first side of the electrode; and
a second low work function electrode disposed on a second side of the electrode.
In the similar field of endeavor of semiconductor devices, Fig. 5A of Jang discloses a first low work function electrode (107L’) disposed on a first side of the electrode (107H); and
a second low work function electrode (107L’) disposed on a second side of the electrode (107H).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Choi with the low work function electrodes as disclosed by Jang, to control the threshold voltage (see Jang, ¶ [0082]).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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