DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note: A p–n junction (or NP junction) is the fundamental interface or boundary between two types of semiconductor materials: p-type (positive, filled with holes) and n-type (negative, filled with electrons). It is the basic building block of most modern electronic devices, including diodes, transistors, and solar cells.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by
Voldman (U.S. 2009/0020818), hereafter Voldman.
As to claim 1, Voldman discloses a semiconductor device (100) for shunting
current in a circuit protection configuration, para-0002+, the device (100) as shown in
figure 1 comprising:
a first heavily doped semiconductor region (126, para-0017) having an anode electrical contact and a first doping polarity;
a second heavily doped semiconductor region (129, para-0017) having a cathode electrical contact and a second doping polarity opposite to the first doping polarity, para-0003+;
a third semiconductor region (122) extending between the first and second
heavily doped semiconductor regions (126, 129), the second doped semiconductor region and the third semiconductor region forming a PN junction, see figure 1G; and
a gate (140, para-0014) coupled to the third semiconductor region (122), the gate
(140) controllable between a first mode in which additional space charges are induced
in the third semiconductor region (122) to deplete the third semiconductor region, and a
second mode in which additional space charges are not induced in the third
semiconductor region.
As to claim 2, Voldman discloses the gate is a gate electrode (140) adjacent to
the third semiconductor region (122) and the gate electrode (140) is configured in the
first mode to generate an electric field to exert a potential change in the third
semiconductor region.
As to claim 3, Voldman discloses the gate electrode forms a p-varactor (reverse
biased PN junction) with the adjacent third semiconductor region, para-0022+.
As to claim 4, Voldman discloses the gate electrode (140) is formed from a
heavily doped polysilicon layer (para-0014+) adjacent to an oxide insulator layer.
As to claim 5, Voldman discloses the gate is a fourth semiconductor region (128)
embedded in the third semiconductor region (122) and form a PN junction with the third semiconductor regions, the fourth semiconductor region (128) configured to induce additional space charges in the third semiconductor region (122) when a bias voltage is applied to the fourth semiconductor region.
As to claim 6, Voldman discloses herein a depth of the third semiconductor
region (122, figure 1G) is larger than a depth of the fourth semiconductor region (128).
As to claim 7, Voldman discloses the fourth semiconductor region (128) is a
heavily doped N+ region (para-0013+) and the third semiconductor region (122) is a p-
type semiconductor region.
As to claim 8, Voldman discloses the first heavily doped semiconductor region (126) is a P+ region, the second heavily doped semiconductor region (129) is an N+ region, and the third semiconductor region (122) is a p-type semiconductor region.
As to claim 9, Voldman further comprising a central P+ semiconductor region
(524, para-0047) that divides the third semiconductor region into two semiconductor regions.
As to claim 10, Voldman discloses the semiconductor device (100) is fabricated
as a silicon-on-insulator device.
As to claim 11, Voldman discloses the PN junction is configured to be forward
biased, para-0022+.
As to claim 12, Voldman discloses the second mode is a surge event mode
during which the voltage received at the anode electrical contact is greater than a
threshold voltage, and the first mode is a normal operation mode during which the
voltage received at the anode electrical contact is less than the threshold voltage, para-
0019+.
Allowable Subject Matter
Claims 13-20 are allowed.
The following is an examiner's statement of reasons for allowance:
Neither the references cited nor the cited references teach, suggest, or in
combination of a circuit for shunting current in a circuit protection configuration having a
coupling circuit configured to couple a second voltage level to the gate when a voltage
of the first voltage source is below a threshold voltage, and configured to pull the gate
down to a ground voltage when the voltage of the first voltage source is above the
threshold voltage.
Any comments considered necessary by applicant must be submitted no later
than the payment of the issue fee and, to avoid processing delays, should preferably
accompany the issue fee. Such submissions should be clearly labeled "Comments on
Statement of Reasons for Allowance."
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 10/10/2025 have been fully considered but they are not persuasive. Applicant argues:
Voldman does not describe or suggest,
"A semiconductor device…comprising:
a first heavily doped semiconductor region having an anode electrical contact and a first doping polarity;
a second heavily doped semiconductor region having a cathode electrical contact and a second doping polarity opposite to the first doping polarity;" and
"a third semiconductor region extending between the first heavily doped semiconductor region and the second heavily doped semiconductor region, the second heavily doped semiconductor region and the third semiconductor region forming a PN junction," as is recited in currently amended independent claim 1, see in Remark, pages 1-2.
After carefully review, examiner respectively disagrees.
As shown in figure 1G, Voldman clearly discloses the first heavily doped semiconductor region (P+,126, para-0017), the second heavily doped semiconductor region (N+, 129, para-0017), and the third semiconductor region (P+, 122) formed in between the first and second heavily doped semiconductor region (126, 129), the structure is formed as the same as in the instant application as shown in figures 6A-6B, in the formed PN or NP junction.
As in figure 9, Voldman clearly discloses in para-0047 that the central P+ (524) semiconductor region that divides the third semiconductor region into two semiconductor regions," as recited in claim 9.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T DINH/Primary Examiner, Art Unit 2848