DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/16/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub 2014/0264610 to Yang et al (hereinafter Yang).
Regarding Claim 1, Yang discloses a three-dimensional stacked (3D-stacked) semiconductor device comprising:
a lower active region (92, Fig. 5) divided into a lower-1ˢᵗ active sub-region and a lower-2ⁿᵈ active sub-region by at least one lower boundary gate structure; and
an upper active region (94), above the lower active region, divided into an upper- 1ˢᵗ active sub-region and an upper-2ⁿᵈ active sub-region by at least one upper boundary gate structure,
wherein at least one of the lower boundary gate structure (98) and the upper boundary gate structure (100) is reverse-biased to electrically isolate the lower-1ˢᵗ active sub-region from the lower-2ⁿᵈ active sub-region, and/or electrically isolate the upper-1ˢᵗ active sub-region from the upper- 2ⁿᵈ active sub-region [0023].
Yang doesn’t explicitly disclose the two active regions to be stacked over each other.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the device of Yang such that the two regions are stacked. 3D circuits were known in the art, prior to the invention, and provide obvious benefits such as allowing for denser circuits and minimize the area a circuit occupies on a substrate.
Regarding Claim 2, Yang makes obvious the 3D-stacked semiconductor device of Claim 1, wherein the upper boundary gate structure is vertically above the lower boundary gate structure (Fig. 5, in an embodiment placing FET 92 over FET 94).
Regarding Claim 3, Yang makes obvious the 3D-stacked semiconductor device of Claim 2, wherein the lower active region comprises at least one dopant of 1st-type polarity, and the upper active region comprises at least one dopant of 2nd-type polarity opposite to the 1st-type polarity, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is configured to prevent current flow between the lower-1st active sub-region and the lower-2nd active sub-region and/or between the upper-1st active sub-region and the upper-2nd active sub-region [0033] & [0023].
Regarding Claim 4, Yang makes obvious the 3D-stacked semiconductor device of Claim 1, wherein the lower boundary gate structure is connected to a 1st voltage source of a 1st-type polarity, and the upper boundary gate structure is connected to a 2nd voltage source of a 2nd-type polarity opposite to the 1st-type polarity [0033].
Regarding Claim 5, Yang discloses the 3D-stacked semiconductor device of Claim 4, further comprising at least one of:
a 1st metal line, through which the lower boundary gate structure is connected to the 1st voltage source [0033]; and
a 2nd metal line through which the upper boundary gate structure is connected to the 2nd voltage source at a back side of the 3D-stacked semiconductor device which is opposite to a back-end-of-line (BEOL) of the 3D-stacked semiconductor device [0033].
Yang does not disclose the 2nd voltage source being on a backside of the structure. However, backside interconnections were known at the time and would have been obvious for a stacked structure to utilize to more efficiently package the circuit together and/or minimize potential parasitic capacitance between interconnections.
Regarding Claim 6, Yang makes obvious the 3D-stacked semiconductor device of Claim 1, wherein the upper active region has a smaller width than the lower active region in a channel-width direction (Fig 5, since the two regions can be stacked in either manner).
Regarding Claims 11 and 12, Yang makes obvious the 3D-stacked semiconductor device of Claim 1, wherein one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2"d active sub-region, or electrically isolate the upper-1st active sub-region from the upper-2"d active sub-region, and wherein the other of the lower boundary gate structure and the upper boundary gate structure is neither forward-biased nor reverse-biased and
wherein one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased by being connected to a positive voltage source or an negative voltage source, and wherein the other of the lower boundary gate structure and the upper boundary gate structure is not connected to any one of the positive voltage source or the negative voltage source.
Not connecting one of the boundary gate structures to a positive or negative voltage would merely require not sending a signal to one of the boundary gates. The functional language of a device is not germane to the structure and has not been given much patentable weight.
Regarding Claim 13, Yang makes obvious the 3D-stacked semiconductor device of Claim 1, further comprising a metal line formed at a back side of the 3D-stacked semiconductor device, which is opposite to a back-end- of-line (BEOL) of the 3D-stacked semiconductor device, wherein one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased by being connected to a positive voltage source or an negative voltage source through the metal line.
Yang does not disclose the metal line as being on a backside of the structure. However, backside interconnections were known at the time and would have been obvious for a stacked structure to utilize to more efficiently package the circuit together and/or minimize potential parasitic capacitance between interconnections.
Regarding Claim 14, Yang discloses a three-dimensional stacked (3D-stacked) semiconductor device comprising:
a 1st lower transistor and a 1st upper transistor thereabove (Fig. 5; 92);
a 2nd lower transistor and a 2nd upper transistor thereabove (94); and
at least one lower boundary transistor (98) between the 1st and 2nd lower transistors, and at least one upper boundary transistor (100), above the lower boundary transistor, between the 1st and 2nd upper transistors, wherein at least one of the lower boundary transistor and the upper boundary transistor is deactivated.
Yang doesn’t explicitly disclose the two active regions to be stacked.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the device of Yang such that the two regions are stacked. 3D circuits were known in the art, prior to the invention, and provide obvious benefits such as allowing for denser circuits and minimize the area a circuit occupies on a substrate. Additionally, deactivating a transistor can amount to not sending a signal to it for biasing one way or another. The functional language of a device is not germane to the structure and has not been given much patentable weight.
Regarding Claim 15, Yang makes obvious the 3D-stacked semiconductor device of Claim 14, wherein a gate structure of at least one of the lower boundary transistor and the upper boundary transistor is biased to a positive polarity or a negative polarity [0033].
Regarding Claim 16, Yang makes obvious the 3D-stacked semiconductor device of Claim 14, wherein a gate structure of at least one of the lower boundary transistor and the upper boundary transistor is connected to a positive voltage source or negative voltage source so that the 1st lower transistor is electrically isolated from the 2nd lower transistor and/or the 1st upper transistor is electrically isolated from the 2nd upper transistor [0033].
Regarding Claim 17, Yang makes obvious the 3D-stacked semiconductor device of Claim 16, wherein a gate structure of at least one of the lower boundary transistor and the upper boundary transistor is biased to a positive polarity or a negative polarity [0033].
Regarding Claim 18, Yang makes obvious the 3D-stacked semiconductor device of Claim 14, wherein the 1st lower transistor, the lower boundary transistor and the 2nd lower transistor are of one or a p-type and an n-type, and a gate structure of the lower boundary transistor is connected to a voltage source of the one of the p-type and the n-type, and wherein the 1st upper transistor, the upper boundary transistor and the 2nd upper transistor are of the other of the p-type and the n-type, and a gate structure of the upper boundary transistor is connected to the other of the p-type and the n-type [0033].
Regarding Claim 19, Yang discloses a three-dimensional stacked (3D-stacked) semiconductor device comprising:
a lower active region (92) surrounded by a plurality of lower gate structures arranged at a predetermined gate pitch; and
an upper active region (94) surrounded by a plurality of upper gate structures, respectively above the lower gate structures, arranged at the predetermined gate pitch,
wherein at least one of the lower gate structures and the upper gate structures is biased to electrically isolate two source/drain regions, connected by a channel structure surrounded by the at least one gate structure, from each other [0023].
Yang doesn’t explicitly disclose the two active regions to be stacked.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the device of Yang such that the two regions are stacked. 3D circuits were known in the art, prior to the invention, and provide obvious benefits such as allowing for denser circuits and minimize the area a circuit occupies on a substrate.
Regarding Claim 20, Yang discloses the 3D-stacked semiconductor device of Claim 19, further comprising a metal line through which the at least one of the lower gate structures and the upper gate structures is connected to a positive voltage source or a negative voltage source, and wherein the metal line is formed at a back side of the 3D-stacked semiconductor device, which is opposite to a back-end-of-line (BEOL) of the 3D-stacked semiconductor device [0033].
Yang does not disclose the metal line formed on a backside of the structure. However, backside interconnections were known at the time and would have been obvious for a stacked structure to utilize to more efficiently package the circuit together and/or minimize potential parasitic capacitance between interconnections.
Allowable Subject Matter
Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7 and 8 recite a nanowire structure for the transistors. It is not apparent that the nMOS and pMOS structures of Yang would function equally well as a GAA structure.
Claims 9 and 10 require the lower boundary gate structure and the upper boundary gate structure share a gate electrode pattern connected to a positive voltage source or a negative voltage source. It is not apparent that the structure of Yang would benefit from such a modification or function equally as well.
Conclusion
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893