DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/03/2026 has been entered.
Status of the Application
Claims 1-16 remain pending in this application. Acknowledgement is made of the amendment received 02/03/2026. Claims 1 and 7 are amended.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (US 20230180456 A1, priority date 12/03/2021, hereafter Jeong) in view of Lo et al (US 20210193566 A1, hereafter Lo).
Regarding claim 1, Jeong teaches: A semiconductor device (Jeong 100, fig 2-5, ¶0031, 0037) comprising:
a lower structure (Jeong 110, at least a structure below SCA, fig 1, ¶0031);
a plurality of active layers (Jeong 120, ¶0040-0041) horizontally oriented along a direction (Jeong Y, fig 3) parallel to a surface of the lower structure (Jeong top surface of 110, with respect to fig 2);
a plurality of bit lines (Jeong 150, ¶0041, fig 3) including a first conductive material (Jeong ¶0053, “… doped semiconductor materials … a conductive metal nitride … a metal-semiconductor …”) coupled to the active layers, respectively (Jeong ¶0041, fig 3), and extended in a vertical direction (Jeong Z) to the surface of the lower structure (Jeong fig 2, 150 extends perpendicular to the top surface of 110);
a word line (Jeong 130, ¶0044) including a second conductive material different from the first conductive material (Jeong ¶0045, “a conductive barrier film and a conductive filling layer covering the conductive barrier film”) horizontally extended in a direction crossing the active layers over the active layers (Jeong fig 3, 4, ¶0044, 130 extends horizontally in the Y direction, crossing 120);
a capping layer (Jeong 132, ¶0046, at least on the bit line side of 130 with respect to fig 3, under a broadest reasonable interpretation of a capping layer) disposed between the bit lines and the word line (Jeong fig 3, ¶0046).
Jeong does not teach: the capping layer including an air gap disposed between the bit lines and the word lines, wherein the air gap is disposed between the bit line and the word line.
Lo, in the same field of endeavor of semiconductor device manufacturing, teaches: a dielectric structure (Lo 115, similar to Jeong 132) disposed between two conductive wires (Lo 114, similar to Jeong 130 and 150)(Lo fig 1), the dielectric structure including an air gap (Lo 112) disposed between the two conductive wires (Lo fig 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the capping layer of Jeong to include the dielectric structure of Lo, such that “the capping layer including an air gap disposed between the bit lines and the word lines, wherein the air gap is disposed between the bit line and the word line”, in order to reduce the dielectric constant of the capping layer (Lo ¶0003, ¶0017), thereby reducing parasitic capacitance and/or improving device performance (Lo ¶0002, 0003, 0017).
Regarding claim 2, Jeong in view of Lo teaches: The semiconductor device of claim 1, wherein the capping layer (Jeong 132 as modified by Lo 115) further includes an inner liner (Lo 118) and an outer liner (Lo 116)(Lo 118 is at least inside Lo 116), wherein the air gap (Lo 112) is bounded by the inner liner and the outer liner (Lo fig 1, ¶0017).
Regarding claim 3, Jeong in view of Lo teaches: The semiconductor device of claim 2, wherein at least one of the inner liner (Lo 118) and the outer liner (Lo 116) includes silicon oxide, silicon carbon oxide, silicon nitride, or a combination thereof (Lo ¶0041, “liner 116 may … comprise silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride, … or any combination of the foregoing”, ¶0044, “liner 118 … comprise silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride … or any combination of the foregoing”, similar to Jeong ¶0100, “132 … silicon nitride”).
Regarding claim 4, Jeong in view of Lo teaches: The semiconductor device of claim 1, wherein the word line (Jeong 130) includes a double word line structure (Jeong fig 2, ¶0044, having an upper and lower level per cell/transistor 120) or a single word line structure.
Regarding claim 5, Jeong in view of Lo teaches: The semiconductor device of claim 1, wherein the air gap (Lo 112, Jeong 132 as modified by Lo 115) is extended along a sidewall (Jeong 132S2) of the word line (Jeong 130)(Jeong fig 5, ¶0046, Jeong 132 is extended along Y direction, where 130 and 132 share a side wall).
Regarding claim 6, Jeong in view of Lo teaches: The semiconductor device of claim 1, wherein the air gap (Lo 112, Jeong 132 as modified by Lo 115) includes an isolated structure disposed to correspond to each of the bit lines (Jeong fig 3, 4, each 132 corresponding to a bit line are isolated from each other in the Y direction by at least 134, in the X direction by 130, and the Z direction by 140).
Regarding claim 7, Jeong teaches: A semiconductor device (Jeong 100, fig 2-5, ¶0031, 0037) comprising:
a lower structure (Jeong 110, at least a structure below SCA, fig 1, ¶0031);
a plurality of active layers (Jeong 120, ¶0040-0041) horizontally spaced apart along a direction (Jeong Y, fig 3) parallel to a surface of the lower structure (Jeong top surface of 110, with respect to fig 2);
a word line (Jeong 130, ¶0044) including a first conductive material (Jeong ¶0045, “a conductive barrier film and a conductive filling layer covering the conductive barrier film”) horizontally extended in a direction crossing the active layers over the active layers (Jeong fig 3, 4, ¶0044, 130 extends horizontally in the Y direction, crossing 120);
a plurality of bit lines (Jeong 150, ¶0041, fig 3) including a second conductive material different from the first conductive material (Jeong ¶0053, “… doped semiconductor materials … a conductive metal nitride … a metal-semiconductor …”) coupled to first sides (Jeong 122) of the active layers, respectively (Jeong ¶0041, fig 3), and extended in a vertical direction (Jeong Z) to the surface of the lower structure (Jeong fig 2, 150 extends perpendicular to the top surface of 110);
a plurality of capacitors (Jeong CAP, ¶0031, 0036) coupled to second sides (Jeong 126) of the active layers, respectively (Jeong ¶0056, fig 3);
a bit line-side capping layer (Jeong 132, ¶0046, at least on the bit line side of 130 with respect to fig 3, under a broadest reasonable interpretation of a capping layer) disposed between the bit lines and the word line (Jeong fig 3, ¶0046), and
a capacitor-side capping layer (Jeong 162, ¶0052, at least on the CAP side of 130 with respect to fig 3, under a broadest reasonable interpretation of a capping layer) disposed between the capacitors and the word line (Jeong fig 3).
Jeong does not teach: the bit line-side capping layer including an air gap disposed between the bit lines and the word line, wherein the air gap is disposed between the bit line and the word line.
Lo, in the same field of endeavor of semiconductor device manufacturing, teaches: a dielectric structure (Lo 115, similar to Jeong 132) disposed between two conductive wires (Lo 114, similar to Jeong 130 and 150)(Lo fig 1), the dielectric structure including an air gap (Lo 112) disposed between the two conductive wires (Lo fig 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the bit line-side capping layer of Jeong to include the dielectric structure of Lo, such that “the bit line-side capping layer including an air gap disposed between the bit lines and the word line, wherein the air gap is disposed between the bit line and the word line”, in order to reduce the dielectric constant of the capping layer (Lo ¶0003, ¶0017), thereby reducing parasitic capacitance and/or improving device performance (Lo ¶0002, 0003, 0017).
Regarding claim 8, Jeong in view of Lo teaches: The semiconductor device of claim 7, wherein the bit line-side capping layer (Jeong 132 as modified by Lo 115) further includes an inner liner (Lo 118) and an outer liner (Lo 116)(Lo 118 is at least inside Lo 116), and wherein the air gap (Lo 112) is bounded by the inner liner and the outer liner (Lo fig 1, ¶0017).
Regarding claim 9, Jeong in view of Lo teaches: The semiconductor device of claim 8, wherein at least one of the inner liner (Lo 118) and the outer liner (Lo 116) includes silicon oxide, silicon carbon oxide, silicon nitride, or a combination thereof (Lo ¶0041, “liner 116 may … comprise silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride, … or any combination of the foregoing”, ¶0044, “liner 118 … comprise silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride … or any combination of the foregoing”, similar to Jeong ¶0100, “132 … silicon nitride”).
Regarding claim 10, Jeong in view of Lo teaches: The semiconductor device of claim 7, wherein the capacitor-side capping layer (Jeong 162) includes silicon oxide, silicon carbon oxide, silicon nitride, or a combination thereof (Jeong ¶0096, “silicon oxide film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, and a carbon-containing silicon oxynitride film”).
Regarding claim 11, Jeong in view of Lo teaches: The semiconductor device of claim 7, wherein at least one of the active layers (Jeong 120) includes a silicon layer, monocrystalline silicon layer, polysilicon layer, or oxide semiconductor material (Jeong ¶0040, “polysilicon … amorphous metal oxide and a polycrystalline metal oxide … IGO … IZO … IGZO”).
Regarding claim 12, Jeong in view of Lo teaches: The semiconductor device of claim 7, wherein the word line (Jeong 130) includes a double word line structure (Jeong fig 2, ¶0044, having an upper and lower level per cell/transistor 120) or a single word line structure.
Regarding claim 13, Jeong in view of Lo teaches: The semiconductor device of claim 7, wherein the air gap (Lo 112, Jeong 132 as modified by Lo 115) is extended along a sidewall (Jeong 132S2) of the word line (Jeong 130)(Jeong fig 5, ¶0046, Jeong 132 is extended along Y direction, where 130 and 132 share a side wall).
Regarding claim 14, Jeong in view of Lo teaches: The semiconductor device of claim 7, wherein the air gap (Lo 112, Jeong 132 as modified by Lo 115) includes an isolated structure disposed to correspond to each of the bit lines (Jeong fig 3, 4, each 132 corresponding to a bit line are isolated from each other in the Y direction by at least 134, in the X direction by 130, and the Z direction by 140).
Regarding claim 15, Jeong in view of Lo teaches: The semiconductor device of claim 1, wherein the word line (Jeong 130) includes notch-type sidewalls (Jeong 130RC, 132S2, ¶0044, 0046, fig 3, 5, under a broadest reasonable interpretation, 130RC at least creates a notch between a plurality of sidewalls 132S2 in the left side of 130 with respect to figs 3 and 5) facing each other (Jeong fig 3, 5, at least face each other with respect to a mirror axis about center of 134) and an individual notch-type sidewall includes flat surfaces (Jeong 132S2, ¶0046) and recessed surfaces (Jeong 130RC, ¶0044),
wherein the air gap (Jeong 132 as modified by Lo 115) is disposed between the recess surfaces of the word line (Jeong 130) and the bit line (Jeong 150)(Jeong fig 3, 5, Jeong 132 is at least between 130RC to the right of 132S2 and the bit line 150 with regard to figs 3 and 5).
Regarding claim 16, Jeong in view of Lo teaches: The semiconductor device of claim 7, wherein the word line (Jeong 130) includes notch-type sidewalls (Jeong 130RC, 132S2, ¶0044, 0046, fig 3, 5, under a broadest reasonable interpretation, 130RC at least creates a notch between a plurality of sidewalls 132S2 in the left side of 130 with respect to figs 3 and 5) facing each other (Jeong fig 3, 5, at least face each other with respect to a mirror axis about center of 134) and an individual notch-type sidewall includes flat surfaces (Jeong 132S2, ¶0046) and recessed surfaces (Jeong 130RC, ¶0044),
wherein the air gap (Jeong 132 as modified by Lo 115) is disposed between the recess surfaces of the word line (Jeong 130) and the bit line (Jeong 150)(Jeong fig 3, 5, Jeong 132 is at least between 130RC to the right of 132S2 and the bit line 150 with regard to figs 3 and 5).
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 7, applicant argues at pages 9-13:
Jeong does not teach an air gap, and that Lo’s air gap (Lo 112) is formed between two conductive metal wirings (Lo 114) made of the same conductive material, wherein the two conductive metal wirings do not correspond to the bit line and the word line requiring different conductive materials, therefore the limitations of claims 1 and 7 are not met.
Applicant further argues at page 13, “There is no teaching, suggestion, or motivation, that would have led one of ordinary skill in the art to make the proposed substitution. Moreover, substituting Lo's air gap into Jeong would therefore require hindsight reconstruction”.
Examiner’s response:
The examiner respectfully disagrees. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The proposed modification does not import Lo’s interconnect wiring into Jeong, rather, it modifies Jeong’s existing capping layer (Jeong 132), which is already disposed between a bit line and a word line (Jeong 150 and 130, respectively), to include Lo’s air gap. Applicant expressly concedes at page 11 that “The spacer 132 of Jeong is formed between two conductive lines (BL, WL) made of different conductive materials”, therefore the amended limitation requiring different conductive materials does not distinguish the claimed device from the combination of Jeong and Lo.
Additionally, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the Lo teaches (Lo ¶0003, 0017, 0026) that an air gap in a dielectric structure reduces the effective dielectric constant, thereby reducing parasitic capacitance between adjacent conductors. Jeong’s capping layer (Jeong 132) is disposed between adjacent conductors (a bit line and a word line, Jeong ¶0046, fig 3). A POSITA would apply Lo’s airgap technique to Jeong’s capping layer to achieve greater capacitance reduction using a known method.
Further, in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818