CTNF 17/989,412 CTNF 98893 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-09 AIA Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) as follows: The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc. , 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994). The disclosure of the prior-filed application, U.S. Provisional Patent Application No. 62/958,223, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. Independent claim 1 recites a processor unit configured to store and to transmit, of which insufficient disclosure is provided from the Provisional Application. Accordingly, claims 1-23 are not entitled to the benefit of the prior Provisional application for the date 01/07/2020. The instant application is filed as continuation-in-part to U.S. Non-Provisional Patent Application No. 17/090,462 and receives benefit to 11/05/2020. The instant application claims foreign priority to KR 10-2020-0006902 and receives benefit to 01/17/2020. The effective filing date for all claims 1-23 is 01/17/2020. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-11, 13-23 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190096453 A1 Shin et al. (hereinafter “ Shin ”) in view of US 20200294575 A1 O et al. (hereinafter “ O ”) in view of US 20210150311 A1 Zhou et al. (hereinafter “ Zhou ”) . Regarding claim 1, Shin discloses a processing-in-memory (PIM) device comprising: memory banks (Figs. 3-4 “MB 200” [0039]) configured to perform a read operation and a write operation ([0043]) in a normal mode, and to perform a first data providing operation (Fig. 4 “DW1-DWn” [0044]) in an accelerator mode; a global buffer (Fig. 3 “GBF 1040” [0033], [0040]) configured to perform a second data providing operation (Fig. 4 “DA” [0044]) in the accelerator mode; processing elements (Figs. 3-4 “CB 300” [0039]) configured to perform (Fig. 4 “CU1-CUn” [0044]; Fig. 25 “calculation unit 500” [0106]) at least one of a first arithmetic operation (Fig. 25 “520” [0106]) and a second arithmetic operation (Fig. 25 “540” [0106]) using at least one of the first data (Fig. 6 “DW[N-1:0]” [0059]) and the second data (Fig. 6 “DA[N-1:0]” [0059]) in the accelerator mode; a command decoder (Fig. 5 “Command Decoder 411” [0057]) configured to output ([0057]) a normal mode control signal or an accelerator mode start signal; and a processor unit (Fig. 2 “CTRL 1030” [0034]) configured to store an operation instruction set transmitted from an external device (Fig. 2 “2000” [0034]), to transmit the operation instruction set to the processing elements (Figs. 3-4 “CB 300” [0039]), and to transmit the accelerator mode control signal to the processing elements (Figs. 3-4 “CB 300” [0039]). Shin appears to be silent with disclosing a normal mode, an accelerator mode , a global buffer configured to perform providing , a normal mode control signal or an accelerator mode start signal, processor unit configured to store an operation instruction set, to transmit the operation instruction set, and to transmit the accelerator mode control signal. O discloses a normal mode ([0057]), an accelerator mode ([0054] operating processing mode), a normal mode control signal ([0068] INPUT_CTRL) or an accelerator mode start signal ([0069] CAL_CTRL), processor unit configured to store an operation instruction set ([0035]), to transmit the operation instruction set ([0034]), and to transmit the accelerator mode control signal ([0069]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Shin’s processing-in-memory device to further comprise modes of operation and instructions as disclosed by O’s features because they are in the claimed invention’s same field of endeavor of processor in memory architecture ([abstract]). Modifying with O’s modes and instructions would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements in control of the device by indicating which flow of operations should execute ([0043], [0056]; Fig. 9 “S12” [0080]). Using O’s modes and instructions to provide a predictable result in Shin’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Shin’s device was ready for improvement to incorporate the mode and instruction features and doing so would be beneficial by providing a greater control of data flow and avoid unnecessary operation executions in the device. O appears to be silent with disclosing a global buffer configured to perform providing. Shin in view of O appears to be silent with disclosing a global buffer configured to perform providing. Zhou discloses a global buffer configured to perform ([0044]) providing. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Shin in view of O’s processing-in-memory device to further comprise buffer functionality as disclosed by Zhou’s features because they are in the claimed invention’s same field of endeavor of processor in memory architecture ([abstract]). Modifying with Zhou’s buffer functionality would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements in moving data of one row of memory cells per one cycle ([0054]). Using Zhou’s buffer functionality to provide a predictable result in Shin in view of O’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Shin in view of O’s device was ready for improvement to incorporate the global buffer features and doing so would be beneficial by providing improved data transferring in the device. Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the memory banks (Figs. 3-4 “MB 200” [0039]) include first to "K"th memory banks (Fig. 4 “DBK1-DBKn” [0043]), the processing elements (Figs. 3-4 “CB 300” [0039]) include first to "K"th processing elements (Fig. 4 “CU1-CUn” [0044]), and the first to "K"th processing elements receive first to "K"th groups of the first data from the first to "K"th memory banks, respectively (Fig. 4 “DBK1, DW1, CU1” [0043-0044]), in the accelerator mode, and wherein the "J"th processing element among the first to "K"th processing elements is configured to receive a "J"th group of the first data from the "J"th memory bank among the first to "K"th memory banks (Fig. 4 “DBK2, DW2, CU2” [0043-0044]), wherein "K" is a natural number (Fig. 4 exemplifies an example of at least three corresponding “DBKn, CUn” [0045]), and wherein "J" is a natural number from 1 to "K" (Fig. 4 exemplifies three from “DBK1, CU1” to “DBKn, CUn” [0045]). Shin appears to be silent with disclosing an accelerator mode. O discloses an accelerator mode ([0054] operating processing mode). The motivation to combine provided with respect to claim 1 similarly applies. Regarding claim 3, the teachings addressed in the claim 2 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the first data (Fig. 6 “DW[N-1:0]” [0059]; Fig. 25 “DW[N-1:0]” [0106]) includes weight data of a weight matrix having at least "K" rows (Fig. 25 “N-1 of DW[N-1:0]” [0062], [0106]), and wherein the "J"th group of the first data is composed of elements of the "J"th row of the weight matrix ([0111] i-th rows). Regarding claim 4, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Shin discloses the PIM device wherein each of the first to "K"th processing elements (Fig. 4 “DBK1, DW1, CU1” [0043-0044]; Fig. 26 “BANK0-BANK15” [0108-0109]) includes first to "L"th MAC operators (Fig. 27 “CU0-0 to CU95-15” “MULTIPLICATION, SUM” [0111]) that perform the first arithmetic (Fig. 25 “520” [0106]) and at least one vector engine (Fig. 26 “Adder 610a-610p” [0109]) that performs the second arithmetic (Fig. 25 “540” [0106]), and wherein "L" is a natural number (Fig. 27 “CU0-0 to CU95-15” “MULTIPLICATION, SUM” [0111] 0 to 95 or 0 to 15). Regarding claim 5, the teachings addressed in the claim 4 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the "J"th group of the first data includes at least first to "L"th sets (Fig. 6 “DW[N-1:0]” [0059]; Fig. 25 “DW[N-1:0]” [0106]; Fig. 27 “DW0-DW95” [0112]), and wherein the first to "L"th MAC operators (Fig. 27 “CU0-0 to CU95-15” “MULTIPLICATION, SUM” [0111]) included in the "J"th processing element among the first to "K"th processing elements (Fig. 4 “DBK1, DW1, CU1” [0043-0044]; Fig. 26 “BANK0-BANK15” [0108-0109]) are configured to receive the first to "L"th sets of the "J"th group of the first data (Fig. 6 “DW[N-1:0]” [0059]; Fig. 25 “DW[N-1:0]” [0106]; Fig. 27 “DW0-DW95” [0112]), respectively, from the "J"th memory bank (Fig. 4 “DBK2, DW2, CU2” [0043-0044]). Regarding claim 6, the teachings addressed in the claim 5 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the second data (Fig. 4 “DA” [0044]) includes vector data of a vector matrix having at least the same number of rows as columns of the weight matrix and at least one column (Fig. 27 “DA0-DA31” [0112]), and the rows of the second data are divided into first to "L" sets (Fig. 27 “DA0-DA15”, “DA16-DA31” [0112]), and wherein the first to "L"th MAC operators (Fig. 27 “CU0-0 to CU95-15” “MULTIPLICATION, SUM” [0111]) of each of the first to "K"th processing elements (Fig. 4 “CU1-CUn” [0044]) are configured to receive the first to "L"th set of the second data (Fig. 27 “Broadcast” [0112]) , respectively, from the global buffer (Fig. 3 “GBF 1040” [0033]). Shin appears to be silent with disclosing from the global buffer . O appears to be silent with disclosing from the global buffer. Shin in view of O appears to be silent with disclosing from the global buffer. Zhou discloses from ([0044]) the global buffer. The motivation to combine provided with respect to claim 1 similarly applies. Regarding claim 7, the teachings addressed in the claim 4 analysis and rejection are incorporated, and Shin discloses the PIM device wherein each of the first to "K"th processing elements (Fig. 4 “DBK1, DW1, CU1” [0043-0044]; Fig. 26 “BANK0-BANK15” [0108-0109]) includes: an internal instruction buffer configured to store the operation instruction set transmitted from the processor unit (Fig. 2 “CTRL 1030” [0034]); and an internal processor configured to transmit an internal control signal corresponding to the operation instruction set stored in the internal instruction buffer to the first to "L"th MAC operators (Fig. 27 “CU0-0 to CU95-15” “MULTIPLICATION, SUM” [0111]) and the vector engine (Fig. 26 “Adder 610a-610p” [0109]), in response to the accelerator mode start signal transmitted from the processor unit (Fig. 2 “CTRL 1030” [0034]). Shin appears to be silent with disclosing an internal instruction buffer configured to store the operation instruction set transmitted, an internal processor configured to transmit an internal control signal corresponding to the operation instruction set stored in the internal instruction buffer, and in response to the accelerator mode start signal transmitted. O discloses an internal instruction buffer (Fig. 7 “460” [0070]) configured to store the operation instruction set transmitted (Fig. 7 bidirectional arrow “Inst” from “460” [0073]), an internal processor (Fig. 7 “450” [0070]) configured to transmit an internal control signal (Fig. 7 “PEIO_CTRL, INPUT_CTRL, CAL_CTRL, REG_CTRL, OUTPUT_CRL, Inst_CTRL” [0072]) corresponding to the operation instruction set stored in the internal instruction buffer (Fig. 7 “Inst” [0073]), and in response to the accelerator mode start signal transmitted (Fig. 7 “CMD ADD” [0054]). The motivation to combine provided with respect to claim 1 similarly applies. Regarding claim 8, the teachings addressed in the claim 7 analysis and rejection are incorporated, and Shin discloses the PIM device further comprising: a global input/output (GIO) line configured to transmit a first data from the first to "K"th memory banks to the first to "K"th processing elements; and a vector transmission line configured to transmit a second data from the global buffer to the first to "K"th processing elements (see claim 15 mapping). Regarding claim 9, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Shin discloses the PIM device wherein data transmission capacity of the vector transmission line is at least "L" times greater than data transfer capacity of the GIO line (see claim 18 mapping). Regarding claim 10, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Shin discloses the PIM device wherein each of the first to "K"th processing elements further includes: a first buffer coupled to the GIO line; a second buffer coupled to the vector transmission line; and a third buffer coupled to the GIO line and configured to store arithmetic result data transmitted from the first to "L"th MAC operators and the vector engine (see claim 19 mapping). Regarding claim 11, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the command decoder (Fig. 5 “Command Decoder 411” [0057]) is configured to output a read control signal ([0057] read operation) or a write control signal ([0057] write operation) as the normal mode control signal to the first to "K"th memory banks (Fig. 4 “DBK1…DBKn” [0043-0044]), and is configured to output the accelerator mode start signal to the processor unit (Fig. 2 “CTRL 1030” [0034]). Shin appears to be silent to disclosing the normal mode control signal and the accelerator mode start signal. O discloses the normal mode control signal ([0068] INPUT_CTRL) and the accelerator mode start signal ([0069] CAL_CTRL). The motivation to combine provided with respect to claim 1 similarly applies. Regarding claim 13, the teachings addressed in the claim 11 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the processor unit (Fig. 2 “CTRL 1030” [0034]) includes: a main processor configured to output the operation instruction set and the accelerator mode start signal to the processing elements (Figs. 3-4 “CB 300” [0039]); and an instruction buffer configured to store the operation instruction set, and to transmit the operation instruction set to the main processor in response to a request signal from the main processor. Shin appears to be silent to disclosing a main processor configured to output the operation instruction set and the accelerator mode start signal; and an instruction buffer configured to store the operation instruction set, and to transmit the operation instruction set to the main processor in response to a request signal from the main processor. O discloses a main processor (Fig. 1 “100” [0025], [0034]) configured to output the operation instruction set (Fig. 1 “Inst” [0035]) and the accelerator mode start signal (Fig. 1 “CMD_PE” “CMD/ADD” [0035], [0069] CAL_CTRL); and an instruction buffer (Fig. 1 “110” [0025]) configured to store the operation instruction set, and to transmit the operation instruction set to the main processor in response ([0026]) to a request signal from the main processor ([0042] a request from the memory controller). Although O discloses the instruction buffer, they appear to be silent with disclosing it configured to store. However, in a separate section of the device, O discloses the functionality of storing instructions ([0035] instruction memory). It would have been obvious before the effective filing date to try the modification given that O discloses a controller coupled to memory configuration in Fig. 7 ([0070]). The instruction queue may store instructions received from a data bus of Fig. 7 ([0073]), which is similar to the memory interface of Fig. 1 ([0026]). Further, the modification would have been obvious to try before the effective filing date due to the beneficial nature of gaining a further functionality of storing instructions. The motivation to combine provided with respect to claim 1 similarly applies. Regarding claim 14, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Shin discloses the PIM device further comprising an external vector engine (Figs. 15, 19 “CAL” [0075], [0088], [0127]) configured to perform a reprocessing operation (Fig. 19 [0095-0096]) for vector result data (Fig. 4 “DR1-DRn” [0088]) from the processing elements (Figs. 3-4 “CB 300” [0039]). Regarding claim 15, the teachings addressed in the claim 14 analysis and rejection are incorporated, and Shin discloses the PIM device further comprising: a global input/output (GIO) line (Fig. 4, 6 “GIO” [0043], [0059-0060]) configured to transmit a first data ([0043] read data) from the memory banks (Figs. 3-4 “MB 200” [0039]) to the processing elements (Figs. 3-4 “CB 300” [0039]); and a vector transmission line (Fig. 2 “TSV” [0035]; Figs. 7, 8A-B “DBUS1-4” [0065], [0067]) configured to transmit a second data ([0035] broadcast data) from the global buffer (Fig. 3 “GBF 1040” [0033]) to the processing elements (Figs. 3-4 “CB 300” [0039]), wherein the external vector engine (Figs. 15, 19 “CAL” [0075], [0088], [0127]) is configured to communicate bidirectionally ([0067]) with the GIO line (Fig. 4 “GIO” [0043]) and the vector transmission line (Fig. 2 “TSV” [0035]; Figs. 7, 8A-B “DBUS1-4” [0065], [0067]). Regarding claim 16, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Shin discloses the PIM device wherein each of the processing elements (Figs. 3-4 “CB 300” [0039]) includes: MAC operators (Fig. 27 “CU0-0 to CU95-15” “MULTIPLICATION, SUM” [0111]) configured to perform MAC arithmetic operations corresponding to a first operation instruction set ([0119] MAC) transmitted from the processor unit (Fig. 2 “CTRL 1030” [0034]); and a vector engine (Fig. 26 “Adder 610a-610p” [0109]) configured to perform vector arithmetic operations corresponding to a second operation instruction set ([0120] SUM) transmitted from the processor unit (Fig. 2 “CTRL 1030” [0034]). Regarding claim 17, the teachings addressed in the claim 16 analysis and rejection are incorporated, and Shin discloses the PIM device further comprising: a global input/output (GIO) line configured to transmit a first data from the memory banks to the processing elements; and a vector transmission line configured to transmit a second data from the global buffer to the processing elements (see claim 15 mapping). Regarding claim 18, the teachings addressed in the claim 17 analysis and rejection are incorporated, and Shin discloses the PIM device wherein data transmission capacity of the vector transfer line is larger than (Fig. 2 “TSV” [0035]; Figs. 7, 8A-B “DBUS1-4” [0065-0067] four busses) data transmission capacity of the GIO line (Fig. 4, 6 “GIO” [0043], [0059-0060] input-output lines). Regarding claim 19, the teachings addressed in the claim 17 analysis and rejection are incorporated, and Shin discloses the PIM device wherein each of the processing elements (Figs. 3-4 “CB 300” [0039]) further includes: a first buffer (Fig. 25 “522” [0106]) coupled to the GIO line (Fig. 6 “GIO” further transformed into “DW[N-1:0]” by “IOSA” [0059]); a second buffer (Fig. 25 “521” [0106]) coupled to the vector transmission line (Fig. 6 “DA[N-1:0]” [0059]; [0035] broadcast data); and a third buffer (Fig. 25 “542” [0106]) coupled to the GIO line (Fig. 6 “GIO” further transformed into “DW[N-1:0]” by “IOSA” [0059]) and configured to store arithmetic result data (Fig. 25 output from “541” [0106]) transmitted from the MAC operators (Fig. 27 “CU0-0 to CU95-15” “MULTIPLICATION, SUM” [0111]) and the vector engine (Fig. 26 “Adder 610a-610p” [0109]). Regarding claim 20, the teachings addressed in the claim 17 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the processor unit (Fig. 2 “CTRL 1030” [0034]) includes: a main processor configured to output the first operation instruction set or the second operation instruction set to the processing elements (Figs. 3-4 “CB 300” [0039]) in response to the accelerator mode start signal; and an instruction buffer configured to store the first operation instruction set and the second operation instruction set, and to transmit the first operation instruction set and the second operation instruction set to the main processor in response to a request signal from the main processor. Shin appears to be silent to disclosing a main processor configured to output the first operation instruction set or the second operation instruction set in response to the accelerator mode start signal; and an instruction buffer configured to store the first operation instruction set and the second operation instruction set, and to transmit the first operation instruction set and the second operation instruction set to the main processor in response to a request signal from the main processor. O discloses a main processor (Fig. 1 “100” [0025], [0034]) configured to output the first operation instruction set or the second operation instruction set (Fig. 1 “Inst” [0035], [0034] plurality of instructions) in response to the accelerator mode start signal (Fig. 1 “CMD_PE” “CMD/ADD” [0035], [0069] CAL_CTRL); and an instruction buffer (Fig. 1 “110” [0025]) configured to store the first operation instruction set and the second operation instruction set ([0034] plurality of instructions), and to transmit the first operation instruction set and the second operation instruction set to the main processor in response ([0026]) to a request signal from the main processor ([0042] a request from the memory controller). Although O discloses the instruction buffer, they appear to be silent with disclosing it configured to store. However, in a separate section of the device, O discloses the functionality of storing instructions ([0035] instruction memory). It would have been obvious before the effective filing date to try the modification given that O discloses a controller coupled to memory configuration in Fig. 7 ([0070]). The instruction queue may store instructions received from a data bus of Fig. 7 ([0073]), which is similar to the memory interface of Fig. 1 ([0026]). Further, the modification would have been obvious to try before the effective filing date due to the beneficial nature of gaining a further functionality of storing instructions. The motivation to combine provided with respect to claim 1 similarly applies. Regarding claim 21, the teachings addressed in the claim 17 analysis and rejection are incorporated, and Shin discloses the PIM device further comprising an external vector engine configured to perform a reprocessing operation for vector result data from the processing elements (see claim 14 mapping). Regarding claim 22, the teachings addressed in the claim 21 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the external vector engine is configured to communicate bidirectionally with the GIO line and the vector transmission line (see claim 15 mapping). Regarding claim 23, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the memory banks (Figs. 3-4 “MB 200” [0039]) share one processing element (Fig. 3-4 “CB 300” [0039]). Although Shin generally disclosing the memory banks and processing elements, they appear to be silent to disclosing the configuration of memory banks sharing a singular processing element. O discloses memory banks sharing ([0050]) a processing element. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Shin’s processing-in-memory device to further comprise sharing circuit elements as disclosed by O’s features because they are in the claimed invention’s same field of endeavor of processor in memory architecture ([abstract]). Modifying with O’s sharing technique would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements by providing higher configurability of the device’s components via different configurations for processing data and unnecessary utilization of extraneous circuit components ([0050], [0114]). Using O’s sharing feature to provide a predictable result in Shin’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Shin’s device was ready for improvement to incorporate the sharing feature and doing so would be beneficial by providing a greater configurability of circuit components in the device and lead to improved performance of the device by avoiding unnecessary utilization of circuit components . 07-22-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of O in view of Zhou as applied to claim 1 above, and further in view of US 20190341091 A1 Sity et al. (hereinafter “ Sity ”) . Regarding claim 12, the teachings addressed in the claim 11 analysis and rejection are incorporated, and Shin discloses the PIM device wherein the command decoder (Fig. 5 “Command Decoder 411” [0057]) is configured to output a refresh control signal (Fig. 5 “REF_ADDR” [0052]), and wherein the command decoder is configured to transmit the refresh control signal (Fig. 5 transmit via “440” [0053]) to the first to "K"th memory banks (Fig. 4 “DBK1-DBKn” [0043]) in the normal mode, and is configured to transmit the refresh control signal to the processor unit (Fig. 2 “CTRL 1030” [0034]) in the accelerator mode. Shin appears to be silent to disclosing configured to output a refresh control signal from the command decoder. However, it would have been obvious before the effective filing date to include the refresh counter 445 in the control logic 410 since it has been held that forming in one piece an article, which has formerly been formed in two pieces and put together, involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). The term “integral” is sufficiently broad to embrace constructions united by such means as fastening and welding. In re Hotte, 177 USPQ 326, 328 (CCPA 1973). Further, making the modification before the effective filing date would have been obvious due to the beneficial nature of the incorporation as doing so would provide the control logic further functionality to perform refresh counting and outputting the refresh address ([0135]). Shin appears to be silent to disclosing the normal mode, and is configured to transmit the refresh control signal to the processor unit in the accelerator mode. O discloses the normal mode ([0057]) and the accelerator mode ([0054] operating processing mode). The motivation to combine provided with respect to claim 1 similarly applies. O appears to be silent to disclosing to transmit the refresh control signal to the processor unit . Zhou appears to be silent to disclosing to transmit the refresh control signal to the processor unit . Shin in view of O in view of Zhou appear to be silent with disclosing to transmit the refresh control signal to the processor unit . Sity discloses transmitting ([0201]) the refresh control signal to the processor unit . It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Shin in view of O in view of Zhou’s processing-in-memory device to further comprise transmitting functionality as disclosed by Sity’s features because they are in the claimed invention’s same field of endeavor of memory-based architecture ([abstract]). Modifying with Sity’s transmitting functionality would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements in providing greater functionality, control over circuit execution, and correctness of calculation ([0201]). Using Sity’s transmitting functionality to provide a predictable result in Shin in view of O in view of Zhou’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Shin in view of O in view of Zhou’s device was ready for improvement to incorporate the transmitting feature and doing so would be beneficial by providing greater functionality, control, and correctness of calculation in the device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151 /James Trujillo/Supervisory Patent Examiner, Art Unit 2151 Application/Control Number: 17/989,412 Page 2 Art Unit: 2151 Application/Control Number: 17/989,412 Page 3 Art Unit: 2151 Application/Control Number: 17/989,412 Page 4 Art Unit: 2151 Application/Control Number: 17/989,412 Page 5 Art Unit: 2151 Application/Control Number: 17/989,412 Page 6 Art Unit: 2151 Application/Control Number: 17/989,412 Page 7 Art Unit: 2151 Application/Control Number: 17/989,412 Page 8 Art Unit: 2151 Application/Control Number: 17/989,412 Page 9 Art Unit: 2151 Application/Control Number: 17/989,412 Page 10 Art Unit: 2151 Application/Control Number: 17/989,412 Page 11 Art Unit: 2151 Application/Control Number: 17/989,412 Page 12 Art Unit: 2151 Application/Control Number: 17/989,412 Page 13 Art Unit: 2151 Application/Control Number: 17/989,412 Page 14 Art Unit: 2151 Application/Control Number: 17/989,412 Page 15 Art Unit: 2151 Application/Control Number: 17/989,412 Page 16 Art Unit: 2151 Application/Control Number: 17/989,412 Page 17 Art Unit: 2151 Application/Control Number: 17/989,412 Page 18 Art Unit: 2151 Application/Control Number: 17/989,412 Page 19 Art Unit: 2151 Application/Control Number: 17/989,412 Page 20 Art Unit: 2151 Application/Control Number: 17/989,412 Page 21 Art Unit: 2151 Application/Control Number: 17/989,412 Page 22 Art Unit: 2151 Application/Control Number: 17/989,412 Page 23 Art Unit: 2151
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