DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 8/6/25 of Species II (Figs. 1, 3A-3B, 5A-5B), in the reply filed on 9/25/25 was acknowledged in a previous office action. Applicant has canceled non-elected claims 10-20.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/1/25 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: A) reference characters "14B”, “143”, and “146” have all been used to designate the “second memory layer” and B) reference characters “15B”, “153”, and “156” have all been used to designate the “second channel pattern”. See, for example, para 56 and 64.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9, and 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,566,348 B1 (“Yeh”) in view of US 2015/0155297 A1 (“Eom”).
Yeh teaches, for example:
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Yeh teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A semiconductor memory device (see e.g. Figs. 4, 7, 36, 39) comprising:
a first stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device; e.g. GSL/411/WL0/411/WL1/412…/415/SSL3 in Fig. 4) and a second stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device; e.g. GSL/411/WL0/411/WL1/412…/415/SSL2 in Fig. 4);
a first vertical structure (e.g. 243a/243b/290 in Fig. 2A) having a sidewall in contact with the first stack structure (see Figs. 2A, 4, etc.), the first vertical structure including a first memory layer (comprising e.g. “data storage structure” such as 243a) and a first channel pattern (comprising e.g. “semiconductor film” such as 243b, which is part of the “channel structure” 243, see e.g. col 8 lines 55-67);
a second vertical structure (e.g. 253a/253b/290 in Fig. 2A) having a sidewall in contact with the second stack structure (see Figs. 2A, 4, etc.), the second vertical structure including a second memory layer (comprising e.g. “data storage structure” such as 253a) and a second channel pattern (comprising e.g. “semiconductor film” such as 253b, which is part of the “channel structure” 253, see e.g. col 8 lines 55-67);
a first bit line contact structure (e.g. “first and second contacts 3371 or 3372” in Figs. 4 or 37; or 3371/3571 or 3372/3572 comprising “first and second contacts” such as 3371 and “first and second vias” such as 3571 in Figs. 4 or 37) on the first vertical structure; and
a first bit line (e.g. 3642 or 3652, see e.g. Fig. 4; see “bit lines” in Fig. 7; see 741-744 in Fig. 8; see 3641-3643 and 3651-3653 in Fig. 9; etc.) overlapping with the first bit line contact structure,
wherein each of the first stack structure and the second stack structure includes conductive layers spaced vertically apart from each other (see “word lines WL0, WL1… WLn,” which are spaced apart by “insulating strips 411-415”, see e.g. Fig. 4), and
wherein the first bit line contact structure has a shape which is widened toward the first bit line (see the shape of e.g. 3371 and 3372 in Fig. 4, which is narrower on its bottom than it is on its top near the bitlines 3642 and 3652).
Yeh does not explicitly teach wherein the first bit line contact structure comprises a same material as the first channel pattern.
Eom teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Yeh that the first bit line contact structure (e.g. “channel pad 190” of Eom, see e.g. Fig. 1A and para 55) comprises a same material (polysilicon) as the first channel pattern (e.g. “vertical channel 170”, se e.g. para 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Eom to the invention of Yeh. The motivation to do so is that the combination produces the predictable results forming the channel, the channel pad, the bitline contact, and the bitline out of known materials (see e.g. para 33, 55, 65-66).
Applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Yeh and Eom together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The semiconductor memory device of claim 1, wherein
the first stack structure includes first conductive layers (e.g. some or all of WL0 through WLn, and perhaps including SSL3 and/or GSL) of the conductive layers spaced vertically apart from each other (spaced apart by one or more of 411-415), and
the second stack structure includes second conductive layers (e.g. some or all of WL0 through WLn, and perhaps including SSL2 and/or GSL) of the conductive layers spaced vertically apart from each other (spaced apart by one or more of 411-415), and
wherein the first conductive layers and the second conductive layers are disposed at the same level (see e.g. Fig. 4).
3. The semiconductor memory device of claim 1, further comprising an isolation insulating layer disposed between the first stack structure and the second stack structure (comprising e.g. “isolation block” such as 261 or 262, see e.g. Figs. 2-2A and 4; or comprising e.g. isolation blocks such as 2315, 2325, 2335, 2345, 2355 in Figs. 23, 34; or comprising e.g. isolation blocks such as 4124, 4134, 4144, 4154, 2315, 2325, 2345, 2355 in e.g. Figs. 41, 45).
4. The semiconductor memory device of claim 1, further comprising: a first isolation structure (e.g. 261 in Fig. 2) disposed between the first memory layer and the second memory layer (when interpreting the “first memory layer” as e.g. the “data storage structure” such as 243a in the uppermost region of the device generally denoted as 210 of Fig. 2 and the “second memory layer” as e.g. the “data storage structure” such as 243a in the region of the device generally denoted by 230 of Fig. 2); and a second isolation structure (e.g. 262 in Fig. 2) disposed between the first channel pattern and the second channel pattern (when interpreting the “first channel pattern” as e.g. the “semiconductor film” such as 243b or the channel structure 243 itself in the uppermost region of the device generally denoted as 210 of Fig. 2 and the “second channel pattern” as e.g. the “semiconductor film” such as 243b or the channel structure 243 itself in the region of the device generally denoted by 230 of Fig. 2).
5. The semiconductor memory device of claim 1, wherein the first bit line contact structure extends from the first channel pattern to protrude beyond the first stack structure (see wherein 3371/3571 extends beyond the top of the stack structure e.g. GSL/411/WL0/412…/SSL3/420/430; the bit line contact structure itself 3371 and/or 3571 and/or plug 2051 connects to the semiconductor film 1731 and thus to the channel pattern).
6. The semiconductor memory device of claim 1, further comprising an upper contact (e.g. 3571 or 3572 in Fig. 4) disposed between the first bit line contact structure (e.g. 3371 or 3372; or 3371/2051 or 3372/2052) and the first bit line (e.g. 3642 or 3652).
7. The semiconductor memory device of claim 1, wherein the first stack structure includes
a first cell stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device; e.g. GSL/411/WL0/411/WL1/412…/415/SSL3 in Fig. 4; or GSL/411/WL0/412/WL1 in Fig. 4) and
a first select stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device; e.g. 413/WL2/414/WLn/415/SSL3 in Fig. 4, since it comprises a stack and a select string SSL3), and
wherein the second stack structure includes
a second cell stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device, as long as they are cells, e.g. connected to the memory storage; e.g. GSL/411/WL0/412/WL1/413…/415/SSL2 in Fig. 4; or GSL/411/WL0/412/WL1 in Fig. 4) and
a second select stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device; e.g. 413/WL2/414/WLn/415/SSL2 in Fig. 4, since it comprises a stack and a select string SSL2), and
wherein the semiconductor memory device further comprises an isolation structure (comprising e.g. “isolation block” such as 261 or 262, see e.g. Figs. 2-2A and 4; or comprising e.g. isolation blocks such as 2315, 2325, 2335, 2345, 2355 in Figs. 23, 34; or comprising e.g. isolation blocks such as 4124, 4134, 4144, 4154, 2315, 2325, 2345, 2355 in e.g. Figs. 41, 45) disposed between the first select stack structure and the second select stack structure (see e.g. Fig. 9, wherein the isolation blocks 925, 935, 945 separate adjacent regions from each other, e.g. separating SSL2 from SSL1 from SSL0).
Re claim 9, Yeh and Eom teach claim 7 and further teach wherein the first stack structure includes first conductive layers (e.g. some or all of WL0 through WLn, and perhaps including SSL3 and/or GSL) of the conductive layers stacked on the semiconductor substrate to be spaced apart from each other (spaced apart by one or more of 411-415), and the second stack structure includes second conductive layers (e.g. some or all of WL0 through WLn, and perhaps including SSL2 and/or GSL) of the conductive layers stacked on the semiconductor substrate to be spaced apart from each other (spaced apart by one or more of 411-415), and
wherein two or more line isolation structures are provided (see e.g. Fig. 9, wherein at least 945, 935, 925, and 915 are provided; see also Fig. 23 wherein many isolation blocks are etched and separated into plural parts; see also 2355, 4154, 2345, 4144, 2335, 4134, 2325, 4124, and 2315 in e.g. Fig. 41).
Yeh does not explicitly teach wherein a distance between the first conductive layers is smaller than a distance between the line isolation structures.
However, Yeh would have suggested as obvious to one of ordinary skill in the art at the time of invention wherein a distance between the first conductive layers is smaller than a distance between the line isolation structures (see Fig. 2, wherein 261 and 262 are separated by a distance that is greater two times than the elongated “radii” of the vertical structures, and Fig. 4 wherein the conductive layers such as two adjacent word lines are separated vertically by very small thicknesses of a layer within 411-415; using the scale shown in Fig. 4, one of ordinary skill in the art would have found it obvious to provide for the claimed limitation due to the relative dimensions shown and general knowledge in the art that the wordlines need not be separated by great distances).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Applicant has not disclosed that the claimed distances are for particular unobvious purposes, produce unexpected results, or are otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984);
To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Re claim 21, Yeh teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
21. A semiconductor memory device (see e.g. Figs. 4, 7, 36, 39) comprising:
a first stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device; e.g. GSL/411/WL0/411/WL1/412…/415/SSL3 in Fig. 4) and a second stack structure (this is a broad limitation that can be met by many different layers, or sub-combinations of layers, in many parts of the device; e.g. GSL/411/WL0/411/WL1/412…/415/SSL2 in Fig. 4);
a first vertical structure (e.g. 243a/243b/290 in Fig. 2A) having a sidewall in contact with the first stack structure (see Figs. 2A, 4, etc.),
the first vertical structure including a first memory layer (comprising e.g. “data storage structure” such as 243a) and a first channel pattern (comprising e.g. “semiconductor film” such as 243b, which is part of the “channel structure” 243, see e.g. col 8 lines 55-67);
a second vertical structure (e.g. 253a/253b/290 in Fig. 2A) having a sidewall in contact with the second stack structure (see Figs. 2A, 4, etc.), the second vertical structure including a second memory layer (comprising e.g. “data storage structure” such as 253a) and a second channel pattern (comprising e.g. “semiconductor film” such as 253b, which is part of the “channel structure” 253, see e.g. col 8 lines 55-67);
a first bit line contact structure (e.g. “first and second contacts 3371 or 3372” in Figs. 4 or 37) on the first vertical structure;
an upper contact (e.g. or 3571 or 3572) on the first bit line contact structure; and
a first bit line (e.g. 3642 or 3652, see e.g. Fig. 4; see “bit lines” in Fig. 7; see 741-744 in Fig. 8; see 3641-3643 and 3651-3653 in Fig. 9; etc.) on the upper contact,
wherein each of the first stack structure and the second stack structure includes conductive layers spaced vertically apart from each other see “word lines WL0, WL1… WLn,” which are spaced apart by “insulating strips 411-415”, see e.g. Fig. 4),
wherein the upper contact connects the first bit line and the first bit line contact structure (see e.g. Fig. 4),
Yeh does not explicitly teach wherein the first bit line contact structure and the first channel pattern include a first material, and wherein the upper contact includes a second material different from the first material.
Eom teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Yeh wherein the first bit line contact structure (e.g. “channel pad 190” of Eom, see e.g. Fig. 1A and para 55) and the first channel pattern (e.g. “vertical channel 170”, se e.g. para 33) include a first material (polysilicon), and wherein the upper contact (e.g. bitline contact 240, see e.g. para 65) includes a second material (e.g. tungsten or copper, see e.g. para 65) different from the first material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Eom to the invention of Yeh. The motivation to do so is that the combination produces the predictable results forming the channel, the channel pad, the bitline contact, and the bitline out of known materials (see e.g. para 33, 55, 65-66).
Applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Yeh and Eom together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
22. The semiconductor memory device of claim 21, wherein the first bit line contact structure is overlapping with the first channel pattern (see e.g. Fig. 4).
23. The semiconductor memory device of claim 22, wherein the first bit line contact structure is protruded from an upper surface of the first channel pattern (see e.g. Yeh Fig. 4; Eom Fig. 1A).
24. The semiconductor memory device of claim 21, wherein a width of an upper surface of the first bit line contact structure is greater than a width of the upper contact (see e.g. Fig. 4).
25. The semiconductor memory device of claim 21, wherein the first bit line contact structure is a portion of the channel pattern protruded from the first stack structure (if they are the same material, as suggested by Eom, the two parts can reasonably be considered portions of a single part).
26. The semiconductor memory device of claim 21, wherein the first material includes silicon (Si) or germanium (Ge) (polysilicon).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of Eom and US 2021/0159241 A1 (“Li”).
Yeh and Eom teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention the limitations of claim 7, as discussed above, but do not teach a dummy vertical structure penetrating the first stack structure or the second stack structure.
Li teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Yeh and Eom, a dummy vertical structure penetrating the first stack structure or the second stack structure (see e.g. para 163, “dummy vertical semiconductor channel 160” or e.g. para 118, “dummy memory stack structure 155” or e.g. para 118 for “dummy memory opening fill structure 158”; see e.g. Fig. 13B, 14B, etc.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Li to the invention of Yeh and Eom. The motivation to do so is that the combination produces the predictable results of using dummy structures that aid leakage current suppression (see e.g. para 163).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered Regarding the 102/103 art rejections, the arguments are moot in view of the new ground(s) of rejection. Regarding the objections to the specification, the previous objections to the drawings have been changed to objections to the specification and described in a bit more detail.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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