DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-12 and 21-28 are rejected under 35 U.S.C. 103 as being obvious over US 2020/0219972 A1 to Leendertz et al. (hereinafter “Leendertz” – previously cited reference).
Regarding claim 7, Leendertz discloses a semiconductor device, comprising:
a trench gate structure in a silicon carbide (SiC) semiconductor body, wherein at least a part of the trench gate structure extends along a first lateral direction (trench gate structure 150 extending along lateral direction in SiC body 100; Fig. 4C; paragraph [0080]);
a source region of a first conductivity type that adjoins the trench gate structure in a first segment (n-type source region 110 adjoining trench gate structure 150 in a first portion; Fig. 4C; paragraphs [0078]-[0080]);
a semiconductor region of a second conductivity type, wherein the semiconductor region comprises a first sub-region arranged below the source region in the first segment, and a second sub-region arranged in a second segment that adjoins the first segment (p-type region having body region 120 below source region 110 and adjoining shield portion 172; Fig. 4C; paragraphs [0080]-[0081]); and
a current spread region of the first conductivity type (n-type current spread region 137; Fig. 4C; paragraph [0082]), wherein a doping concentration profile defining the current spread region changes, along the first lateral direction, from a first doping concentration level in the first segment to a second doping concentration level in the second segment (first portion of n-type current spread region 137 may have different doping concentration profile than second portion of n-type current spread region 137 in a lateral direction; Fig. 4C; paragraphs [0030]-[0031]), wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends perpendicular to a lateral direction along which the trench gate structure is stripe-shaped (p-type region continuous through first left side and second right side portions of body 100 along an axis that extends perpendicular to a lateral direction along which a trench gate structure 150 is stripe-shaped; Figs. 4C & 4D), (ii) extends, in the first segment, between the source region and the current spread region (p-type region having a part in the first portion of body 100 between source region 110 and first portion of current spread region 137 adjoining trench gate structure 150; Fig. 4C), and (iii) extends, in the second segment, between the trench gate structure and the current spread region (p-type region having a part in the second portion of body 100 between trench gate structure 150 and second portion of current spread region 137; Fig. 4C), wherein the first sub-region and the second sub-region of the semiconductor region are arranged in a same mesa region and adjoin one another along a longitudinal direction of the trench gate structure (p-type region having body region 120 with first portion under source region 110 and second portion adjoining shield portion 172, where first and second portions are arranged in the same mesa 190 and adjoin one another along longitudinal direction of trench gate structure 150; Figs. 4A and 4C).
Leendertz fails to disclose wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends in parallel to a lateral direction along which the trench gate structure is stripe-shaped.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz in this manner given that power device active areas are typically much larger than the cell pitch in both directions, making the layout effectively symmetric on a macro scale and so parallel and perpendicular orientations would yield similar electrical performance.
Regarding claim 8, Leendertz discloses the semiconductor device of claim 7, wherein the second sub-region of the semiconductor region is arranged between the current spread region and the trench gate structure (shield portion 172 arranged between current spread region 137 and trench gate structure 150; Fig. 4C).
Regarding claim 9, Leendertz discloses the semiconductor device of claim 7, comprising: a pn junction between the semiconductor region and the current spread region (pn junction formed between the p-type body region 120 and n-type current spread region 137; Fig. 4C), wherein a vertical distance from the pn junction to a first surface of the SiC semiconductor body changes, along the first lateral direction, from a first vertical distance in the first segment to a second vertical distance in the second segment (vertical distance between pn junction and surface of SiC body 100 changes along a lateral direction between first and second portion of current spread region 137; Fig 4C).
Regarding claim 10, Leendertz discloses the semiconductor device of claim 7, wherein a vertical concentration profile of dopants defining the first sub-region of the semiconductor region is different from a vertical concentration profile of dopants defining the second sub-region of the semiconductor region (body region 120 has different doping concentration relative shield portion 172; paragraph [0081]).
Regarding claim 11, Leendertz discloses semiconductor device of claim 7, wherein the doping concentration profile defining the current spread region alternates, along the first lateral direction, between the first doping concentration level and the second doping concentration level (current spread region 137 alternates between n doping and n- doping along the lateral direction; Fig. 11B).
Regarding claim 12, Leendertz discloses the semiconductor device of claim 7, comprising: a pn junction between the semiconductor region and the current spread region (pn junction formed between the p-type body region 120 and n-type current spread region 137; Fig. 4C), wherein a vertical distance from the pn junction to a first surface of the SiC semiconductor body varies within the second segment (vertical distance between pn junction and surface of SiC body 100 changes along a lateral direction within second portion of current spread region 137; Fig 4C).
Regarding claim 21, Leendertz discloses the semiconductor device of claim 7, wherein the second sub-region of the semiconductor region is arranged between the trench gate structure and the second sub-region of the current spread region (diagonal line from trench gate structure 150 through portion of body region 120 adjacent shield portion 172 towards portion of current spread region 137; Fig. 4C).
Leendertz fails to explicitly disclose wherein, in the second segment, the second sub-region of the semiconductor region is arranged between the trench gate structure and the second sub-region of the current spread region.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz in this manner given that the second segment may be arbitrarily defined and the orientation claimed is already disclosed by Leendertz, just not in the second segment. Therefore, providing the disclosed orientation in the second segment would merely be a duplication or relocation of parts already disclosed.
Regarding claim 22, Leendertz discloses a semiconductor device, comprising:
a trench gate structure in a silicon carbide (SiC) semiconductor body (trench gate structure 150 in SiC body 100; Fig. 4C; paragraph [0080]);
a source region of a first conductivity type that adjoins the trench gate structure in a first segment (n-type source region 110 adjoining trench gate structure 150 in a first left side portion of body 100; Fig. 4C; paragraphs [0078]-[0080]);
a semiconductor region of a second conductivity type, wherein the semiconductor region comprises a first sub-region arranged below the source region in the first segment, and a second sub-region arranged in a second segment that adjoins the first segment (p-type region having body region 120 below source region 110 and adjoining shield portion 172 in second right side portion of body 100 adjacent first left side portion; Fig. 4C; paragraphs [0080]-[0081]); and
a current spread region of the first conductivity type (n-type current spread region 137; Fig. 4C; paragraph [0082]), wherein the current spread region comprises a first sub-region that adjoins the trench gate structure in the first segment at a vertical distance to a first surface of the SiC semiconductor body (first portion of current spread region 137 adjoining trench gate structure 150 and surface of SiC body 100; Fig. 4C), and a second sub-region that is spaced from the trench gate structure in the second segment at the vertical distance to the first surface by a lateral distance (second portion of current spread region 137 spaced apart from trench gate structure 150 in an adjacent iteration of the design pattern; Fig. 4C), wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends perpendicular to a lateral direction along which the trench gate structure is stripe-shaped (p-type region continuous through first left side and second right side portions of body 100 along an axis that extends perpendicular to a lateral direction along which a trench gate structure 150 is stripe-shaped; Figs. 4C & 4D), (ii) extends, in the first segment, between the source region and the first sub-region of the current spread region (p-type region having a part in the first left side portion of body 100 between source region 110 and first portion of current spread region 137 adjoining trench gate structure 150; Fig. 4C), and (iii) extends, in the second segment, between the trench gate structure and the second sub-region of the current spread region that is spaced from the trench gate structure in the second segment (p-type region having a part in the second right side portion of body 100 between trench gate structure 150 and second portion of current spread region 137 spaced apart from trench gate structure 150; Fig. 4C), wherein, in the second segment, the second sub-region of the semiconductor region is arranged between the trench gate structure and the second sub-region of the current spread region (diagonal line from trench gate structure 150 through portion of body region 120 adjacent shield portion 172 towards portion of current spread region 137; Fig. 4C).
Leendertz fails to disclose wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends in parallel to a lateral direction along which the trench gate structure is stripe-shaped; and wherein, in the second segment, the second sub-region of the semiconductor region is arranged between the trench gate structure and the second sub-region of the current spread region.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz to have the axis extend in parallel given that power device active areas are typically much larger than the cell pitch in both directions, making the layout effectively symmetric on a macro scale and so parallel and perpendicular orientations would yield similar electrical performance. Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz to have the second segment include the disclosed orientation given that the second segment may be arbitrarily defined and the orientation claimed is already disclosed by Leendertz, just not in the second segment. Therefore, providing the disclosed orientation in the second segment would merely be a duplication or relocation of parts already disclosed.
Regarding claim 23, Leendertz discloses the semiconductor device of claim 22, wherein the first sub-region and the second sub-region of the semiconductor region are arranged in a same mesa region and adjoin one another along a longitudinal direction of the trench gate structure (p-type region having body region 120 with first portion under source region 110 and second portion adjoining shield portion 172, where first and second portions are arranged in the same mesa 190 and adjoin one another along longitudinal direction of trench gate structure 150; Figs. 4A and 4C).
Regarding claim 24, Leendertz discloses the semiconductor device of claim 22, wherein a pn junction between a p-type region and the current spread region includes a first section extending along a direction perpendicular to a longitudinal direction of the trench gate structure (SRO; other part of p-type region of body 100 has a p-n junction with current spread region 137 extending in vertical direction; Fig. 4C) and a second section extending along the longitudinal direction of the trench gate structure (p-n junction between p-type body region 120 and n-type current spread region 137 extends in longitudinal direction; Fig. 4C).
Leendertz fails to explicitly disclose a first section of the pn junction extending along a direction perpendicular to a longitudinal direction of the trench gate structure.
However, Leendertz already discloses another part of p-type region of body 100 has a p-n junction with current spread region 137 extending in vertical direction (see Fig. 4C).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz to have a portion of the p-n junction in a vertical direction in order to potentially provide improved current spreading, vertical junction segments that distribute the depletion region more uniformly, and limitation of current in fault conditions. Further, this feature is not new in the prior art as evidenced by US 2009/0078971 A1 to Treu et al. and US 2011/0254016 A1 to Ryu.
Regarding claim 25, Leendertz discloses a semiconductor device, comprising:
a trench gate structure in a silicon carbide (SiC) semiconductor body, wherein at least a part of the trench gate structure extends along a first lateral direction (trench gate structure 150 in SiC body 100 and extending in lateral direction; Fig. 4C; paragraph [0080]);
a source region of a first conductivity type that adjoins the trench gate structure in a first segment (n-type source region 110 adjoining trench gate structure 150 in a first left side portion of body 100; Fig. 4C; paragraphs [0078]-[0080]);
a semiconductor region of a second conductivity type, wherein the semiconductor region comprises a first sub-region arranged below the source region in the first segment, and a second sub-region arranged in a second segment that adjoins the first segment (p-type region having body region 120 below source region 110 and adjoining shield portion 172 in second right side portion of body 100 adjacent first left side portion; Fig. 4C; paragraphs [0080]-[0081]); and
a current spread region of the first conductivity type (n-type current spread region 137; Fig. 4C; paragraph [0082]), wherein a doping concentration profile defining the current spread region changes, along the first lateral direction, from a first doping concentration level in the first segment to a second doping concentration level in the second segment (first portion of n-type current spread region 137 may have different doping concentration profile than second portion of n-type current spread region 137 in a lateral direction; Fig. 4C; paragraphs [0030]-[0031]), wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends perpendicular to a lateral direction along which the trench gate structure is stripe-shaped (p-type region continuous through first left side and second right side portions of body 100 along an axis that extends perpendicular to a lateral direction along which a trench gate structure 150 is stripe-shaped; Figs. 4C & 4D), (ii) extends, in the first segment, between the source region and the current spread region (p-type region having a part in the first left side portion of body 100 between source region 110 and first portion of current spread region 137 adjoining trench gate structure 150; Fig. 4C), and (iii) extends, in the second segment, between the trench gate structure and the current spread region (p-type region having a part in the second right side portion of body 100 between trench gate structure 150 and second portion of current spread region 137; Fig. 4C), wherein a pn junction between a p-type region and the current spread region includes a first section extending along a direction perpendicular to a longitudinal direction of the trench gate structure (SRO; other part of p-type region of body 100 has a p-n junction with current spread region 137 extending in vertical direction; Fig. 4C) and a second section extending along the longitudinal direction of the trench gate structure (p-n junction between p-type body region 120 and n-type current spread region 137 extends in longitudinal direction; Fig. 4C).
Leendertz fails to disclose wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends in parallel to a lateral direction along which the trench gate structure is stripe-shaped; and a first section of the pn junction extending along a direction perpendicular to a longitudinal direction of the trench gate structure.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz to have the axis extend in parallel given that power device active areas are typically much larger than the cell pitch in both directions, making the layout effectively symmetric on a macro scale and so parallel and perpendicular orientations would yield similar electrical performance. Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz to have a portion of the p-n junction in a vertical direction in order to potentially provide improved current spreading, vertical junction segments that distribute the depletion region more uniformly, and limitation of current in fault conditions. This feature is not new in the prior art as evidenced by US 2009/0078971 A1 to Treu et al. and US 2011/0254016 A1 to Ryu.
Regarding claim 26, Leendertz discloses the semiconductor device of claim 25, wherein the first sub-region and the second sub-region of the semiconductor region are arranged in a same mesa region and adjoin one another along a longitudinal direction of the trench gate structure (p-type region having body region 120 with first portion under source region 110 and second portion adjoining shield portion 172, where first and second portions are arranged in the same mesa 190 and adjoin one another along longitudinal direction of trench gate structure 150; Figs. 4A and 4C).
Regarding claim 27, Leendertz discloses the semiconductor device of claim 25, wherein the second sub-region of the semiconductor region is arranged between the trench gate structure and the second sub-region of the current spread region (diagonal line from trench gate structure 150 through portion of body region 120 adjacent shield portion 172 towards portion of current spread region 137; Fig. 4C).
Leendertz fails to explicitly disclose wherein, in the second segment, the second sub-region of the semiconductor region is arranged between the trench gate structure and the second sub-region of the current spread region.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Leendertz in this manner given that the second segment may be arbitrarily defined and the orientation claimed is already disclosed by Leendertz, just not in the second segment. Therefore, providing the disclosed orientation in the second segment would merely be a duplication or relocation of parts already disclosed.
Regarding claim 28, Leendertz discloses the semiconductor device of claim 25, wherein a vertical concentration profile of dopants defining the first sub-region of the semiconductor region is different from a vertical concentration profile of dopants defining the second sub-region of the semiconductor region (body region 120 has different doping concentration relative shield portion 172; paragraph [0081]).
Allowable Subject Matter
Claims 1-6 are allowed.
Regarding amended claim 1, Leendertz discloses a semiconductor device, comprising: a trench gate structure in a silicon carbide (SiC) semiconductor body (trench gate structure 150 in SiC body 100; Fig. 4C; paragraph [0080]); a source region of a first conductivity type that adjoins the trench gate structure in a first segment (n-type source region 110 adjoining trench gate structure 150 in a first left side portion of body 100; Fig. 4C; paragraphs [0078]-[0080]); a semiconductor region of a second conductivity type, wherein the semiconductor region comprises a first sub-region arranged below the source region in the first segment, and a second sub-region arranged in a second segment that adjoins the first segment (p-type region having body region 120 below source region 110 and adjoining shield portion 172 in second right side portion of body 100 adjacent first left side portion; Fig. 4C; paragraphs [0080]-[0081]); and a current spread region of the first conductivity type (n-type current spread region 137; Fig. 4C; paragraph [0082]), wherein the current spread region comprises a first sub-region that adjoins the trench gate structure in the first segment at a vertical distance to a first surface of the SiC semiconductor body (first portion of current spread region 137 adjoining trench gate structure 150 and surface of SiC body 100; Fig. 4C), and a second sub-region that is spaced from the trench gate structure in the second segment at the vertical distance to the first surface by a lateral distance (second portion of current spread region 137 spaced apart from trench gate structure 150 in an adjacent iteration of the design pattern; Fig. 4C), wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends perpendicular to a lateral direction along which the trench gate structure is stripe-shaped (p-type region continuous through first left side and second right side portions of body 100 along an axis that extends perpendicular to a lateral direction along which a trench gate structure 150 is stripe-shaped; Figs. 4C & 4D), (ii) extends, in the first segment, between the source region and the first sub-region of the current spread region (p-type region having a part in the first left side portion of body 100 between source region 110 and first portion of current spread region 137 adjoining trench gate structure 150; Fig. 4C), and (iii) extends, in the second segment, between the trench gate structure and the second sub-region of the current spread region that is spaced from the trench gate structure in the second segment (p-type region having a part in the second right side portion of body 100 between trench gate structure 150 and second portion of current spread region 137 spaced apart from trench gate structure 150; Fig. 4C), wherein the first sub-region and the second sub-region of the semiconductor region are arranged in a same mesa region and adjoin one another along the longitudinal direction of the stripe-shaped trench gate structure (p-type region having body region 120 with first portion under source region 110 and second portion adjoining shield portion 172, where first and second portions are arranged in the same mesa 190 and adjoin one another along longitudinal direction of trench gate structure 150; Figs. 4A and 4C), and wherein a pn junction between the semiconductor region and the current spread region includes a second section extending along the longitudinal direction of the stripe-shaped trench gate structure (p-n junction between p-type body region 120 and n-type current spread region 137 extends in longitudinal direction; Fig. 4C).
Leendertz and each of the references uncovered fails to collectively disclose wherein the semiconductor region (i) is continuous through the first segment and the second segment along an axis that extends in parallel to a lateral direction along which the trench gate structure is stripe-shaped, wherein, in the second segment, the second sub-region of the semiconductor region is arranged between the trench gate structure and the second sub-region of the current spread region, wherein a pn junction between the semiconductor region and the current spread region includes a first section extending along a direction perpendicular to the longitudinal direction of the stripe-shaped trench gate structure. While Leendertz discloses the vast majority of each of these limitations and accordingly renders obvious each of these limitations, there does not appear to be a clear motivation to combine each of the associated modifications to Leendertz. Similarly, there does not appear to be a clear motivation to combine any number of other prior art references that would modify Leendertz, including US 2009/0078971 A1 to Treu et al. and US 2011/0254016 A1 to Ryu.
Claims 2-6 are allowable for depending upon allowable claim 1.
Response to Arguments
Applicant's arguments filed May 13, 2026 have been fully considered. Applicant amended claims 1 and 7, added new claims 21-28 and provided corresponding arguments. Examiner agrees that amended claim 1 is allowable. However, amended claim 7 and new claims 21-28 are rejected under 35 USC 103 using Leendertz for the reasons outlined above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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