DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 09/03/2025.
Applicant’s amendments filed 09/03/2025 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 3, 6, 9-10, 14, and 17; cancellation of claims 2, 7-8, 15, and 18-19; and the addition of new claims 21 and 22.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 9-10, 13-14, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0230429 to Miyamoto et al. (hereinafter Miyamoto) in view of Gao et al. (CN 104637991 A, hereinafter Gao).
With respect to claim 1, Miyamoto discloses a semiconductor device (e.g., hetero-junction field effect transistor (HFET)) (Miyamoto, Figs. 2-3, 6, ¶0001, ¶0086-¶0148, ¶0161-¶0204), comprising:
a substrate (110) (Miyamoto, Figs. 2-3, 6, ¶0105-¶0107);
a multilayer semiconductor layer (111) (Miyamoto, Figs. 2-3, 6, ¶0106, ¶0162, ¶0183, ¶0195) located on a side of the substrate (110);
a source (112) (Miyamoto, Figs. 2-3, 6, ¶0105, ¶0162-¶0164, ¶0183-¶0186, ¶0195-¶0198), a gate (113) and a drain (114) located on a side, away from the substrate (110), of the multilayer semiconductor layer (111), wherein the gate (113) is located between the source (112) and the drain (114); and
a field plate structure (118) (Miyamoto, Fig. 6, ¶0089-¶0091, ¶0113, ¶0115-¶0121, ¶0132-¶0133, ¶0135-¶0142) located on the side, away from the substrate (110), of the multilayer semiconductor layer (111), wherein the field plate structure (118) comprises a main body portion (119, having a length Lfp2, shown in Fig. 2) and a first extension portion (e.g., gate overlapping portion and a portion between the gate and the source); the main body portion (119) is located between the gate (113) and the drain (114); the first extension portion is connected to the main body portion (119), and the first extension portion is located on a side, away from the multilayer semiconductor layer (111), of the gate (113); and a vertical projection of the first extension portion on a plane where the substrate (110) is located at least partially overlaps a vertical projection of the gate (110) on the plane where the substrate (110) is located,
the first extension portion (e.g., the gate overlapping portion and the portion between the gate and the source) (Miyamoto, Fig. 6, ¶0089-¶0091, ¶0113, ¶0115-¶0121, ¶0133, ¶0135-¶0142) comprises a first part (e.g., the gate overlapping portion) and a second part (e.g., a portion of the field plate 118 extending between the gate and the source 112), a vertical projection of the first part on the plane where the substrate (110) is located partially overlaps the vertical projection of the gate (113) on the plane where the substrate (110) is located, the second part extends toward a direction from the gate (113) to the source (112) to a place between the gate (113) and the source (112) and extends toward the multilayer semiconductor layer (111), and the vertical projection of the first part on the plane where the substrate (110) is located and a vertical projection of the second part on the plane where the substrate (110) is located are adjacent without overlapping,
along a direction from the gate to the drain (Miyamoto, Fig. 6, ¶0190), an extension length of the second part between the gate and the source is L3, and a distance between the gate and the source is LGS.
Further, Miyamoto does not specifically disclose wherein in an extending direction of the gate, a width of the first extension portion and a width of the main body portion are the same, wherein 0<L3<0.5*LGS.
However, Gao teaches forming a transistor (e.g., high electron mobility transistor (HEMT)) (Gao, Figs. 4A, 6, 7D, ¶0002, ¶0025-¶0038, ¶0045-¶0049) comprising a source field plate (51) (Gao, Figs. 4A, 6, 7D, ¶0038-¶0039, ¶0041, ¶0045-¶0047) located on a side of the gate (41) and including a main body portion (e.g., a portion between the gate 41 and the drain 22) and a first extension portion (e.g., a portion overlapping gate 41 and extending between the gate 41 and the source 21), wherein in an extending direction (e.g., vertical direction in Fig. 7D) of the gate (41), a width of the first extension portion and a width of the main body portion are the same, and wherein along a direction from the gate (41) to the drain (22), an extension length (e.g., LSFP2 -LGFP2=0.3 mm- 0.2 mm=0.1 mm) (Gao, Figs. 4A, 6, 7D, ¶0037-¶0038) of the second part between the gate (41) and the source (21) is L3 (0.1 mm), and a distance (e.g., LGS -LGFP2=0.5 mm- 0.2 mm=0.3 mm) between the gate (41) and the source (21) is LGS (0.2 mm), wherein 0<L3<0.5*LGS (0< L3=0.1 mm <0.5*0.3 mm). In Gao, the source field plate prevents damage of the device during breakdown to provide stability of the HEMT device for high power application (Gao, Figs. 4A, 6, 7D, ¶0009-¶0011).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Miyamoto by forming the source field plate extending between the gate and the source as taught by Gao, wherein the extension length of the source field plate between the gate and the source is less than a distance between the gate and the source as taught by Gao to have the semiconductor device, wherein in an extending direction of the gate, a width of the first extension portion and a width of the main body portion are the same, and wherein 0<L3<0.5*LGS, in order to provide improved source field plate to prevent damage of the device during breakdown and to provide stability of the HEMT device for high power application (Gao, ¶0009-¶0011, ¶0037, ¶0038).
Regarding claim 3, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto discloses the semiconductor device, wherein along the direction from the gate (113) to the drain (114), an extension length of the first part is L1 (e.g., Lfd=0.25 mm, 0.5 mm, or 0.75 mm; or 0≤Lfd≤0.5 mm) (Miyamoto, Figs. 2-3, 6, ¶0108-¶0117, ¶0173-¶0176, ¶0186-¶0189), and an extension length of the gate is LG (e.g., Lg=0.5 mm), but does not specifically disclose that 0.1*LG<L1<0.65*LG.
However, Miyamoto teaches a specific example, wherein 0≤Lfd≤0.5 mm (Miyamoto, Figs. 2-3, 6, ¶0173-¶0176), to obtain a high gain for a high frequency region of 5GHz or more.
Thus, a person of ordinary skill in the art would recognize that with gate length Lg of 0.5 mm, the overlapping region would have the extension length L1 of the first part in the range 0.05<L1<0.325. This rnage lies inside the range 0≤Lfd≤0.5 mm of Miyamoto.
Further, Miyamoto recognizes that the length of the overlapping region between the gate and the field plate impacts gain of the device at specific frequency region. Thus, the length of the overlapping region between the gate and the field plate is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the length of the overlapping region between the gate and the field plate as Miyamoto has identified the length of the overlapping region as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific relation 0.1*LG<L1<0.65*LG, in order to provide a transistor having a high gain for a high frequency region as taught by Miyamoto (¶0175-¶0176) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Miyamoto/Gao by optimizing the length of the overlapping region between the gate and the field plate as taught by Miyamoto to have the semiconductor device, wherein along a direction from the gate to the drain, 0.1*LG<L1<0.65*LG, in order to provide improved semiconductor device having a high gain for a high frequency region (Miyamoto, ¶0022, ¶0047, ¶0115-¶0117, ¶0173-¶0176).
Regarding claim 4, Miyamoto in view of Gao discloses the semiconductor device according to claim 3. Further, Miyamoto discloses the semiconductor device, wherein 400nm<LG<2000nm (e.g., Lg=0.5 mm (500 nm) (Miyamoto, Figs. 2-3, 6, ¶0173-¶0176) that is the claimed range between 400 nm and 2000 nm). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Regarding claim 5, Miyamoto in view of Gao discloses the semiconductor device according to claim 3. Further, Miyamoto discloses the semiconductor device, wherein along the direction from the gate (113) to the drain (114), an extension length of the main body portion is L2 (e.g., Lfp2=1.0 mm) (Miyamoto, Figs. 2-3, 6, ¶0132-¶0133, ¶0173-¶0176, ¶0186-¶0189), wherein L1<L2 (e.g., with L1 of 0.25 mm corresponding the overlapping length Lfd and L2 of 1.0 mm corresponding the length Lfp2, L1<L2) (Miyamoto, Figs. 2-3, 6, ¶0186, ¶0189). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Regarding claim 6, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto discloses the semiconductor device, wherein along the direction from the gate (113) to the drain (114), an extension length of the first part is L1 (e.g., Lfd) (Miyamoto, Figs. 2-3, 6, ¶0132, ¶0133, ¶0201-¶0202), and an extension length of the main body portion is L2 (e.g., Lfp2), wherein L1<L2 (e.g., an example, wherein Lfd=0.75 mm and Lfp2= 1 mm).
Regarding claim 9, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto discloses the semiconductor device, wherein along the direction from the gate to the drain, an extension length of the main body portion is L2 (e.g., Lfp2) (e.g., an example, wherein Lfp2= 1 mm) (Miyamoto, Figs. 2-3, 6, ¶0132, ¶0133, ¶0186-¶0189), but does not specifically disclose the semiconductor device, wherein L3<L2.
However, Gao teaches that along the direction from the gate (41) to the drain (22), an extension length of the main body portion (e.g., LSFP1 -LGFP1=0.5 mm- 0.2 mm=0.3 mm) (Gao, Figs. 4A, 6, 7D, ¶0037-¶0038) is L2, wherein L3 (0.1 mm) < L2 (0.3 mm).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Miyamoto/Gao by forming the field plate extending between the gate and the drain as taught by Gao, wherein the extension length of the field plate between the gate and the drain is greater than the extension length of the field plate between the gate and the source as taught by Gao to have the semiconductor device, wherein L3<L2, in order to provide improved field plate to prevent damage of the device during breakdown and to provide stability of the HEMT device for high power application (Gao, ¶0009-¶0011, ¶0037, ¶0038).
Regarding claim 10, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto discloses the semiconductor device, wherein along the direction from the gate (113) to the drain (114), an extension length of the main body portion is L2 (e.g., Lfp2) (Miyamoto, Figs. 2-3, 6, ¶0132, ¶0134, ¶0186-¶0189), and a distance between the gate and the drain is LGD (e.g., LGD=3.5 mm) (Miyamoto, Figs. 2-3, 6, ¶0215), but does not specifically disclose that L2<0.6*LGD.
However, Miyamoto teaches a specific example, wherein Lfp2=1.0 mm (Miyamoto, Figs. 2-3, 6, ¶0134, ¶0215), to obtain a high gain for a high frequency region.
Thus, a person of ordinary skill in the art would recognize that with a distance between the gate and the drain LGD of 3.5 mm and the extension length of the main body portion L2 of about 1.0 mm, the relation L2<0.6*LGD would be satisfied.
Further, Miyamoto recognizes that the dimension of the field plate impacts gain of the device at specific frequency region. Thus, the dimension of the field plate is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the dimension of the field plate including an extension length of the main body portion as Miyamoto has identified the dimension of the field plate as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific relation L2<0.6*LGD, in order to provide a transistor having a high gain for a high frequency region as taught by Miyamoto (¶0175-¶0176) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Miyamoto/Gao by optimizing the dimension of the field plate including an extension length of the main body portion as taught by Miyamoto to have the semiconductor device, wherein along a direction from the gate to the drain, L2<0.6*LGD, in order to provide improved semiconductor device having a high gain for a high frequency region (Miyamoto, ¶0022, ¶0047, ¶0115-¶0117, ¶0173-¶0176).
Regarding claim 13, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto discloses the semiconductor device, wherein the semiconductor device further comprises at least one dielectric layer (117) (Miyamoto, Figs. 2-3, 6, ¶0109, ¶0165, ¶0188, ¶0200), and the dielectric layer (117) covers an upper surface and a side surface of the gate (113).
Regarding claim 14, Miyamoto in view of Gao discloses the semiconductor device according to claim 13. Further, Miyamoto discloses the semiconductor device, wherein along a direction perpendicular to the substrate (110), a thickness L5 (e.g., 150 nm or 200 nm) (Miyamoto, Figs. 2-3, 6, ¶0109, ¶0138, ¶0165, ¶0188, ¶0200) of the dielectric layer (117) on the upper surface of the gate (113) satisfies 50 nm < L5< 300 nm; and along the direction from the gate (113) to the drain (114), an extension length L6 (e.g., d3, corresponding to the thickness of the dielectric layer 117 that is 150 nm or 200 nm) of the dielectric layer (117) on the side surface of the gate (113) satisfies 50 nm <L6< 300 nm (note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Regarding claim 16, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto discloses the semiconductor device, wherein the field plate structure (118) further comprises a second extension portion (e.g., extending portion of the field plate 118 between the gate 113 and the source 112) (Miyamoto, Fig. 6, ¶0190), the second extension portion comprises one or more extension branches located between the gate (113) and the source (112), one end of each extension branch is connected to the first extension portion (e.g., gate overlapping portion of the field plate 118), another end of each extension branch is electrically connected to the source (112).
With respect to claim 17, Miyamoto discloses a preparation method of a semiconductor device (e.g., hetero-junction field effect transistor (HFET)) (Miyamoto, Figs. 2-3, 6, ¶0001, ¶0086-¶0148, ¶0161-¶0204), comprising:
providing a substrate (110) (Miyamoto, Figs. 2-3, 6, ¶0105-¶0107);
preparing a multilayer semiconductor layer (111) (Miyamoto, Figs. 2-3, 6, ¶0106, ¶0162, ¶0183, ¶0195) on a side of the substrate (110);
preparing a source (112) (Miyamoto, Figs. 2-3, 6, ¶0105, ¶0162-¶0164, ¶0183-¶0186, ¶0195-¶0198), a gate (113) and a drain (114) on a side, away from the substrate (110), of the multilayer semiconductor layer (111), wherein the gate (113) is located between the source (112) and the drain (114); and
preparing a field plate structure (118) (Miyamoto, Figs. 2-3, 6, ¶0089-¶0091, ¶0113, ¶0115-¶0121, ¶0135-¶0142) on the side, away from the substrate (110), of the multilayer semiconductor layer (111), wherein the field plate structure (118) comprises a main body portion (119) and a first extension portion (e.g., gate overlapping portion); the main body portion (119) is located between the gate (113) and the drain (114); the first extension portion is connected to the main body portion (119), and the first extension portion is located on a side, away from the multilayer semiconductor layer (111), of the gate (113); and a vertical projection of the first extension portion on a plane where the substrate (110) is located at least partially overlaps a vertical projection of the gate (110) on the plane where the substrate (110) is located,
the first extension portion (e.g., the gate overlapping portion and the portion between the gate and the source) (Miyamoto, Fig. 6, ¶0089-¶0091, ¶0113, ¶0115-¶0121, ¶0133, ¶0135-¶0142) comprises a first part (e.g., the gate overlapping portion) and a second part (e.g., a portion of the field plate 118 extending between the gate and the source 112), a vertical projection of the first part on the plane where the substrate (110) is located partially overlaps the vertical projection of the gate (113) on the plane where the substrate (110) is located, the second part extends toward a direction from the gate (113) to the source (112) to a place between the gate (113) and the source (112) and extends toward the multilayer semiconductor layer (111), and the vertical projection of the first part on the plane where the substrate (110) is located and a vertical projection of the second part on the plane where the substrate (110) is located are adjacent without overlapping,
along a direction from the gate to the drain (Miyamoto, Fig. 6, ¶0190), an extension length of the second part between the gate and the source is L3, and a distance between the gate and the source is LGS.
Further, Miyamoto does not specifically disclose wherein in an extending direction of the gate, a width of the first extension portion and a width of the main body portion are the same, wherein 0<L3<0.5*LGS.
However, Gao teaches forming a transistor (e.g., high electron mobility transistor (HEMT)) (Gao, Figs. 4A, 6, 7D, ¶0002, ¶0025-¶0038, ¶0045-¶0049) comprising a source field plate (51) (Gao, Figs. 4A, 6, 7D, ¶0038-¶0039, ¶0041, ¶0045-¶0047) located on a side of the gate (41) and including a main body portion (e.g., a portion between the gate 41 and the drain 22) and a first extension portion (e.g., a portion overlapping gate 41 and extending between the gate 41 and the source 21), wherein in an extending direction (e.g., vertical direction in Fig. 7D) of the gate (41), a width of the first extension portion and a width of the main body portion are the same, and wherein along a direction from the gate (41) to the drain (22), an extension length (e.g., LSFP2 -LGFP2=0.3 mm- 0.2 mm=0.1 mm) (Gao, Figs. 4A, 6, 7D, ¶0037-¶0038) of the second part between the gate (41) and the source (21) is L3 (0.1 mm), and a distance (e.g., LGS -LGFP2=0.5 mm- 0.2 mm=0.3 mm) between the gate (41) and the source (21) is LGS (0.2 mm), wherein 0<L3<0.5*LGS (0< L3=0.1 mm <0.5*0.3 mm). In Gao, the source field plate prevents damage of the device during breakdown to provide stability of the HEMT device for high power application (Gao, Figs. 4A, 6, 7D, ¶0009-¶0011).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the preparation method of a semiconductor device of Miyamoto by forming the source field plate extending between the gate and the source as taught by Gao, wherein the extension length of the source field plate between the gate and the source is less than a distance between the gate and the source as taught by Gao to have the semiconductor device, wherein in an extending direction of the gate, a width of the first extension portion and a width of the main body portion are the same, and wherein 0<L3<0.5*LGS, in order to provide improved source field plate to prevent damage of the device during breakdown and to provide stability of the HEMT device for high power application (Gao, ¶0009-¶0011, ¶0037, ¶0038).
Regarding claim 20, Miyamoto in view of Gao discloses the preparation method of a semiconductor device according to claim 17. Further, Miyamoto discloses the preparation method of a semiconductor device, wherein before preparing the field plate structure (e.g., the field plate 118 is formed on the second insulating layer 117) (Miyamoto, Figs. 2-3, 6, ¶0108-¶0114) on the side, away from the substrate (110) of the multilayer semiconductor layer (111), the method further comprises: preparing at least one dielectric layer (115/117) (Miyamoto, Figs. 2-3, 6, ¶0108-¶0114, ¶0163-¶0165, ¶0184-¶0190, ¶0196-¶0200) on the side, away from the substrate (110) of the multilayer semiconductor layer (111), wherein the dielectric layer (115/117) covers an upper surface and a side surface of the gate (113).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0230429 to Miyamoto in view of Gao (CN 104637991) as applied to claim 1, and further in view of Wu (US 2011/0114997).
Regarding claim 11, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto discloses the semiconductor device, wherein the multilayer semiconductor layer (11) (Miyamoto, Figs. 2-3, 6, ¶0004, ¶0106, ¶0162, ¶0183, ¶0195) comprises a buffer layer (131), a channel layer (132) and a barrier layer (133) arranged in sequence, and a two-dimensional electron gas (e.g., heterostructure GaN/AlGaN provides a two-dimensional electron gas) is formed in the multilayer semiconductor layer, but does not specifically disclose a nucleation layer.
However, Wu teaches forming a nucleation layer (Wu, Figs.1-2, ¶0049-¶0056), to reduce lattice mismatch between the substrate and the overlying the GaN layer to improve performance characteristics of the device (Wu, Figs.1-2, ¶0051).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Miyamoto/Gao by forming a nucleation layer between the substrate and the buffer layer taught by Wu to have the semiconductor device, wherein the multilayer semiconductor layer comprises a nucleation layer, in order to reduce lattice mismatch between the substrate and the overlying the GaN layer to improve performance characteristics of the device (Wu, ¶0051-¶0056).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0230429 to Miyamoto in view of Gao (CN 104637991) and Wu (US 2011/0114997) as applied to claim 11, and further in view of Yamada (US 2019/0123152).
Regarding claim 12, Miyamoto in view of Gao and Wu discloses the semiconductor device according to claim 11. Further, Miyamoto discloses the semiconductor device, wherein along a direction perpendicular to the substrate, a distance L4 between the first extension portion (118) and the channel layer (133) is a sum of a thickness of the insulating layer (117) (Miyamoto, Figs. 2-3, 6, ¶0183-¶0189), a thickness of the gate electrode (113/116), and a thickness of the barrier layer (133), but does not specifically disclose the semiconductor device, wherein along a direction perpendicular to the substrate, a distance L4 between the first extension portion and the channel layer satisfies 300 nm<L4<2000 nm.
However, Yamada teaches forming a field plate (34a/34b) (Yamada, Figs. 2A-2B, ¶0024, ¶0031, ¶0032) extending over the gate electrode (33) and having a thickness smaller than that of the gate electrode. Specifically, the thickness of the field plate is about 0.21 mm and a thickness of the gate electrode (33) is between 0. 3 mm and 0.7 mm. The field plate (34) (Yamada, Figs. 2A-2B, ¶0024, ¶0032, ¶0045) is connected to the source electrode (32) to stabilize the electrical potential.
Thus, a person of ordinary skill in the art would recognize that with the thickness of the insulating layer (117) of 150 nm (Miyamoto, Figs. 2-3, 6, ¶0183-¶0189) and a thickness of the barrier layer (133) of 30 nm, and with a thickness of the gate electrode between 0. 3 mm (300 nm) and 0.7 mm (700 nm) (Yamada, Figs. 2A-2B, ¶0024), a distance L4 between the first extension portion and the channel layer would be between 480 nm and 880 nm. This range lies inside the claimed range between 300 nm and 2000 nm.
In Miyamoto, the insulating layer (117) (Miyamoto, Figs. 2-3, 6, ¶0108-¶0111) is provided as a surface protective film to effectively suppress collapse in the transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Miyamoto/Gao/Wu by forming a field plate transistor having an insulating layer between the field plate and the gate electrode and having specific thickness taught by Miyamoto, and forming the gate electrode having a specific thickness as taught by Yamada to have the semiconductor device, wherein along a direction perpendicular to the substrate, a distance L4 between the first extension portion and the channel layer satisfies 300 nm<L4<2000 nm, in order to provide improved transistor with effectively suppressed collapse in the transistor under high frequency operation; and to stabilize the electrical potential to improve performance characteristics of the device (Miyamoto, ¶0047, ¶0107-¶0111, ¶0114; Yamada, ¶0024, ¶0045).
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0230429 to Miyamoto in view of Gao (CN 104637991) as applied to claim 1 (claim 17), and further in view of Marui et al. (US 20090242937, hereinafter Marui).
Regarding claim 21, Miyamoto in view of Gao discloses the semiconductor device according to claim 1. Further, Miyamoto does not specifically disclose the semiconductor device, wherein along the direction from the gate to the drain, a thickness of the main body portion is uniform, and the thickness of the main body portion is greater than a thickness of the gate.
However, Marui teaches forming a HEMT device (Marui, Fig. 6, ¶0013-¶0016, ¶0026-¶0050) comprising a field plate (43) having a main body portion between the gate (31) and the drain (29a) (Marui, Fig. 6, ¶0040-¶0044) of uniform thickness that is greater than a thickness of the gate, to reduce a current collapse in HEMT device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Miyamoto/Gao by forming a field plate having uniform thickness between the gate and the drain as taught by Marui to have the semiconductor device, wherein along the direction from the gate to the drain, a thickness of the main body portion is uniform, and the thickness of the main body portion is greater than a thickness of the gate, tin order o reduce a current collapse in HEMT device (Marui, ¶0013-¶0016, ¶0036, ¶0044).
Regarding claim 22, Miyamoto in view of Gao discloses the preparation method of a semiconductor device according to claim 17. Further, Miyamoto does not specifically disclose that along the direction from the gate to the drain, a thickness of the main body portion is uniform, and the thickness of the main body portion is greater than a thickness of the gate.
However, Marui teaches forming a HEMT device (Marui, Fig. 6, ¶0013-¶0016, ¶0026-¶0050) comprising a field plate (43) having a main body portion between the gate (31) and the drain (29a) (Marui, Fig. 6, ¶0040-¶0044) of uniform thickness that is greater than a thickness of the gate, to reduce a current collapse in HEMT device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the preparation method of a semiconductor device of Miyamoto/Gao by forming a field plate having uniform thickness between the gate and the drain as taught by Marui to have the preparation method of a semiconductor device, wherein along the direction from the gate to the drain, a thickness of the main body portion is uniform, and the thickness of the main body portion is greater than a thickness of the gate, tin order o reduce a current collapse in HEMT device (Marui, ¶0013-¶0016, ¶0036, ¶0044).
Response to Arguments
Applicant's arguments filed 09/03/2025 have been fully considered but they are not persuasive.
In response to Applicant’s arguments that “Miyamoto does not disclose the features "in an extending direction of the gate, a width of the first extension portion (including a first part and a second part) and a width of the main body portion are the same" and "along a direction from the gate to the drain, an extension length of the second part between the gate and the source is L3, and a distance between the gate and the source is LGS, wherein 0<L3<0.5*LGS" as recited in claim 1”, the examiner submits that newly discovered prior art by Gao (Fig. 7D) teaches the features "in an extending direction of the gate, a width of the first extension portion (including a first part and a second part) and a width of the main body portion are the same" and "along a direction from the gate to the drain, an extension length of the second part between the gate and the source is L3, and a distance between the gate and the source is LGS, wherein 0<L3<0.5*LGS" (Fig. 6), as required by claim 1. Thus, the above Applicant’s arguments are not persuasive, and the rejection of claim 1 under 35 USC 103 over Miyamoto in view of Gao is maintained.
In response to Applicant’s arguments that “Miyamoto fails to disclose "along the direction from the gate to the drain, a thickness of the main body portion is uniform, and the thickness of the main body portion is greater than a thickness of the gate" as recited in claim 21”, the examiner submits that newly discovered prior art by Marui teaches forming a field plate having the main body portion with a uniform thickness and the thickness of the main body portion is greater than a thickness of the gate, as required by claim 21. Thus, the above Applicant’s arguments are not persuasive, and the rejection of claim 21 under 35 USC 103 over Miyamoto in view of Gao and Marui is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891