DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 6 and 7 in the Applicant’s response dated 13 January 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendment to claim 3 in the Applicant’s response dated 13 January 2026 in lieu of the 112(a) rejection presented in the previous office action presented by the Examiner dated 13 August 2025. The 112(a) rejection previously presented has been withdrawn.
The Examiner acknowledges newly presented claims 8 and 9 in the Applicant’s response dated 13 January 2026. The new claims have been addressed below.
The Applicant states that as claim 4 depends from amended claim 1, it is therefore allowable over the cited prior art. In response to this argument, it appears that claim 4 is directed to non-elected Species G, H, I and J as set forth in the office action mailed 13 January 2026. Therefore, claim 4 was withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 and 5-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention.
Regarding Claim 1, page 4 of the Applicant’s Remarks includes amended claim 1, wherein line 3 states the amended limitations “comprises a single photodiode”. The support for said amendment is found on page 1, para [0002] lines 2 and 3 of the specification, wherein the Applicant states “Imaging semiconductor detectors (imagers) generally consist of a rectangular lattice arrangement of pixels, i.e. of cells comprising single photodiodes”. Para [0002] is found in the background of the art section of the specification. The Applicant discussing that semiconductor detectors generally consist of rectangular lattice arrangements of pixels, for example, cells comprising single photodiodes, does not convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Specifically, stating in the background of the disclosure that imaging detectors can consist of cells comprising single photodiodes does not imply that the invention as claimed requires that each pixel only comprise a single photodiode. Claim 1 has therefore been rejected for failing to comply with the written description requirement.
Claims 2-3, 5 and 8 are rejected due to their dependence on claim 1.
Regarding Claim 6, page 5 of the Applicant’s Remarks includes amended claim 6, wherein line 4 states the amended limitations “comprises a single photodiode”. The support for said amendment is found on page 1, para [0002] lines 2 and 3 of the specification, wherein the Applicant states “Imaging semiconductor detectors (imagers) generally consist of a rectangular lattice arrangement of pixels, i.e. of cells comprising single photodiodes”. Para [0002] is found in the background of the art section of the specification. The Applicant discussing that semiconductor detectors generally consist of rectangular lattice arrangements of pixels, for example, cells comprising single photodiodes, does not convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Specifically, stating in the background of the disclosure that imaging detectors can consist of cells comprising single photodiodes does not imply that the invention as claimed requires that each pixel only comprise a single photodiode. Claim 6 has therefore been rejected for failing to comply with the written description requirement
Regarding Claim 7, page 5 of the Applicant’s Remarks includes amended claim 6, wherein lines 3 and 4 state the amended limitations “wherein each pixel comprises a single photodiode”. The support for said amendment is found on page 1, para [0002] lines 2 and 3 of the specification, wherein the Applicant states “Imaging semiconductor detectors (imagers) generally consist of a rectangular lattice arrangement of pixels, i.e. of cells comprising single photodiodes”. Para [0002] is found in the background of the art section of the specification. The Applicant discussing that semiconductor detectors generally consist of rectangular lattice arrangements of pixels, for example, cells comprising single photodiodes, does not convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Specifically, stating in the background of the disclosure that imaging detectors can consist of cells comprising single photodiodes does not imply that the invention as claimed requires that each pixel only comprise a single photodiode. Claim 7 has therefore been rejected for failing to comply with the written description requirement
Claim 9 is rejected due to its dependence on claim 7.
Regarding Claim 8, page 5 of the Applicant’s Remarks includes amended claim 8, wherein lines 1-3 state the amended limitations “the single photodiode”. The support for said amendment is found on page 1, para [0002] lines 2 and 3 of the specification, wherein the Applicant states “Imaging semiconductor detectors (imagers) generally consist of a rectangular lattice arrangement of pixels, i.e. of cells comprising single photodiodes”. Para [0002] is found in the background of the art section of the specification. The Applicant discussing that semiconductor detectors generally consist of rectangular lattice arrangements of pixels, for example, cells comprising single photodiodes, does not convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Specifically, stating in the background of the disclosure that imaging detectors can consist of cells comprising single photodiodes does not imply that the invention as claimed requires that each pixel only comprise a single photodiode. Claim 8 has therefore been rejected for failing to comply with the written description requirement.
Regarding Claim 9, page 5 of the Applicant’s Remarks includes amended claim 9, wherein lines 1-3 state the amended limitations “the single photodiode”. The support for said amendment is found on page 1, para [0002] lines 2 and 3 of the specification, wherein the Applicant states “Imaging semiconductor detectors (imagers) generally consist of a rectangular lattice arrangement of pixels, i.e. of cells comprising single photodiodes”. Para [0002] is found in the background of the art section of the specification. The Applicant discussing that semiconductor detectors generally consist of rectangular lattice arrangements of pixels, for example, cells comprising single photodiodes, does not convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Specifically, stating in the background of the disclosure that imaging detectors can consist of cells comprising single photodiodes does not imply that the invention as claimed requires that each pixel only comprise a single photodiode. Claim 9 has therefore been rejected for failing to comply with the written description requirement.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jeff Raynor et al. (US 2008/0225140 A1; hereinafter “Raynor”) in view of Sosumu Inoue et al. (US 2018/0182789 A1; hereinafter “Inoue”).
Regarding Claim 1, Raynor teaches a semiconductor detector comprising
a plurality of pixels arranged in a rectangular lattice (60, 62 and 64, Fig. 10, para [0096] describes a linear pixel array of a rectangular shape where pixel components are stacked vertically), wherein each pixel has an area with a photosensitive region for detecting light (60 and 62, Fig. 10, para [0092] describes photosensitive portions 60 and 62 of a pixel), and wherein the photosensitive region has a geometric layout adapted to reduce a signal variation if the point source moves from a first pixel to a second pixel located at an adjacent lattice position (this limitation “adapted to…” is a recitation of a property of the device; because the structure of the prior art, comprising a photosensitive region for detecting light with a geometric layout (60 and 62), is substantially identical to the device claimed, the claims property is presumed to be present (see MPEP 2112.01 (I))) with respect to the first pixel (Fig. 10, para [0094] and para [0095] describes wherein controlling the geometry of the pixels to be as close as possible to one another eliminates “dead space” which may result in signal loss which is a form of signal variation).
Raynor fails to explicitly disclose wherein each pixel comprises a single photodiode.
However, Inoue teaches a similar semiconductor detector, wherein each pixel comprises a single photodiode (Fig. 3, para [0082] describes n+ regions 102, P+ regions 103 and avalanche regions 104 of an avalanche photodiode wherein para [0052] describes said photodiode is used for sensing light received on a unit pixel).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Raynor with Inoue to further disclose a semiconductor detector wherein each pixel comprises a single photodiode in order to provide the well-known advantage of simplifying a manufacturing process by requiring a single photodiode to be comprised on a unit pixel lowering manufacturing costs and manufacturing production time.
Regarding Claim 2, the combination of Raynor and Inoue teach the semiconductor detector of claim 1, wherein the geometric layout is adapted to reduce a difference of a first signal variation, occurring if the second pixel is located at a nearest-neighbor lattice position with respect to the first pixel, and a second signal variation, occurring if the second pixel is located at a second-nearest neighbor lattice position (Raynor, wherein this limitation “adapted to…” is a recitation of a property of the device; because the structure of the prior art, comprising a photosensitive region for detecting light with a geometric layout (60 and 62), is substantially identical to the device claimed, the claims property is presumed to be present (see MPEP 2112.01 (I))) with respect to the first pixel (Raynor, 90 and 92, Fig. 20 and Fig. 21, para [0101] – para [0103] describes wherein comprising the geometric layout of the photosensitive regions 90 and 92 as such in Fig. 20 and Fig. 21, increases light photosensitivity resulting in reduced signal variation between neighboring pixels).
Regarding Claim 5, the combination of Raynor and Inoue teach the semiconductor detector of claim 1, wherein a surface of each pixel comprises an area which is non-sensitive to light and comprises electronics configured to perform a readout of a signal generated by an illumination of the photosensitive region (Raynor, 94, Fig. 20 and Fig. 21, para [0004], para [0063] and para [0102] describes readout circuitry that is not a photosensitive area configured to connect the photosensitive portions to an output node to read the charge associated with the illumination of the photosensitive portion).
Regarding Claim 7, Raynor teaches a method for manufacturing a semiconductor detector, the semiconductor detector comprising a plurality of pixels arranged in a rectangular lattice (60, 62 and 64, Fig. 10, para [0096] describes a linear pixel array of a rectangular shape where pixel components are stacked vertically), the method comprising,
generating, in each pixel, a photosensitive region which has a geometric layout (60 and 62, Fig. 10, para [0017] and para [0092] describes forming photosensitive portions 60 and 62 of a pixel) adapted to reduce a signal variation if a point source illumination moves from a first pixel to a second pixel which is located at an adjacent lattice position (this limitation “adapted to…” is a recitation of a property of the device; because the structure of the prior art, comprising a photosensitive region for detecting light with a geometric layout (60 and 62), is substantially identical to the device claimed, the claims property is presumed to be present (see MPEP 2112.01 (I))) with respect to the first pixel (Fig. 10, para [0094] and para [0095] describes wherein controlling the geometry of the pixels to be as close as possible to one another eliminates “dead space” which may result in signal loss which is a form of signal variation).
Raynor fails to explicitly disclose wherein each pixel comprises a single photodiode.
However, Inoue teaches a similar semiconductor detector, wherein each pixel comprises a single photodiode (Fig. 3, para [0082] describes n+ regions 102, P+ regions 103 and avalanche regions 104 of an avalanche photodiode wherein para [0052] describes said photodiode is used for sensing light received on a unit pixel).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Raynor with Inoue to further disclose a semiconductor detector wherein each pixel comprises a single photodiode in order to provide the well-known advantage of simplifying a manufacturing process by requiring a single photodiode to be comprised on a unit pixel lowering manufacturing costs and manufacturing production time.
Regarding Claim 8, the combination of Raynor and Inoue teach the semiconductor detector according to claim 1, wherein the single photodiode (i) is rectangular (Inoue, 101, Fig. 3, para [0067] depicts wherein the single photodiode is in a rectangular shape outlined by a well region 101), and (ii) the geometric layout is generated on the single photodiode via a mask (Inoue, para [[082] describes wherein the n+ regions, p+ regions and avalanche regions geometric regions comprising a single photodiode are generated by a mask corresponding to a pattern of each of the regions).
Regarding Claim 9, the combination of Raynor and Inoue teach the method according to claim 7, wherein the single photodiode (i) is rectangular (Inoue, 101, Fig. 3, para [0067] depicts wherein the single photodiode is in a rectangular shape outlined by a well region 101), and (ii) the geometric layout is generated on the single photodiode via a mask (Inoue, para [[082] describes wherein the n+ regions, p+ regions and avalanche regions geometric regions comprising a single photodiode are generated by a mask corresponding to a pattern of each of the regions).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jeff Raynor et al. (US 2008/0225140 A1; hereinafter “Raynor”) in view of Sosumu Inoue et al. (US 2018/0182789 A1; hereinafter “Inoue”) and in further view of James Zhengshe Liu et al. (US 2015/0108354 A1; hereinafter “Liu”).
Regarding Claim 3, the combination of Raynor and Inoue discloses all the limitations of claim 1.
Raynor and Inoue fail to disclose the semiconductor detector of claim 1, wherein the photosensitive region comprises a component with at least one of the following shapes:
a star shape.
However, Liu teaches a similar semiconductor detector as Raynor, wherein the photosensitive region comprises a component with at least one of the following shapes:
a star shape (510 and 610, Fig. 5 and Fig. 6, para [0082] describes photodiode 510 with arms 512 which form the shape of a star and photodiode 610 with arms 612 which form the shape of a star).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Raynor and Inoue with Lio to further disclose a semiconductor detector which comprises a photosensitive region in the shape of a star in order to provide the advantage of increasing uniformity of light reception in particular applications as well as increasing ease and practicality, and lowering expense of manufacturing or forming the photodiodes (Liu, para [0080]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jeff Raynor et al. (US 2008/0225140 A1; hereinafter “Raynor”) in view of Sosumu Inoue et al. (US 2018/0182789 A1; hereinafter “Inoue”) and in further view of David Le Croller et al. (US 2016/0358026 A1; hereinafter “Le Croller”).
Regarding Claim 6, Raynor a semiconductor detector comprising
a plurality of pixels arranged in a rectangular lattice (60, 62 and 64, Fig. 10, para [0096] describes a linear pixel array where pixel components are stacked vertically), wherein each pixel has an area with a photosensitive region for detecting light (60 and 62, Fig. 10, para [0092] describes photosensitive portions 60 and 62 of a pixel), and wherein the photosensitive region has a geometric layout adapted to reduce a signal variation if a point source moves from a first pixel to a second pixel located at an adjacent lattice position (this limitation “adapted to…” is a recitation of a property of the device; because the structure of the prior art, comprising a photosensitive region for detecting light with a geometric layout (60 and 62), is substantially identical to the device claimed, the claims property is presumed to be present (see MPEP 2112.01 (I))) with respect to the first pixel (Fig. 10, para [0094] and para [0095] describes wherein controlling the geometry of the pixels to be as close as possible to one another eliminates “dead space” which may result in signal loss which is a form of signal variation).
Raynor fails to explicitly disclose wherein each pixel comprises a single photodiode.
However, Inoue teaches a similar semiconductor detector, wherein each pixel comprises a single photodiode (Fig. 3, para [0082] describes n+ regions 102, P+ regions 103 and avalanche regions 104 of an avalanche photodiode wherein para [0052] describes said photodiode is used for sensing light received on a unit pixel).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Raynor with Inoue to further disclose a semiconductor detector wherein each pixel comprises a single photodiode in order to provide the well-known advantage of simplifying a manufacturing process by requiring a single photodiode to be comprised on a unit pixel lowering manufacturing costs and manufacturing production time.
The combination of Raynor and Inoue fail to explicitly disclose wherein the semiconductor detector is used in a missile warning device.
However, Le Croller teaches a similar semiconductor detector as Raynor, wherein the semiconductor detector is used in a missile warning device (para [0031] describes wherein the detector device can be integrated into a hostile-missile detector).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Raynor with the teachings of Le Croller to further disclose a semiconductor detector which can be integrated into a hostile-missile detector in order to provide the advantage of efficiently detecting projectiles fired by hostiles (Le Croller, para [0007]).
Response to Arguments
Applicant’s arguments with respect to claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898