DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/20/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1, 10 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
Applicant’s amendment of Claims 6 and 13 in the Applicants Arguments dated 03/16/2026 overcome the 35 USC § 112 rejection made in the Office Action mailed on 01/29/2026. Therefore the 35 USC § 112 rejection made in the Office Action mailed on 01/29/2026 are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-9 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 2022/0208775 A1, hereinafter Zhang ‘775) in view of Higashitani et al. (US 2013/0130468 A1, hereinafter Higashitani ‘468).
PNG
media_image1.png
627
1127
media_image1.png
Greyscale
With respect to Claim 1 Zhang ‘775 discloses a three-dimensional (3D) memory device (Fig. 1-2B and 4A-5), comprising:
a stack structure (404, Fig 4D, Para [0073]) comprising alternating conductive layers (conductive layers deposited in place of the sacrificial layers 406 (shown in Fig 4D) is disclosed in Fig 5, step 514, Para [0096]) and dielectric layers (408, Fig 4D, Para [0073]) and having at least two core regions (Region C, Fig 2B, Para [0064], two core regions Region C disclosed) and a staircase region (226, Fig 2B, Para [0042]) between the two core regions (Region C);
bridge structures (206, Fig 2B, Para [0043], bridges structures 206 disclosed in annotated Fig 2B of Zhang ‘775) extending through the staircase region (226) in a thickness direction (z direction as shown in Fig 2A) of the stack structure (404) and extending along a first lateral direction (x direction as shown in Fig 2A) perpendicular to the thickness direction (z direction, x direction perpendicular to z direction shown in Fig 2A) to connect the two core regions (Region C, shown in Fig 2B), wherein a first bridge structure (top 206 shown in annotated Fig 2B of Zhang ‘775, hereinafter FBS) of the bridge structures (206) comprises at least two current paths (arrows in 206, Fig 2B, Para [0054], hereinafter CP) between the two core regions (Region C);
an isolation structure (208-1,Fig 2B, Para [0043]) extending through the staircase region (226) in the thickness direction (z direction as shown in Fig 2A), arranged along a second lateral direction (y direction as shown in Fig 2B) perpendicular to the thickness direction (z direction) and the first lateral direction (x direction)(y direction perpendicular to z direction and x direction shown in Fig 2A);
a first slit structure (210-1, Fig 2B, Para [0043]) extending through the staircase region (226) in the thickness direction (z direction shown in Fig 2A) and arranged along the second lateral direction (y direction, shown in Fig 2A) in the staircase region (226); and
a second slit structure (208-2, Fig 2A and 2B, Para [0043]) extending through the staircase region 9226) in the thickness direction (Z direction shown in Fig 2A) and arranged along the second lateral direction (y direction as shown in Fig 2B) in the staircase region (226),
wherein the first slit structure (210-1) is between the second slit structure (208-2) and the isolation structure (208-1)(210-1 between 208-1 and 208-2 shown in Fig 2B);
and wherein a first current path (first current path shown in annotated Fig 2B of Zhang ‘775, hereinafter 1CP) of the at least two current paths (CP) is between the isolation structure (208-1) and the first slit structure (210-1)(1CP between 208-1 and 210-1 shown in annotated Fig 2B of Zhang ‘775), and a second current path (second current path shown in annotated Fig 2B of Zhang ‘775, hereinafter 2CP) of the at least two current paths (CP) is between the first slit structure (210-1) and the second slit structure (208-2)(2CP between 210-1 and 208-2 shown in annotated Fig 2B of Zhang ‘775).
But Zhang ‘775 fails to explicitly disclose wherein the isolation structure separates two bridge structures in two adjacent memory blocks.
Nevertheless, in a related endeavor (Fig 3 of Higashitani ‘468), Higashitani ‘468 teaches wherein the isolation structure (S6, Fig 3 of Higashitani ‘468, Para [0079]) separates two bridge structures (I1 and I2, Fig 3 of Higashitani ‘468, Para [0079]) in two adjacent memory blocks (CA1 and CA2, Fig 3 of Higashitani ‘468, Para [0079]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Higashitani ‘468’s teaching of wherein the isolation structure separates two bridge structures in two adjacent memory blocks into Zhang ‘775’s device. Zhang ‘775 discloses a 3D memory device with a bridge structure extending through a staircase region with the well-known purpose of separating memory string regions. Zhang ‘775 discloses (in Para [0039]) the taught structure can consist of an array of memory structures 106-1 and 106-2 on either side of the bridge structure (206) but does not explicitly provide details of the isolation structure separating bridge structures in the array. Higashitani ‘468 teaches a 3D memory device with a bridge structure and further teaches the bridge structure can separate two bridge structures in two adjacent memory blocks in a memory array. The ordinary artisan would recognize that the structure taught by Higashitani ‘468 is merely a duplication of the bridge structure of Zhang ‘775 and would have a reasonable expectation of success in adding the second structure. Therefore, the person of ordinary skill in the art would have been motivated then to modify Zhang ‘775 in the manner set forth above, at least, this addition of the bridge structure between memory arrays would provide further separation between memory strings which would reduce the possibility of parasitic capacitance between those memory regions.
As incorporated, the isolation structure (S6) separating two bridge structures (I1 and I2) in two adjacent memory blocks taught by Higashitani ‘468 would be used so that the isolation structure (208-1 of Zhang ‘775) would separate two bridge structures (206 of Zhang ‘775) in the device of Zhang ‘775.
With respect to Claim 2 Zhang ‘775 as modified by Higashitani ‘468 discloses all limitations of the 3D memory device of claim 1, and Zhang ‘775 as modified by Higashitani ‘468 further discloses wherein:
the first slit structure (210-1) is discontinuously arranged (210-1 discontinuously arranged is disclosed in Fig 2B) along the second lateral direction (y-direction) in the staircase region (226); and the second slit structure (208-2) is discontinuously arranged (208-2 discontinuously arranged is disclosed in Fig 2B) along the second lateral direction (y-direction) in the staircase region (226).
With respect to Claim 4 Zhang ‘775 as modified by Higashitani ‘468 discloses all limitations of the 3D memory device of claim 2, and Zhang ‘775 as modified by Higashitani ‘468 further discloses wherein the first current path (1CP) and the second current path (2CP) are interconnected through discontinuous portions of the first slit structure (210-1)(annotated Fig 2B of Zhang ‘775 discloses 1CP and 2CP are interconnected through discontinuous portions of 210-1).
With respect to Claim 7 Zhang ‘775 as modified by Higashitani ‘468 discloses all limitations of the 3D memory device of claim 1, and Zhang ‘775 as modified by Higashitani ‘468 discloses further comprising: channel structures each extending in the stack structure (channel structure extending in the stack structure disclosed in Para [0051]) along the thickness direction (x direction) in the core regions (Region C).
With respect to Claim 8 Zhang ‘775 as modified by Higashitani ‘468 discloses all limitations of the 3D memory device of claim 7, and Zhang ‘775 as modified by Higashitani ‘468 further discloses wherein the first bridge structure (first 206 of Zhang ‘775 as modified by Higashitani ‘468 above) connects two of the conductive layers in two respective core regions (Region C)(Para [0049] discloses bridge structure 206 conductively connects to the core regions).
With respect to Claim 9 Zhang ‘775 as modified by Higashitani ‘468 discloses all limitations of the 3D memory device of claim 1, and Zhang ‘775 as modified by Higashitani ‘468 further discloses wherein a material of the bridge structures (206 of Zhang ‘775 as modified by Higashitani ‘468 above) comprises tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof (Para [0044] discloses 206 comprises conductive layers of tungsten (W)).
With respect to Claim 17 Zhang ‘775 discloses a system, comprising: a three-dimensional (3D) memory device (Fig. 1-2B and 4A-5) configured to store data (disclosed in Para [0033]), the 3D memory device comprising:
a stack structure (404, Fig 4D, Para [0073]) comprising alternating conductive layers conductive layers deposited in place of the sacrificial layers 406 (shown in Fig 4D) is disclosed in Fig 5, step 514, Para [0096])) and dielectric layers (408, Fig 4D, Para [0073]) and having at least two core regions (Region C, Fig 2B, Para [0064], two core regions Region C disclosed) and a staircase region (226, Fig 2B, Para [0042]) between the two core regions (Region C);
bridge structures (206, Fig 2B, Para [0043], bridges structures 206 disclosed in annotated Fig 2B of Zhang ‘775) extending through the staircase region (226) in a thickness direction (z direction as shown in Fig 2A) of the stack structure (226) and extending along a first lateral direction (x direction as shown in Fig 2A) perpendicular to the thickness direction (z direction) (z direction, x direction perpendicular to z direction shown in Fig 2A) to connect the two core regions (Region C), wherein a first bridge structure (first bridge structure 206 as shown in annotated Fig 2B of Zhang ‘775) of the bridge structures (bridge structures 206) comprises at least two current paths (arrows in 206, Fig 2B, Para [0054], hereinafter CP) between the two core regions (Region C);
an isolation structure (208-1,Fig 2B, Para [0043]) extending through the staircase region (226) in the thickness direction (z direction as shown in Fig 2A), wherein the isolation structure (208-1) arranged along a second lateral direction (y direction as shown in Fig 2B) perpendicular to the thickness direction (z direction) and the first lateral direction (x direction) (y direction perpendicular to z direction and x direction shown in Fig 2A);
a first slit structure (210-1, Fig 2B, Para [0043]) extending through the staircase region (226) in the thickness direction (z direction shown in Fig 2A) and arranged along the second lateral direction (y direction, shown in Fig 2A) in the staircase region (226); and
a second slit structure (208-2, Fig 2A and 2B, Para [0043]) extending through the staircase region 9226) in the thickness direction (Z direction shown in Fig 2A) and arranged along the second lateral direction (y direction as shown in Fig 2B) in the staircase region (226),
wherein the first slit structure (210-1) is between the second slit structure (208-2) and the isolation structure (208-1)(210-1 between 208-1 and 208-2 shown in Fig 2B);
and wherein a first current path (first current path shown in annotated Fig 2B of Zhang ‘775, hereinafter 1CP) of the at least two current paths (CP) is between the isolation structure (208-1) and the first slit structure (210-1)(1CP between 208-1 and 210-1 shown in annotated Fig 2B of Zhang ‘775), and a second current path (second current path shown in annotated Fig 2B of Zhang ‘775, hereinafter 2CP) of the at least two current paths (CP) is between the first slit structure (210-1) and the second slit structure (208-2)(2CP between 210-1 and 208-2 shown in annotated Fig 2B of Zhang ‘775) and
a memory controller coupled to the 3D memory device and configured to control the 3D memory device (Para [0004] discloses memory device of Zhang ‘775 as coupled to a peripheral device for controlling signals to and from the memory array).
But Zhang ‘775 fails to explicitly disclose wherein the isolation structure separates two bridge structures in two adjacent memory blocks.
Nevertheless, in a related endeavor (Fig 3 of Higashitani ‘468), Higashitani ‘468 teaches wherein the isolation structure (S6, Fig 3 of Higashitani ‘468, Para [0079]) separates two bridge structures (I1 and I2, Fig 3 of Higashitani ‘468, Para [0079]) in two adjacent memory blocks (CA1 and CA2, Fig 3 of Higashitani ‘468, Para [0079]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Higashitani ‘468’s teaching of wherein the isolation structure separates two bridge structures in two adjacent memory blocks into Zhang ‘775’s device. Zhang ‘775 discloses a 3D memory device with a bridge structure extending through a staircase region with the well-known purpose of separating memory string regions. Zhang ‘775 discloses (in Para [0039]) the taught structure can consist of an array of memory structures 106-1 and 106-2 but does not explicitly provide details of the isolation structure separating bridge structures in the array. Higashitani ‘468 teaches a 3D memory device with a bridge structure and further teaches the bridge structure can separate two bridge structures in two adjacent memory blocks. The ordinary artisan would recognize that the structure taught by Higashitani ‘468 is merely a duplication the bridge structure of Zhang ‘775 and would have a reasonable expectation of success in adding the second structure. Therefore, the person of ordinary skill in the art would have been motivated then to modify Zhang ‘775 in the manner set forth above, at least, this addition of the bridge structure would provide further separation between memory strings which would reduce the possibility of parasitic capacitance between those memory regions.
As incorporated, the isolation structure (S6) separating two bridge structures (I1 and I2) in two adjacent memory blocks taught by Higashitani ‘468 would be used so that the isolation structure (208-1 of Zhang ‘775) would separate two bridge structures (206 of Zhang ‘775) in the device of Zhang ‘775.
With respect to Claim 18 Zhang ‘775 as modified by Higashitani ‘468 discloses all limitations of the system of claim 17, and Zhang ‘775 as modified by Higashitani ‘468 further discloses wherein:
the first slit structure (210-1) is discontinuously arranged (210-1 discontinuously arranged is disclosed in Fig 2B) along the second lateral direction (y-direction) in the staircase region (226); and the second slit structure (208-2) is discontinuously arranged (208-2 discontinuously arranged is disclosed in Fig 2B) along the second lateral direction (y-direction) in the staircase region (226).
With respect to Claim 19 Zhang ‘775 as modified by Higashitani ‘468 discloses all limitations of the system of claim 18, and Zhang ‘775 as modified by Higashitani ‘468 further discloses wherein the first current path (1CP) and the second current path (2CP) are interconnected through discontinuous portions of the first slit structure (210-1)(annotated Fig 2B of Zhang ‘775 discloses 1CP and 2CP are interconnected through discontinuous portions of 210-1).
Allowable Subject Matter
Claims 10-11 and 13-16 are allowed.
Claims 5-6 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claims 10-11 and 13-16: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “and at least three dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction, wherein first dummy channel structures of the at least three dummy channel structures are in contact with the second slit structure at a close side toward the isolation structure, wherein a width of a first bridge structure of the bridge structures is ranged from the isolation structure to the first dummy channel structures” along with the rest of the limitations of said claims.
Closest prior art of record Zhang (US 2022/0208775 A1, hereinafter Zhang ‘775) teaches “a 3D memory device , comprising: a stack structure comprising alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions; bridge structures extending through the staircase region in a thickness direction of the stack structure and connecting the two core regions arranged along a first lateral direction perpendicular to the thickness direction; an isolation structure extending through the staircase region in the thickness direction, wherein the isolation structure separates two bridge structures in two adjacent memory blocks arranged along a second lateral direction perpendicular to the thickness direction and the first lateral direction; a first slit structure extending through the staircase region in the thickness direction and discontinuously arranged along the second lateral direction in the staircase region; a second slit structure extending through the staircase region in the thickness direction and discontinuously arranged along the second lateral direction in the staircase region, wherein the first slit structure is between the second slit structure and the isolation structure”. However Zhang ‘775 fails to disclose “and at least three dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction, wherein first dummy channel structures of the at least three dummy channel structures are in contact with the second slit structure at a close side toward the isolation structure, wherein a width of a first bridge structure of the bridge structures is ranged from the isolation structure to the first dummy channel structures”.
Closest prior art of record Lee (US 2019/0067182 A1, hereinafter Lee ‘182) teaches dummy channel structures in a 3D memory device. But Lee ‘182 fails to disclose “and at least three dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction, wherein first dummy channel structures of the at least three dummy channel structures are in contact with the second slit structure at a close side toward the isolation structure, wherein a width of a first bridge structure of the bridge structures is ranged from the isolation structure to the first dummy channel structures”.
Regarding Claim 5-6: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “first dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the second slit structure at a close side toward the isolation structure, wherein the first current path of the at least two current paths is between the isolation structure and the first dummy channel structures, and the second current path of the at least two current paths is between the second dummy channel structures and the third dummy channel structures” along with the rest of the limitations of said claims.
Closest prior art of record Zhang ‘775 discloses a 3D memory structure with bridge regions and slit structures with current paths as cited by the limitations of Claim 1, but Zhang ‘775 fails to disclose “first dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the second slit structure at a close side toward the isolation structure, wherein the first current path of the at least two current paths is between the isolation structure and the first dummy channel structures, and the second current path of the at least two current paths is between the second dummy channel structures and the third dummy channel structures”.
Closest prior art of record Higashitani ‘468 discloses a 3D memory structure with an isolation structure separating two bridge structures in two adjacent memory blocks, but Higashitani ‘468 fails to disclose “first dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the second slit structure at a close side toward the isolation structure, wherein the first current path of the at least two current paths is between the isolation structure and the first dummy channel structures, and the second current path of the at least two current paths is between the second dummy channel structures and the third dummy channel structures”.
Regarding Claim 20: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “first dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction perpendicular to the thickness direction and the first lateral direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the second slit structure at a close side toward the isolation structure, wherein the first current path of the at least two current paths is between the isolation structure and the first dummy channel structures, and the second current path of the at least two current paths is between the second dummy channel structures and the third dummy channel structures” along with the rest of the limitations of said claims.
Closest prior art of record Zhang ‘775 discloses a 3D memory structure with bridge regions and slit structures with current paths as cited by the limitations of Claim 17, but Zhang ‘775 fails to disclose “first dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction perpendicular to the thickness direction and the first lateral direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the second slit structure at a close side toward the isolation structure, wherein the first current path of the at least two current paths is between the isolation structure and the first dummy channel structures, and the second current path of the at least two current paths is between the second dummy channel structures and the third dummy channel structures”.
Closest prior art of record Higashitani ‘468 discloses a 3D memory structure with an isolation structure separating two bridge structures in two adjacent memory blocks, but Higashitani ‘468 fails to disclose “first dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction perpendicular to the thickness direction and the first lateral direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure in the thickness direction and being arranged side-by-side in the second lateral direction and in contact with the second slit structure at a close side toward the isolation structure, wherein the first current path of the at least two current paths is between the isolation structure and the first dummy channel structures, and the second current path of the at least two current paths is between the second dummy channel structures and the third dummy channel structures”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights