DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/3/2026 has been entered.
Status of Claims
Claims 1-3 and 5-6 are pending in this application. Claims 4 and 7-23 remains withdrawn.
Claim Rejections - 35 USC § 112
Prior rejection of Claims 1-3 and 5-6 under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, are withdrawn in view of applicant’s amendments to claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kato et al. (US 2021/0159239 A1, newly cited).
Re Claim 1, Kato teaches a semiconductor memory device (Fig. 32) comprising:
a gate stack structure (23+25, Fig. 32, paras [0080] – [0082]) including a plurality of interlayer insulating layers (23, Fig. 32, para [0080]) and a plurality of conductive layers (25, Fig. 32, para [0080]), which are alternately stacked in a first direction (alternately stacked along z-axis, see Fig. 32), the gate stack structure having a stepped structure defined by an end portion of each of the plurality of conductive layers extending to a different length (see Fig. 32 where the stack has a stepped structure, and different word lines 25 have different lengths, for example WL6 is longer than WL7 in Fig. 32);
a gap fill insulating layer (27+28, Fig. 32, para [0081]) disposed on the gate stack structure to cover the stepped structure (see Fig. 32);
a tubular insulating layer (32 forms a tubular section, Fig. 32, para [0118], also see Fig. 19, on how the layer is initially formed) intersecting the end portion of each of the plurality of conductive layers (end portions of 25 layers, see Fig. 32), the tubular insulating layer extending in the first direction (along z-axis) to penetrate (see Fig. 32) the stepped structure of the gate stack structure (23+25) and the gap fill insulating layer (27+28); and
a conductive gate contact (41+42, Fig. 32, para [0086]) disposed in a central region of the tubular insulating layer (32, see Fig. 32),
wherein the conductive gate contact (41+42) includes a protrusion part (marked “gate contact protrusion” in annotated Fig. 32 below) penetrating a side portion of the tubular insulating layer (32, see Fig. 32) to be connected to one conductive layer among the plurality of conductive layers (one of the corresponding word line layer 25, Fig. 32), and
wherein the tubular insulating layer (32, Fig. 32) extends in the first direction (z-axis, Fig. 32) without forming a protruded region in a second direction (no protrusion along x-axis in the tubular section, Fig. 32) perpendicular to the first direction, and along which the end portion of each of the plurality of conductive layers extends to a different length (different word line layers 25 have different lengths along x-axis, see Fig. 32).
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Re Claim 2, Kato teaches the semiconductor memory device of claim 1, wherein the tubular insulating layer (32, Fig. 32) is isolated into a first tubular insulating pattern (marked “32-1” in annotated Fig. 32 above) penetrating the gate stack structure (23+25) and a second tubular insulating pattern (marked “32-2” in annotated Fig. 32 above) penetrating the gap fill insulating layer (27+28) by the protrusion part.
Re Claim 3, Kato teaches the semiconductor memory device of claim 1, wherein the tubular insulating layer (32) continuously extends to penetrate at least one conductive layer among the plurality of conductive layers (at least one of the word line layer 25, see Fig. 32) and at least one interlayer insulating layer among the plurality of interlayer insulating layers (at least one of the insulating layer 23, see Fig. 32).
Re Claim 5, Kato teaches the semiconductor memory device of claim 1, wherein the conductive gate contact (41+42) includes a pillar part (marked “pillar part of gate contact” in annotated Fig. 32 above) surrounded by the tubular insulating layer (32, see Fig. 32), the pillar part (“pillar part of gate contact”) being integrated with the protrusion part (“gate contact protrusion”, see annotated Fig. 32 above).
Re Claim 6, Kato teaches the semiconductor memory device of claim 1, wherein the protrusion part (“gate contact protrusion”) of the conductive gate contact (41+42) is integrated with the one conductive layer among the plurality of conductive layers (one of the corresponding word line layer 25, see Fig. 32).
Rejection 2
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2020/0350249 A1, newly cited).
Re Claim 1, Kim teaches a semiconductor memory device (Fig. 17A) comprising:
a gate stack structure (260A+112, Fig. 17A, paras [0109] - [0111]) including a plurality of interlayer insulating layers (112, Fig. 17A, para [0111]) and a plurality of conductive layers (260A, Fig. 17A, para [0109]), which are alternately stacked in a first direction (alternately stacked along vertical axis in Fig. 17A), the gate stack structure having a stepped structure defined by an end portion of each of the plurality of conductive layers extending to a different length (see Fig. 17A where the stack has a stepped structure, and 260A layers have different lengths along horizontal axis in Fig. 17A);
a gap fill insulating layer (ILD, Fig. 17A, para [0041]) disposed on the gate stack structure to cover the stepped structure (see Fig. 17A);
a tubular insulating layer (240, Fig. 17A, para [0099]) intersecting the end portion of each of the plurality of conductive layers (end portions of 260A layers, see Fig. 17A), the tubular insulating layer extending in the first direction (vertical axis in Fig. 17A) to penetrate (see Fig. 17A) the stepped structure of the gate stack structure (260A+112) and the gap fill insulating layer (ILD); and
a conductive gate contact (250+260B, Fig. 17A, paras [0102] and [0109]) disposed in a central region of the tubular insulating layer (240, see Fig. 17A),
wherein the conductive gate contact (250+260B) includes a protrusion part (260B, Fig. 17A) penetrating a side portion of the tubular insulating layer (240, see Fig. 17A) to be connected to one conductive layer among the plurality of conductive layers (one of the corresponding 260A layers, see Fig. 17A), and
wherein the tubular insulating layer (240, Fig. 17A) extends in the first direction (vertical axis, Fig. 17A) without forming a protruded region in a second direction (240 has no protrusion along horizontal axis in Fig. 17A) perpendicular to the first direction, and along which the end portion of each of the plurality of conductive layers extends to a different length (260A layers have different lengths along horizontal axis in Fig. 17A).
Re Claim 2, Kim teaches the semiconductor memory device of claim 1, wherein the tubular insulating layer (240, Fig. 17A) is isolated into a first tubular insulating pattern (marked “240-1” in annotated Fig. 17A below) penetrating the gate stack structure (260A+112) and a second tubular insulating pattern (marked “240-2” in annotated Fig. 17A below) penetrating the gap fill insulating layer (ILD) by the protrusion part.
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Re Claim 3, Kim teaches the semiconductor memory device of claim 1, wherein the tubular insulating layer (240, Fig. 17A) continuously extends to penetrate at least one conductive layer among the plurality of conductive layers (at least one 260A layer, see Fig. 17A) and at least one interlayer insulating layer among the plurality of interlayer insulating layers (at least one insulating layer 112, see Fig. 17A).
Re Claim 5, Kim teaches the semiconductor memory device of claim 1, wherein the conductive gate contact (250+260B, Fig. 17A) includes a pillar part (250) surrounded by the tubular insulating layer (240), the pillar part (250) being integrated with the protrusion part (260B).
Re Claim 6, Kim teaches the semiconductor memory device of claim 1, wherein the protrusion part (260B, Fig. 17A) of the conductive gate contact (250+260B) is integrated with the one conductive layer among the plurality of conductive layers (one of the corresponding 260A layer, see Fig. 17A).
Response to Arguments
Applicant’s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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