Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/12/2026 has been entered.
Drawings Objection Withdrawal
Claims 4-7 are withdrawn from consideration. Thus, the objection to drawings is withdrawn.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 8 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 8 depends from nonelected Claim 4. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 8-11 rejected under 35 U.S.C. 103 as being unpatentable over Cho (U.S. Patent Pub. No. 2021/0305130) of record, in view of Yu (U.S. Patent Pub. No. 2012/0326319) of record, in view of Kao (U.S. Patent Pub. No. 2020/0381512) of record, in view of Lin (U.S. Patent Pub. No. 2021/0215755)
Regarding Claim 1
FIG. 13 (annotated below) of Cho discloses a semiconductor component comprising a semiconductor substrate (150) having a front side (fs) and a back side (bs), and comprising a first area (A1) and a second area (A2) not overlapping the first area, the areas extending from the front side of the substrate to the back side through a complete thickness of the substrate, the semiconductor component comprising: a device layer (142) at the front side of the substrate, comprising a plurality of active devices located in the first area, wherein the active devices are configured to receive input signals and to send output signals (I/O signals); a plurality of buried interconnect rails (I/O rails) (156) at least partially buried in the substrate, at the front side thereof, and located in the second area; a plurality of through substrate via (TSV) connections (I/O TSVs) (174) located in the second area, passing through the substrate from the I/O rails to the back side of the substrate, each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (172); a front side redistribution layer (UWL) on the device layer, configured to route the I/O signals between the active devices in the first area and the I/O rails in the second area; input/output terminals (I/O terminals) (187) at the back side of the component; a back side redistribution layer (LWL) at the back side of the substrate configured to route the I/O signals between the I/O terminals on the back side of the component and a back end of the I/O TSVs; and a plurality of power supply terminals (187a/b) and conductors connected thereto, configured to supply power to the active devices, the power supply terminals being coupled to either a reference voltage Vss or a power voltage VDD [0113], wherein no active devices are formed in the second area, the plurality of I/O rails are electrically connected by the plurality of I/O TSVs to the back side redistribution layer electrically connected to the I/O terminals.
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Cho is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well, the substrate comprises a second well in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, wherein the second well separates the first well from the rest of the substrate, the second well being of a second conductivity type opposite the first conductivity type, so that a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well” and “the plurality of I/O rails are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs”.
FIG. 3 of Yu discloses a similar component, wherein the substrate (3) comprises a second well (19) in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, the second well being of a second conductivity type opposite the first conductivity type [0014], and the second well includes at least one contact (63, FIG. 4), configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Yu. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing parasitic capacitance and cost ([0004] of Yu).
Cho as modified by Yu is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well”; “the second well separates the first well from the rest of the substrate” and “a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well”
FIG. 7 of Kao discloses a similar component, wherein the plurality of I/O TSVs (104) and the plurality of I/O rails are located in a first well (108 within 102w) of the substrate (108), each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (118), the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well; the second well (102w) separates the first well from the rest of the substrate; and a junction (110) is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well [0023].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Kao. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing the accumulation of charge at the semiconductor device ([0019] of Kao).
Cho as modified by Yu and Kao is silent with respect to “the plurality of I/O rails are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs”.
FIG. 5 of Lin discloses a similar component, wherein the plurality of I/O rails (connecting OCS and 400, CLK and 400) are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs (300).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Lin. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of transmitting signal in the TSV array ([0075] of Lin).
Regarding Claim 2
FIG. 13 of Cho discloses buried power rails and power TSV connections (174a/b) in the first area, coupled to Vss (187b) and VDD (187a) terminals at the back side of the component and coupled to the active devices in the device layer at the front side of the substrate for supplying power thereto.
Regarding Claim 3
FIG. 4 of Yu discloses the at least one contact (63) of the second well is coupled to VDD [0024].
Regarding Claim 8
FIG. 7 of Kao discloses one or more of the additional contacts comprise regions which form guard rings around the floating well [0051].
Regarding Claim 9
FIG. 3 of Yu discloses the substrate (3) is a p or n doped silicon substrate [0024].
Regarding Claim 10
FIG. 13 of Cho discloses the component is an integrated circuit chip [0020].
Regarding Claim 11
FIG. 13 of Cho discloses the first well is not connected to an external voltage source for applying the bias.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Cho, in view of Yu, in view of Kao, in view of Law (U.S. Patent Pub. No. 2010/0252934).
Regarding Claim 1
FIG. 13 (annotated above) of Cho discloses a semiconductor component comprising a semiconductor substrate (150) having a front side (fs) and a back side (bs), and comprising a first area (A1) and a second area (A2) not overlapping the first area, the areas extending from the front side of the substrate to the back side through a complete thickness of the substrate, the semiconductor component comprising: a device layer (142) at the front side of the substrate, comprising a plurality of active devices located in the first area, wherein the active devices are configured to receive input signals and to send output signals (I/O signals); a plurality of buried interconnect rails (I/O rails) (156) at least partially buried in the substrate, at the front side thereof, and located in the second area; a plurality of through substrate via (TSV) connections (I/O TSVs) (174) located in the second area, passing through the substrate from the I/O rails to the back side of the substrate, each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (172); a front side redistribution layer (UWL) on the device layer, configured to route the I/O signals between the active devices in the first area and the I/O rails in the second area; input/output terminals (I/O terminals) (187) at the back side of the component; a back side redistribution layer (LWL) at the back side of the substrate configured to route the I/O signals between the I/O terminals on the back side of the component and a back end of the I/O TSVs; and a plurality of power supply terminals (187a/b) and conductors connected thereto, configured to supply power to the active devices, the power supply terminals being coupled to either a reference voltage Vss or a power voltage VDD [0113], wherein no active devices are formed in the second area, the plurality of I/O rails are electrically connected by the plurality of I/O TSVs to the back side redistribution layer electrically connected to the I/O terminals,.
Cho is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well, the substrate comprises a second well in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, wherein the second well separates the first well from the rest of the substrate, the second well being of a second conductivity type opposite the first conductivity type, so that a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well” and “the plurality of I/O rails are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs”.
FIG. 3 of Yu discloses a similar component, wherein the substrate (3) comprises a second well (19) in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, the second well being of a second conductivity type opposite the first conductivity type [0014], and the second well includes at least one contact (63, FIG. 4), configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Yu. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing parasitic capacitance and cost ([0004] of Yu).
Cho as modified by Yu is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well”; “the second well separates the first well from the rest of the substrate” and “a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well”
FIG. 7 of Kao discloses a similar component, wherein the plurality of I/O TSVs (104) and the plurality of I/O rails are located in a first well (108 within 102w) of the substrate (108), each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (118), the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well; the second well (102w) separates the first well from the rest of the substrate; and a junction (110) is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well [0023].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Kao. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing the accumulation of charge at the semiconductor device ([0019] of Kao).
Cho as modified by Yu and Kao is silent with respect to “the plurality of I/O rails are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs”.
FIG. 6 of Law discloses a similar component, wherein the plurality of I/O rails (605) are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs (603).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Law. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing the complexity of the signal, power, and ground interconnections ([0005] of Law).
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Cho, in view of Yu, in view of Kao, in view of Kim (CN 102576657, machine-translation provided).
Regarding Claim 1
FIG. 13 (annotated above) of Cho discloses a semiconductor component comprising a semiconductor substrate (150) having a front side (fs) and a back side (bs), and comprising a first area (A1) and a second area (A2) not overlapping the first area, the areas extending from the front side of the substrate to the back side through a complete thickness of the substrate, the semiconductor component comprising: a device layer (142) at the front side of the substrate, comprising a plurality of active devices located in the first area, wherein the active devices are configured to receive input signals and to send output signals (I/O signals); a plurality of buried interconnect rails (I/O rails) (156) at least partially buried in the substrate, at the front side thereof, and located in the second area; a plurality of through substrate via (TSV) connections (I/O TSVs) (174) located in the second area, passing through the substrate from the I/O rails to the back side of the substrate, each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (172); a front side redistribution layer (UWL) on the device layer, configured to route the I/O signals between the active devices in the first area and the I/O rails in the second area; input/output terminals (I/O terminals) (187) at the back side of the component; a back side redistribution layer (LWL) at the back side of the substrate configured to route the I/O signals between the I/O terminals on the back side of the component and a back end of the I/O TSVs; and a plurality of power supply terminals (187a/b) and conductors connected thereto, configured to supply power to the active devices, the power supply terminals being coupled to either a reference voltage Vss or a power voltage VDD [0113], wherein no active devices are formed in the second area, the plurality of I/O rails are electrically connected by the plurality of I/O TSVs to the back side redistribution layer electrically connected to the I/O terminals,.
Cho is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well, the substrate comprises a second well in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, wherein the second well separates the first well from the rest of the substrate, the second well being of a second conductivity type opposite the first conductivity type, so that a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well” and “the plurality of I/O rails are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs”.
FIG. 3 of Yu discloses a similar component, wherein the substrate (3) comprises a second well (19) in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, the second well being of a second conductivity type opposite the first conductivity type [0014], and the second well includes at least one contact (63, FIG. 4), configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Yu. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing parasitic capacitance and cost ([0004] of Yu).
Cho as modified by Yu is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well”; “the second well separates the first well from the rest of the substrate” and “a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well”
FIG. 7 of Kao discloses a similar component, wherein the plurality of I/O TSVs (104) and the plurality of I/O rails are located in a first well (108 within 102w) of the substrate (108), each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (118), the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well; the second well (102w) separates the first well from the rest of the substrate; and a junction (110) is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well [0023].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Kao. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing the accumulation of charge at the semiconductor device ([0019] of Kao).
Cho as modified by Yu and Kao is silent with respect to “the plurality of I/O rails are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs”.
FIG. 7 of Kim discloses a similar component, wherein the plurality of I/O rails (704) are elongated and extend in a lateral direction parallel to a major surface of the semiconductor substrate to traverse two or more of the plurality of I/O TSVs (702).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Kim. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of coupling signal input to conductive path ([0055] of Kim).
Pertinent Art
FIG. 4 of Wu (CN 101859762) discloses a semiconductor component comprising a semiconductor [0054] substrate (101) having a front side (105) and a back side (107), and comprising a first area (comprising 303) and a second area (comprising 301) not overlapping the first area, the areas extending from the front side of the substrate to the back side through a complete thickness of the substrate, the semiconductor component comprising: a device layer at the front side of the substrate, comprising a plurality of active devices (102) located in the first area, wherein the active devices are configured to receive input signals and to send output signals (I/O signals); a plurality of buried interconnect rails (I/O rails) (connection between 301 and 201) at least partially buried in the substrate, at the front side thereof, and located in the second area; a plurality of through substrate via (TSV) (301) connections (I/O TSVs) located in the second area, passing through the substrate from the I/O rails to the back side of the substrate, a front side redistribution layer (201) on the device layer, configured to route the I/O signals between the active devices in the first area and the I/O rails in the second area; input/output terminals (I/O terminals) (405) at the back side of the component; a back side redistribution layer (401) at the back side of the substrate configured to route the I/O signals between the I/O terminals on the back side of the component and a back end of the I/O TSVs; and a plurality of power supply terminals [0029] and conductors connected thereto, configured to supply power to the active devices, the power supply terminals being coupled to either a reference voltage Vss or a power voltage VDD [0057].
FIG. 6 of Endo (U.S. Patent Pub. No. 2013/0168832) discloses the second well comprises a third contact opposite the first contact, at the other side of the substrate compared to the first contact, the third contact comprising a region of the first conductivity type; the substrate comprises a fourth contact opposite the second contact, the fourth contact comprising a region of the second conductivity type; and the third and fourth contacts are coupled to the I/O rails, so that the ESD circuit is a double diode circuit formed by two diodes formed respectively by at least part of the junction between the substrate and the region of the fourth contact and by at least part of the junction between the second well and the region of the third contact. Pertinent art also includes Horng (U.S. Patent Pub. No. 2013/0147057), Lin (U.S. Patent Pub. No. 2010/0237386), Cheng (CN 102201405) and Chu (U.S. Patent Pub. No. 2022/0208753).
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Applicant's arguments with respect to Cho have been considered but they are not persuasive. [0116] of Cho merely states “The TSVs 174c and 174d may be electrically connected to a plurality of active elements through a plurality of TSV landing pads 156c and 156d”. This does not necessarily mean the active elements are located in the same area as the TSV 174c and 174d. The active elements can be located in the first area but connected to the TSVs in the second area. For clarity, the Examiner refines the second area, as shown in the annotated FIG. 13 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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