Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Drawings Objection
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations in Claims 4-7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. In the response filed on 10/20/2025, the Applicant argues that these features are shown in FIGS. 4A, 5, 6A, 7, 8A-8C and 9. However, none of these figures are elected. In the reply filed on 5/27/2025, Embodiment II (FIGS. 2A-2B) is elected for examination.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 8-11 rejected under 35 U.S.C. 103 as being unpatentable over Cho (U.S. Patent Pub. No. 2021/0305130) of record, in view of Yu (U.S. Patent Pub. No. 2012/0326319) of record, in view of Kao (U.S. Patent Pub. No. 2020/0381512) of record.
Regarding Claim 1
FIG. 13 of Cho discloses a semiconductor component comprising a semiconductor substrate (150) having a front side (150fs) and a back side (150bs), and comprising a first area (comprising 156a/b) and a second area (comprising 156c/d) not overlapping the first area, the areas extending from the front side of the substrate to the back side through a complete thickness of the substrate, the semiconductor component comprising: a device layer (142) at the front side of the substrate, comprising a plurality of active devices located in the first area, wherein the active devices are configured to receive input signals and to send output signals (I/O signals); a plurality of buried interconnect rails (I/O rails) (156c/d) at least partially buried in the substrate, at the front side thereof, and located in the second area; a plurality of through substrate via (TSV) (174c/d) connections (I/O TSVs) located in the second area, passing through the substrate from the I/O rails to the back side of the substrate, each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (172); a front side redistribution layer (UWL) on the device layer, configured to route the I/O signals between the active devices in the first area and the I/O rails in the second area; input/output terminals (I/O terminals) (187c/d) at the back side of the component; a back side redistribution layer (LWL) at the back side of the substrate configured to route the I/O signals between the I/O terminals on the back side of the component and a back end of the I/O TSVs; and a plurality of power supply terminals (187a/b) and conductors connected thereto, configured to supply power to the active devices, the power supply terminals being coupled to either a reference voltage Vss or a power voltage VDD [0113].
Cho is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well, the substrate comprises a second well in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, wherein the second well separates the first well from the rest of the substrate, the second well being of a second conductivity type opposite the first conductivity type, so that a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well”.
FIG. 3 of Yu discloses a similar component, wherein the substrate (3) comprises a second well (19) in the second area, the second well extending from the front side of the substrate to the back side of the substrate through the complete thickness of the substrate, the second well being of a second conductivity type opposite the first conductivity type [0014], and the second well includes at least one contact (63, FIG. 4), configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Yu. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing parasitic capacitance and cost ([0004] of Yu).
Cho as modified by Yu is silent with respect to “the plurality of I/O TSVs and the plurality of I/O rails are located in a first well of the substrate, the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well”; “the second well separates the first well from the rest of the substrate” and “a junction is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well”
FIG. 7 of Kao discloses a similar component, wherein the plurality of I/O TSVs (104) and the plurality of I/O rails are located in a first well (108 within 102w) of the substrate (108), each I/O TSV and each I/O rail being isolated from the substrate by a dielectric liner (118), the first well being formed of semiconductor material of a first conductivity type, the first well extending from the front side of the substrate to the back side of the substrate, through the complete thickness of the substrate, the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well; the second well (102w) separates the first well from the rest of the substrate; and a junction (110) is formed between the first well and the second well, and the second well includes at least one contact, configured to enable an application of a bias voltage to the second well, so as to reverse bias at least part of the junction between the first well and the second well [0023].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Kao. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing the accumulation of charge at the semiconductor device ([0019] of Kao).
Regarding Claim 2
FIG. 13 of Cho discloses buried power rails and power TSV connections (174a/b) in the first area, coupled to Vss (187b) and VDD (187a) terminals at the back side of the component and coupled to the active devices in the device layer at the front side of the substrate for supplying power thereto.
Regarding Claim 3
FIG. 4 of Yu discloses the at least one contact (63) of the second well is coupled to VDD [0024].
Regarding Claim 8
FIG. 7 of Kao discloses one or more of the additional contacts comprise regions which form guard rings around the floating well [0051].
Regarding Claim 9
FIG. 3 of Yu discloses the substrate (3) is a p or n doped silicon substrate [0024].
Regarding Claim 10
FIG. 13 of Cho discloses the component is an integrated circuit chip [0020].
Regarding Claim 11
FIG. 13 of Cho discloses the first well is not connected to an external voltage source for applying the bias.
Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Cho, Yu and Kao, in view of Furuta (U.S. Patent Pub. No. 2014/0091478) of record.
Regarding Claim 4
Cho as modified by Yu and Kao discloses Claim 1.
Cho as modified by Yu and Kao is silent with respect to “additional contacts, junctions, and conductors which implement an ESD protection circuit for protecting the I/O rails and the I/O TSVs from ESD pulses”.
FIG. 10 of Furuta discloses a similar component, comprising additional contacts, junctions, and conductors which implement an ESD protection circuit for protecting the I/O rails and the I/O TSVs from ESD pulses [0061].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Furuta. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of having a high efficiency of arranging a TSV ([0027] of Furuta).
Claims 5-7 rejected under 35 U.S.C. 103 as being unpatentable over Cho, Yu, Kao and Furuta, in view of Endo (U.S. Patent Pub. No. 2013/0168832).
Regarding Claim 5
Cho as modified by Yu, Kao and Furuta discloses Claim 4. FIG. 4 of Yu further discloses the substrate (3) is formed of semiconductor material of the first conductivity type [0014], the at least one contact (63) of the second well (19) comprises a first contact coupled to VDD and comprising a region of the second conductivity type [0014]; the substrate comprises a second contact (65) coupled to Vss [0024], wherein the second contact comprises a region of the first conductivity type, located adjacent the second well.
Cho as modified by Yu, Kao and Furuta is silent with respect to “the second well comprises a third contact opposite the first contact, at the other side of the substrate compared to the first contact, the third contact comprising a region of the first conductivity type; the substrate comprises a fourth contact opposite the second contact, the fourth contact comprising a region of the second conductivity type; and the third and fourth contacts are coupled to the I/O rails, so that the ESD circuit is a double diode circuit formed by two diodes formed respectively by at least part of the junction between the substrate and the region of the fourth contact and by at least part of the junction between the second well and the region of the third contact”.
FIG. 6 of Endo discloses a similar component, wherein the second well comprises a third contact opposite the first contact, at the other side of the substrate compared to the first contact, the third contact comprising a region of the first conductivity type; the substrate comprises a fourth contact opposite the second contact, the fourth contact comprising a region of the second conductivity type; and the third and fourth contacts are coupled to the I/O rails, so that the ESD circuit is a double diode circuit formed by two diodes formed respectively by at least part of the junction between the substrate and the region of the fourth contact and by at least part of the junction between the second well and the region of the third contact.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cho, as taught by Endo. The ordinary artisan would have been motivated to modify Cho in the above manner for purpose of reducing parasitic capacitance and cost ([0005] of Endo).
Regarding Claim 6
Modified Cho discloses the second well further comprises a fifth contact, comprising a region of the first conductivity type, and located adjacent the fourth contact and at the same side of the substrate as the fourth contact, wherein the fifth contact is coupled to the I/O rails, so that the ESD circuit additionally comprises a bipolar transistor formed by: at least part of the junction between the region of the fifth contact and the second well, and at least part of the junction between the floating well and the second well.
Regarding Claim 7
Modified Cho discloses the substrate is formed of semiconductor material of the first conductivity type, the at least one contact of the second well comprises a first contact coupled to VDD and comprises a region of the second conductivity type, the substrate comprises a second contact coupled to Vss, the second contact comprising a region of the first conductivity type, located adjacent the second well, the second well comprises a third contact opposite the first contact, the third contact comprising a region of the first conductivity type, the second well comprises a fourth contact also opposite the first contact and adjacent the third contact, the fourth contact comprising a region of the second conductivity type, the second well comprises a fifth contact on the same side of the substrate as the third and fourth contacts but on the opposite side of the floating well, the fifth contact comprising a region of the second conductivity type, the substrate comprises a sixth contact adjacent the fifth contact and opposite the second contact, the sixth contact comprising a region of the second conductivity type, the substrate comprises a seventh contact adjacent the sixth contact and also opposite the second contact, the seventh contact comprising a region of the first conductivity type, the third contact and the sixth contact are coupled to the 1/0 rails, the fourth contact and the fifth contact are coupled to VDD, and the seventh contact is coupled to Vss, so that the ESD circuit is a double diode circuit comprising: a first set of two diodes formed respectively by a first portion of the junction between the substrate and the region of the sixth contact and by a first portion of the junction between the second well and the region of the third contact, a second set of two diodes formed respectively by a second portion of the junction between the substrate and the region of the sixth contact and by a second portion of the junction between the second well and the region of the third contact, and a bipolar transistor formed by: at least part of the junction between the region of the sixth contact and the substrate, and at least part of the junction between the floating well and the second well.
Pertinent Art
FIG. 4 of Wu (CN 101859762) discloses a semiconductor component comprising a semiconductor [0054] substrate (101) having a front side (105) and a back side (107), and comprising a first area (comprising 303) and a second area (comprising 301) not overlapping the first area, the areas extending from the front side of the substrate to the back side through a complete thickness of the substrate, the semiconductor component comprising: a device layer at the front side of the substrate, comprising a plurality of active devices (102) located in the first area, wherein the active devices are configured to receive input signals and to send output signals (I/O signals); a plurality of buried interconnect rails (I/O rails) (connection between 301 and 201) at least partially buried in the substrate, at the front side thereof, and located in the second area; a plurality of through substrate via (TSV) (301) connections (I/O TSVs) located in the second area, passing through the substrate from the I/O rails to the back side of the substrate, a front side redistribution layer (201) on the device layer, configured to route the I/O signals between the active devices in the first area and the I/O rails in the second area; input/output terminals (I/O terminals) (405) at the back side of the component; a back side redistribution layer (401) at the back side of the substrate configured to route the I/O signals between the I/O terminals on the back side of the component and a back end of the I/O TSVs; and a plurality of power supply terminals [0029] and conductors connected thereto, configured to supply power to the active devices, the power supply terminals being coupled to either a reference voltage Vss or a power voltage VDD [0057].
Pertinent art also includes Horng (U.S. Patent Pub. No. 2013/0147057), Lin (U.S. Patent Pub. No. 2010/0237386), and Cheng (CN 102201405).
Response to Arguments
Applicant's arguments with respect to Kao have been considered but they are not persuasive. Claim 1 recites “the first well is a floating well that is not provided with contacts for applying a bias voltage to the first well”. Bias voltage is a constant DC voltage applied to an electronic component to set a specific operating point, enabling proper function like amplification or ensuring a circuit’s integrity. It establishes the initial conditions for the component, allowing it to react to an AC signal or for a system to check for faults. Shielding voltage is a voltage often connected to a shield or guard conductor, which is designed to protect the inner conductors from EMI or high-voltage hazards. Bulk voltage is a specific type of voltage applied to the substrate or body of the transistor to control the transistor’s characteristics through the body effect. These voltages have different meanings and functions. For example, the elected FIGS 2A-2B of the application, first well 25 has a number of I/O terminals 19 on its back side which are connected to the I/O TSVs 16b through conductors of the back side redistribution layer 17 [0074].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897