DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 22, 2026 has been entered.
Response to Amendment
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “wherein the electronic component is mounted on the terminals of the circuit substrate according to Claim 1”. This phrase is unclear because “an electronic component” is not previously introduced in Claim 1.
Appropriate action is required. For purposes of compact prosecution, Claim 6 is interpreted to instead recite “wherein an electronic component is mounted on the terminals of the circuit substrate according to Claim 1”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hiroki et al. (“Hiroki”), JP2005038955 (see previous machine translation for citations).
Regarding Claim 1, Hiroki discloses circuit substrate (1; Fig. 1; ¶ 0019) having at least one pair of terminals (2; ¶ 0020), wherein
a bonding material (4; ¶ 0024) containing a metal element (¶ 0024) is disposed above the terminals (¶ 0022),
the pair of terminals and the bonding material are disposed inside (Fig. 1) a wall (5; Fig. 1; ¶ 0019, 0026) formed by an insulator (0019), and
the wall has an uneven portion (8; Figs. 4-6; ¶ 0029-0031) on a first inner side surface (Figs. 4-6 the bottom inner side surface) and a second inner side surface (Figs. 4-6 the top inner side surface),
wherein a constituent material (6; Figs. 1-2; ¶ 0027-0028 “adhesive 6”) is disposed between the bonding material (4; Fig. 2) and the wall (5; Fig. 2) along a direction in which the first inner side surface (the bottom inner side surface of wall 5) and the second inner side surface (the top inner side surface of wall 5) face each other (Fig. 2 in this instance regarding the bottom electronic component 3, the bottom inner side surface of wall 5 faces the top inner side surface of wall 5, there are two vertical interfaces between the lower portions of bonding 4 and constituent 6, there are two vertical interfaces between the upper portions of bonding 4 and constituent 6, there is a horizontal interface between constituent 6 and lower inside surface of wall 5, there is a horizontal interface between constituent 6 and upper inside surface of wall 5, therefore constituent 6 is between bonding 4 and inside surfaces of wall 5 that face each other).
Regarding Claim 2, Hiroki discloses wherein the uneven portion extends in a thickness direction (Figs. 4-6; ¶ 0029-0031) of the circuit substrate.
Regarding Claim 6, Hiroki discloses a mounted substrate (Fig. 1), wherein the electronic component (3; Figs. 1-2; ¶ 0023, 0027-0028) is mounted on the terminals of the circuit substrate according to claim 1 (mounted on the terminals as described in ¶ 0019, see Claim 1 rejections, supra, for all other limitations of Claim 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroki et al. (“Hiroki”), JP2005038955.
Regarding Claim 3, Hiroki discloses Claim 1, as described supra.
Hiroki does not disclose wherein, in plan view, when a reference line is set in a direction in which the first inner side surface expands, and a length of the reference line is set to a length a, and a length of the wall corresponding to the reference line is set to a length L, wherein a ratio of the length to the length a is greater than or equal to 1.02 and less than or equal to 1.20.
MPEP 2144.04(IV)(A) states Changes in Size/Proportion: In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed application to have the wall 5 in Fig. 5 of Hiroki shaped such that in plan view, when a reference line is set in a direction in which the first inner side surface expands, and a length of the reference line is set to a length a, and a length of the wall corresponding to the reference line is set to a length L, wherein a ratio of the Length L to the length a is greater than or equal to 1.02 and less than or equal to 1.20 in order to prevent the bonding material 4 from overflowing the wall 5, thereby preventing a short circuit (Hiroki ¶ 0031).
Regarding Claim 4, Hiroki discloses Claim 1, as described supra.
Hiroki does not disclose wherein, in plan view, when a reference line is set in a direction in which the first inner side surface expands, the wall has 40 or more and 1200 or less uneven portions per 1 mm of the reference line.
Hiroki in Fig. 5 explicitly discloses the inner side surface of wall 5 having numerous uneven portions (in this instance 20 uneven portions). Similarly, ¶ 0029 of Hiroki explicitly discloses the “unevenness” of wall 5 in plan view.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed application to have the wall 5 in Fig. 5 of Hiroki shaped such that in plan view, when a reference line is set in a direction in which the first inner side surface expands, the wall has 40 or more and 1200 or less uneven portions per 1 mm of the reference line in order to prevent the bonding material 4 from overflowing the wall 5, thereby preventing a short circuit (Hiroki ¶ 0031). It has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The changes involve routine skill in the art, MPEP 2144.05(II)(A).
Regarding Claim 7, Hiroki discloses wherein the wall further has a third inner side surface (Fig. 6; another bottom inner side surface of wall 5, see annotated Fig. 6 infra) and a fourth inner side surface (Fig. 6; another top inner side surface of wall 5, see annotated Fig. 6 infra).
Hiroki lacks specifically disclosing the constituent material contacts the first, second, third and fourth inner side surfaces of the wall.
It would be obvious for Hiroki to have wherein the constituent material contacts the first, second, third and fourth inner side surfaces of the wall to eliminate a short circuit (¶ 0030 having constituent material 6 contact the first, second, third and fourth inner side surfaces of the wall will “reliably…eliminate a short circuit” between the bonding materials 4, plus having constituent material 6 contact the first, second, third and fourth inner side surfaces of the wall will “reliably…eliminate a short circuit” between the terminals 2, see also ¶ 0013-0015 and 0029).
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Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hiroki et al. (“Hiroki”), JP2005038955 as applied to claim 1 above, and further in view of Kazuji et al. (“Kazuji”), JP2006093523 (listed on the IDS filed 21 November 2022, see previous machine translation for citations).
Regarding Claim 5, Hiroki discloses Claim 1, as described supra.
Hiroki does not disclose wherein a reflector is formed on an upper surface of a base material on which the wall is provided inside the wall.
Kazuji discloses wherein a reflector (5; Fig. 5; ¶ 0038) is formed on an upper surface (Fig. 5) of a base material (21; Fig. 5; ¶ 0032) on which the wall is provided inside the wall (Fig. 5; ¶ 0034, 0038 “the fluorescent material 5 is applied to the upper surface (and part of the side surface) of the LED chips 3 mounted in each cavity”, therefore material 5 is inside the wall).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed application to form a reflector on an upper surface of a base material inside the wall in order to convert light emitted from an LED chip into white light (Kazuji ¶ 0031), thereby increasing the functionality of the circuit substrate.
Response to Arguments
The applicant states (pages 4-5) that Hiroki does not “teach the adhesive between the conductive resin and wall along a direction in which the two inner side surfaces face each other.”
As explained supra, Hiroki discloses wherein a constituent material (6; Figs. 1-2; ¶ 0027-0028 “adhesive 6”) is disposed between the bonding material (4; Fig. 2) and the wall (5; Fig. 2) along a direction in which the first inner side surface (the bottom inner side surface of wall 5) and the second inner side surface (the top inner side surface of wall 5) face each other (Fig. 2 in this instance regarding the bottom electronic component 3, the bottom inner side surface of wall 5 faces the top inner side surface of wall 5, there are two vertical interfaces between the lower portions of bonding 4 and constituent 6, there are two vertical interfaces between the upper portions of bonding 4 and constituent 6, there is a horizontal interface between constituent 6 and lower inside surface of wall 5, there is a horizontal interface between constituent 6 and upper inside surface of wall 5, therefore constituent 6 is between bonding 4 and inside surfaces of wall 5 that face each other).
The applicant states (pages 5-6) that new dependent “claim 7 is allowable for its dependency from an allowable base claim and also for the features that it recites.”
As explained supra, Hiroki discloses wherein the wall further has a third inner side surface (Fig. 6; another bottom inner side surface of wall 5, see annotated Fig. 6 supra) and a fourth inner side surface (Fig. 6; another top inner side surface of wall 5, see annotated Fig. 6 supra).
It would be obvious for Hiroki to have wherein the constituent material contacts the first, second, third and fourth inner side surfaces of the wall to eliminate a short circuit (¶ 0030 having constituent material 6 contact the first, second, third and fourth inner side surfaces of the wall will “reliably…eliminate a short circuit” between the bonding materials 4, plus having constituent material 6 contact the first, second, third and fourth inner side surfaces of the wall will “reliably…eliminate a short circuit” between the terminals 2, see also ¶ 0013-0015 and 0029).
Independent Claim 1 is rejected for at least the reasons stated supra. Dependent Claims 2-7 are rejected for at least the reasons stated supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rose Keagy whose telephone number is (571)270-3455. The examiner can normally be reached Mon-Fri. 8am-5pm (CT).
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818