DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 26 November 2025 have been fully considered but they are respectfully not found persuasive.
Regarding the arguments relating to the 35 USC 112(b) rejection of claim 7 (Remarks; page 6-7). Applicant has amended claim 7 to recite what is in the instant specification at ¶0058. However, Applicant has not fully addressed the issue pointed out in the previous Office action (previous Office action, page 2) of “It is unclear how the concentration of C affects the capacitance of the second separation layer (for example, does an increase in carbon concentration increase the capacitance or decrease it”.
The claim nor the specification provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter regarding the relationship between C concentration and its specific relationship to its effect on the capacitance in SiCN. The rejection is maintained.
Regarding the argument relating to the 35 USC 103 rejection of claim 1 (Remarks; pages 7-9). Applicant has not amended the claims with sufficient specificity to overcome the prior art of record (such as claiming limitations relating the separation film and memory layers). Applicant states “the memory layers ML [of Choi] are not included within the channel separating pattern CI”. However, the limitations of the claim do not require such structure. The claim merely requires “a plug separation pattern separating the main plug into first and second sub-plugs … including a gap and a separation layer surrounding the gap.” The claims do not recite any memory layers. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The rejections have been updated below, as necessitated by the amendment.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, it recites “wherein capacitance of the second separation layer is proportional to a concentration of carbon (C) included in the SiCN”. It is unclear how the concentration of C is proportional to the capacitance of the second separation layer (for example, does an increase in carbon concentration increase the capacitance or decrease it”. The specification is silent regarding this, and does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter regarding the specific relationship between C concentration and its proportional effect on the capacitance in SiCN.
For the purpose of examination, this claim is satisfied by meeting the limitations of claim 6, wherein the second separation layer includes SiCN, which inherently has a carbon concentration in it.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-11, and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jung Dal Choi et al. (US 20210020203 A1; hereinafter Choi) in view of Minori Kajimoto et al. (US 20230371266 A1; hereinafter Kajimoto).
PNG
media_image1.png
524
806
media_image1.png
Greyscale
Regarding Claim 1, Choi teaches a memory device, comprising:
a stacked structure (Fig. 6A; GST; ¶0059) including gate lines (Fig. 6A; GST includes gate lines WL1 to WLn; ¶0057; hereinafter WL), wherein the gate lines (WL) are stacked in a vertical direction (D3), and wherein the gate lines (WL) are separated from each other (WL are separated from each other by IL; ¶0068);
a main plug (in view of Fig. 2A and Fig. 3A; main plug PL; ¶0043) extending in the vertical direction through the stacked structure (as shown in view of Fig. 6; wherein the main plug comprising CI extends through the stacked structure GST);
a plug separation pattern (Fig. 2A, Fig. 3A, Fig. 6; comprising CI/MLa/MLb; ¶0043, ¶0050) separating the main plug (PL) into first and second sub-plugs (CI/MLa/MLb separates main plug PL into sub-plugs comprising CHa and CHb respectively; ¶0047);
wherein the plug separation pattern (CI/MLa/MLb) includes:
an insulating material (CI comprises an insulating material; ¶0047); and
a separation layer (Fig. 3A in view of Fig. 6; MLa/MLb; ¶0050) surrounding the insulating material (MLa/MLb surrounds the insulating material of CI).
Choi is silent regarding what material is used as the insulating material. Specifically, that the insulating material is a gap.
In the same field of endeavor, Kajimoto teaches a memory device including a gate line stack (Fig. 24B; 31; ¶0021) separated from each other (by 32; ¶0022), wherein a plug (pillar body 40; ¶0020) is separated into sub plugs (Fig. 24B; 41 and 42) by a separation pattern (Fig. 24B; 43c) which is an air gap instead of a core insulating pillar (Kajimoto; ¶0084).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gap of Kajimoto as the insulating material of Choi in order to reduce parasitic capacitance and improve performance of the memory cell (Kajimoto; ¶0085). Furthermore, Kajimoto teaches a core insulating material (Kajimoto; Fig. 23B; 43a; ¶0080) and an air gap (Kajimoto; Fig. 24B; 43c) are equivalent as an insulating material for the intended use of separating semiconductor memory elements.
Regarding Claim 2, modified Choi teaches the memory device of claim 1, wherein the separation layer (MLa/MLb) includes a first separation layer (Choi; Fig. 3A; BI), a second separation layer (Choi; Fig. 3A; DL), and a third separation layer (Choi; Fig. 3A; TI).
Regarding Claim 3, modified Choi teaches the memory device of claim 2, wherein the gap (as modified, CI) is surrounded by the third separation layer (TI), the third separation layer (TI) has a curved side wall (as shown in Choi Fig. 3A), the second separation layer (DL) surrounds the curved side wall of the third separation layer (TI) to have a curved side wall (as shown in Choi Fig. 3A), and the first separation layer (BI) surrounds the curved side wall of the second separation layer (DL) (as shown in Choi Fig. 3A).
Regarding Claim 4, modified Choi teaches the memory device of claim 2, wherein each of the first separation layer (BI) and the third separation layer (TI) includes an insulating material (Choi; ¶0050).
Regarding Claim 8, modified Choi teaches the memory device of claim 1, wherein the main plug (Choi Fig. 2A; PL) includes a core pillar (CO; ¶0049), a channel layer (CL; ¶0044, ¶0049), a tunnel isolation layer (TI; ¶0050), a charge trap layer (DL; ¶0050), and a blocking layer (BI; ¶0050) extending in the stacked structure (as shown in view of Choi Fig. 6).
Regarding Claim 9, modified Choi teaches the memory device of claim 1, wherein the first (comprising CHa) and second (comprising CHb) sub-plugs are substantially symmetrical to each other with respect to the plug separation pattern (CI/MLa/MLb) (as shown in Choi Fig. 3A).
Regarding Claim 10, modified Choi teaches the memory device of claim 1, wherein the plug separation pattern (CI/MLa/MLb) extends in the main plug (PL) and the stacked structure (GST) (as shown in Choi Fig. 3A/ 6A).
Regarding Claim 11, modified Choi teaches the memory device of claim 2, wherein the gap (CI as modified by Kajimoto) and the first to third separation layers (BI, DL, TI respectively) are formed in the plug separation pattern to extend in the main plug (PL) and the stacked structure (GST) (as shown in Choi Fig. 3A in view of Fig. 6A).
Regarding Claim 13, modified Choi teaches the memory device of claim 2, wherein the separation layer (MLa/MLb) includes a sub-separation region contacting the first and second sub-plugs (CHa and CHb, respectively) (Choi; Fig. 3A/6A; sub-separation regions are where MLa contacts CHa and MLb contacts CHb in a region above the lowemost conductive line SSL of the stack GST).
Regarding Claim 14, Choi teaches the memory device of claim 13, wherein, except for the sub-separation region (region above SSL in Choi Fig. 6A), the second separation layer (DL of MLb/MLa) directly contacts a source line (as shown in Choi; Fig. 6A; source line SL; ¶0054; SL directly contacts MLa/MLb at a bottom end, and since the first, second, and third separation layers are stacked radially {as shown in view of Fig. 3A} each separation layer of MLa/MLb is directly contacting SL).
Regarding Claim 15, modified Choi teaches the memory device of claim 14, wherein the first separation layer (BI) overlaps with the first and second sub-plugs (as shown in Choi Fig. 3A; wherein BI overlaps sub plugs comprising CHa and CHb laterally and/or vertically).
Regarding Claim 16, modified Choi teaches the memory device of claim 1, wherein the gap constitutes an air gap (as modified by Kajimoto; 43c is an airgap; ¶0084).
Regarding Claim 17, modified Choi teaches the memory device of claim 1, wherein the gap includes a gas (as modified by Kajimoto, gap 43c is an air gap, and air is a gas, however Kajimoto also describes in ¶0084 that it may be an inert gas).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jung Dal Choi et al. (US 20210020203 A1; hereinafter Choi) in view of Minori Kajimoto et al. (US 20230371266 A1; hereinafter Kajimoto) and non-patent literature “Characterization of Low-Dielectric Constant Silicon Carbonitride (SiCN) Dielectric Films for Charge Trapping Nonvolatile Memories” by Shiekh Rashel Al Ahmed et al. (2015) (hereinafter Ahmed).
Regarding Claim 5, modified Choi teaches the memory device of claim 2, but is silent regarding wherein the second separation layer (DL) includes a low-k material. Although Choi is silent regarding the material, Choi discloses in ¶0050 that DL may be a charge trap film.
In the same field of endeavor, Ahmed teaches using SiCN as a charge trap film material in a non-volatile memory device (Ahmed, Section 4 Summary; “We suggest that the presence of such deep traps resulted in the long-term data retention of the SiCN-based memory capacitors. The SiCN dielectric films with a low-dielectric constant can be employed as the charge trapping layer of NVMs.”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the SiCN (which is a low-k material) charge trapping layer of Ahmed for the charge trapping layer (DL) of Choi in order to obtain long term data retention (as quoted above from Ahmed).
Regarding Claim 6, modified Choi teaches the memory device of claim 5, wherein the low-k material includes SiCN (as modified by Ahmed).
Regarding Claim 7, modified Choi teaches the memory device of claim 6, wherein capacitance of the second separation layer is proportional to a concentration of carbon (C) included in the SiCN (since this is a device claim this limitation is satisfied as modified by Ahmed, wherein the second separation layer is SiCN and inherently contains a concentration of carbon).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jung Dal Choi et al. (US 20210020203 A1; hereinafter Choi) in view of Minori Kajimoto et al. (US 20230371266 A1; hereinafter Kajimoto) and Tin-Wei Wu et al. (US 9543319 B1; hereinafter Wu).
Regarding Claim 12, modified Choi teaches the memory device of claim 1, but does not expressly disclose wherein the plug separation pattern (CI/MLa/MLb) includes a blocking pattern surrounded by the separation layer over the gap.
In the same field of endeavor, Wu teaches a memory device (Wu; Fig. 1E) comprising a separation pattern (118; C4:L23-37) surrounded by a separation layer (122 separates 112a and 102; C4:L55-C5:L6), wherein the separation pattern (118) includes a gap (116; C4:L1-12) and a blocking pattern (120 which blocks 114a from exposure) that is surrounded by the separation layer (122) and over the gap (116).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the blocking pattern over the gap (of Wu) in the device of modified Choi in order to fill the opening in such a way as to make a planar top surface of the device (Wu; Fig. 1E; C5:L28-C6:L8).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights