DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 18 March 2026 has been entered.
Response to Arguments
Applicant’s arguments/amendments, see Remarks/Claims, filed 18 March 2026, with respect to the rejection(s) of the claims in the previous Office action have been fully considered and are persuasive. Therefore, the rejection(s) of 21 January 2026 have been withdrawn. However, upon further consideration or the amendment which adds new limitations while broadening other limitations, a new ground(s) of rejection is made in view of Choi and Kajimoto (of record), as well as in view of newly cited references Yu-Wei Jiang et al. (US 20200335510 A1) and Hang-Ting Lue (US 20160260732 A1). The updated rejections are presented below in detail.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 8, as amended, it recites “The memory device of claim 1, wherein increases as each of the memory patterns includes a core pillar…”. It is unclear as to what increases, and the overall construction of the claim is incomprehensible. As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of claim 8, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP 2173.06 II.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu-Wei Jiang et al. (US 20200335510 A1; hereinafter Jiang).
Regarding Claim 1, Jiang discloses a memory device (Fig. 20A, Fig. 20B; ¶0004 and all relevant paragraphs related to the elements below), comprising:
a stacked structure including gate lines (220; ¶0065; commensurate in scope with the instant specification [0065]), wherein the gate lines (220) are stacked in a vertical direction (Fig. 20B), and wherein the gate lines (220) are separated from each other (by 130);
a main plug (310/320) extending in the vertical direction through the stacked structure and including memory patterns (two memory patterns 140; ¶0038); and
a plug separation pattern (160/152/240) separating the main plug into first (310) and second (320) sub-plugs,
wherein the plug separation pattern (160/152/240) includes:
a gap (a gap between the adjacent sections of 160/152); and a separation layer (160/152) disposed between the gap and each of the memory patterns (160/152 is between the gap and each respective memory pattern 140 of the respective sub-plugs 310/320, as shown in Fig. 20A and Fig. 20B).
Regarding Claim 9, Jiang discloses the memory device of claim 1,
wherein the first (310) and second (320) sub-plugs are substantially symmetrical to each other with respect to the plug separation pattern (as shown in Fig. 20A).
Regarding Claim 10, Jiang discloses the memory device of claim 1,
wherein the first (310) and second (320) sub-plugs are spaced apart from each other by the plug separation pattern (160/152) interposed therebetween (as shown in Fig. 20A/20B).
Claims 1, 9, 10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hang-Ting Lue (US 20160260732 A1; hereinafter Lue).
Regarding Claim 1, Lue discloses a memory device (Fig. 15, 19, 27, and all relevant paragraphs related to the elements below), comprising:
a stacked structure including gate lines (GSL/WL/SSL; ¶0044), wherein the gate lines are stacked in a vertical direction (Z), and wherein the gate lines are separated from each other (by 1121/1122/1123/1124/1125);
a main plug (including 1130/1131/1132/1155 in view of Fig. 15 and Fig. 19) extending in the vertical direction (Z) through the stacked structure and including memory patterns (memory patterns include adjacent and separated 1130/1131/1132; ¶0147); and
a plug separation pattern (1160/1161/1155) separating the main plug into first and second sub- plugs (adjacent sub plugs including 1130/1131/1132),
wherein the plug separation pattern includes:
a gap (1161; ¶0152); and a separation layer (1155) disposed between the gap (1161) and each of the memory patterns (1130/1131/1132).
Regarding Claim 9, Lue discloses the memory device of claim 1,
wherein the first and second sub-plugs are substantially symmetrical to each other with respect to the plug separation pattern (as shown in Fig. 15, 19, and 26).
Regarding Claim 10, Lue discloses the memory device of claim 1,
wherein the first and second sub-plugs (adjacent 1130/1131/1132) are spaced apart from each other by the plug separation pattern (1161/1162/1155) interposed therebetween (Fig. 26).
Regarding Claim 12, Lue discloses the memory device of claim 1,
wherein the plug separation pattern (1160/1161/1155) includes a blocking pattern (1160) surrounded by the separation layer (1155) over the gap (1161).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lue in view of Minori Kajimoto et al. (US 20230371266 A1; hereinafter Kajimoto).
Regarding Claim 16, Lue discloses the memory device of claim 1, but does not expressly disclose wherein the gap (1161) constitutes an air gap.
In the same field of endeavor, Kajimoto teaches a memory device including a gate line stack (Fig. 24B; 31; ¶0021) separated from each other (by 32; ¶0022), wherein a plug (pillar body 40; ¶0020) is separated into sub plugs (Fig. 24B; 41 and 42) by a separation pattern (Fig. 24B; 43c) which is an air gap (Kajimoto; ¶0084).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the gap of Lue would be an air gap as in Kajimoto, in order to reduce parasitic capacitance and improve performance of the memory cell (Kajimoto; ¶0085).
Regarding Claim 17, Lue discloses the memory device of claim 1, but does not expressly disclose wherein the gap includes a gas.
In the same field of endeavor, Kajimoto teaches a memory device including a gate line stack (Fig. 24B; 31; ¶0021) separated from each other (by 32; ¶0022), wherein a plug (pillar body 40; ¶0020) is separated into sub plugs (Fig. 24B; 41 and 42) by a separation pattern (Fig. 24B; 43c) which is an inert gas (Kajimoto; ¶0084).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the gap of Lue would include an inert gas as in Kajimoto, in order to reduce parasitic capacitance and improve performance of the memory cell (Kajimoto; ¶0085).
Claims 1, 2, 5, 9-11, 13, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jung Dal Choi et al. (US 20210020203 A1; hereinafter Choi) in view of Kajimoto.
Regarding Claim 1, Choi teaches a memory device, comprising:
a stacked structure (Fig. 6A; GST; ¶0059) including gate lines (Fig. 6A; GST includes gate lines WL1 to WLn; ¶0057; hereinafter WL), wherein the gate lines (WL) are stacked in a vertical direction (D3), and wherein the gate lines (WL) are separated from each other (WL are separated from each other by IL; ¶0068);
a main plug (in view of Fig. 2B and Fig. 3B; main plug PL; ¶0043) extending in the vertical direction through the stacked structure (as shown in view of Fig. 6; wherein the main plug comprising CI extends through the stacked structure GST) and including memory patterns (memory patterns MLa and MLb; ¶0043);
a plug separation pattern (Fig. 2B, Fig. 3B, Fig. 6; comprising CI/CO/CL; ¶0043, ¶0049) separating the main plug (PL) into first and second sub-plugs (Fig. 3B; STRa and STRb comprising MLa and MLb; ¶0047);
wherein the plug separation pattern (CI/CO/CL) includes:
an insulating material (CI comprises an insulating material; ¶0047); and
a separation layer (Fig. 3B in view of Fig. 6A; CO/CL) disposed between the insulating material (CI) and each of the memory patterns (MLa/MLb) (as shown in Fig. 3B).
Choi is silent regarding what material is used for the insulating material (CI). Specifically, that the insulating material is a gap.
In the same field of endeavor, Kajimoto teaches a memory device including a gate line stack (Fig. 24B; 31; ¶0021) separated from each other (by 32; ¶0022), wherein a plug (pillar body 40; ¶0020) is separated into sub plugs (Fig. 24B; 41 and 42) by an insulating material (Fig. 24B; 43; ¶0022) which includes an air gap (43c; ¶0084) surrounded by an insulating film (43b; ¶0080).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the insulating structure (43) including the air gap (43c) surrounded by an insulating film (43b) of Kajimoto as the insulating material (CI) of Choi in order to reduce parasitic capacitance and improve performance of the memory cell (Kajimoto; ¶0085). This would result in a structure including Kajimoto’s insulating layer (43b) surrounding the air gap (43c) replacing Choi’s insulating material (CI) in Choi Fig. 3B.
Regarding Claim 2, modified Choi teaches the memory device of claim 1, wherein the separation layer (as modified wherein Choi’s CI is replaced by the insulation structure 43 of Kajimoto including the air gap 43c surrounded by the insulating film 43b) includes a first separation layer (Kajimoto; 43b surrounding the air gap), a second separation layer (Choi; Fig. 3B; CO), and a third separation layer (Choi; Fig. 3B; CL).
Regarding Claim 5, modified Choi teaches the memory device of claim 2, but does not expressly disclose wherein the second separation layer (CO) includes a low-k material.
However, Kajimoto discloses in ¶0030 that any low-k material is suitable for the purpose of a core insulating material in a memory device pattern.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a low-k material as the insulating material of (CO) because the substitution of a known equivalent (insulating material) for another known equivalent (insulating material) for the art-recognized suitability for its intended purpose is a prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 9, modified Choi teaches the memory device of claim 1, wherein the first (STRa) and second (STRb) sub-plugs are substantially symmetrical to each other with respect to the plug separation pattern (as shown in view of Choi Fig. 3B).
Regarding Claim 10, modified Choi teaches the memory device of claim 1, wherein the plug separation pattern (as modified; CI replaced by 43 of Kajimoto/CO/CL) extends in the main plug (PL) and the stacked structure (GST) (as shown in Choi Fig. 3B/ 6A).
Regarding Claim 11, modified Choi teaches the memory device of claim 2, wherein the gap (43c as modified by Kajimoto) and the first to third separation layers (43b, CO, CL respectively) are formed in the plug separation pattern to extend in the main plug (PL) and the stacked structure (GST) (as shown in Choi Fig. 3B in view of Fig. 6A).
Regarding Claim 13, modified Choi teaches the memory device of claim 2, wherein the separation layer (43b/CO/CL) includes a sub-separation region contacting the first and second sub-plugs (MLa and MLb, respectively) (Choi; Fig. 3B/6A; sub-separation regions are where CI contacts MLa/MLb).
Regarding Claim 16, modified Choi teaches the memory device of claim 1, wherein the gap constitutes an air gap (as modified by Kajimoto; 43c is an airgap; ¶0084).
Regarding Claim 17, modified Choi teaches the memory device of claim 1, wherein the gap includes a gas (as modified by Kajimoto, gap 43c is an air gap, and air is a gas, however Kajimoto also describes in ¶0084 that it may be an inert gas).
Allowable Subject Matter
Claims 3-4, 6-7, and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior art of record teaches the device of claim 2. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the gap is surrounded by the third separation layer, the third separation layer has a curved side wall,
the second separation layer surrounds the curved side wall of the third separation layer to have a curved side wall, and
the first separation layer surrounds the curved side wall of the second separation layer.
Regarding Claim 4, the prior art of record teaches the device of claim 2. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein each of the first separation layer and the third separation layer includes an insulating material.
Regarding Claim 6, the prior art of record teaches the device of claim 5. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the low-k material includes SiCN. For at least this reason, claim 7 would also be allowable based on its dependency from claim 6.
Regarding Claim 14, the prior art of record teaches the device of claim 13. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein, except for the sub-separation region, the second separation layer directly contacts a source line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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