DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 6/9/2026. Claims 1-25 are pending and have been examined. Claims 1, 8, 10, 16 and 19 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-15 are objected to because of the following informalities:
In regard to claim 1, line 10 amend the limitation “the host processor” to “the host processor device” as to use language consistent with line 4 and to correct a minor antecedent basis issue.
Claims 2-15 are dependent upon one of the claims above and therefore are similarly objected to for including the deficiencies of one of the claims above.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are mailbox manager to determine/read/write/verify in claim 1, 10 and 19. The examiner interprets the manager to be firmware and/or hardware circuitry as disclosed in paragraphs [0132-0133].
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claim 1, lines 8-9 stating “and the first executable is written to the mailbox register by the host processor device, wherein the first executable is cryptographically authenticated by the host processor…” lacks clarity and is indefinite because the limitation is inconsistent with the specification (See MPEP 2173.03). The limitation is inconsistent with the specification because paragraphs [0066, 0070 and 0072] appear to disclose that the host device may sign, encrypt or cryptographically secure executable code and write said code to a mailbox, then the XPU authenticates or verifies the executable based on the signature or secure data written. However, it does not appear that the host processor is authenticating or verifying the executable code, the XPU is performing the authentication based on the signature of the host. Thus, the claim limitation is indefinite based on the above inconsistency.
For purposes of examination the examiner will interpret the claim limitation as disclosed in paragraphs [0066, 0070 and 0072] of the specification and as claimed in claim 19 which states “…wherein the first executable is cryptographically secured by the host processor…”.
In regard to claim 6, the limitation stating “…wherein the mailbox manager is implemented in hardware circuitry” lacks clarity in light of the amendments made to claim 1. As current claim 1 now states “a mailbox manager executable by the processor circuitry”, it is unclear how the mailbox manager can be implemented in hardware if it is executable software (e.g. hardware cannot be executed or an executable implemented in hardware)? The examiner suggests amending claim 1 to correct the issue or cancelling claim 6.
Claim 16 is similarly rejected on the same basis as claim 1 above.
Claims 2-15 and 17-18 are dependent upon one of the claims above and therefore are rejected for including the deficiencies of one of the claims above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 13, 15-17, 19-21 and 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, PGPUB No. 2019/0052617 (cited on IDS filed on 12/29/22), Pappachan, PGPUB No. 2020/0137031 (cited on 892 filed on 3/9/2026) and further in view of Wallach, PGPUB No. 2009/0070553.
In regards to claim 1, Chen discloses An apparatus (See Figs. 8 and 11) comprising: processor circuitry ([0067 and 0084]: combination of 830, 840, 845 and 850 (See Fig. 8)) a memory (See Fig. 8: combination of elements 855 and 870) a port to couple to a host processor device via an interconnect ([0060 and 0066]: wherein a port couples a host processor device (element 510) via interconnect (element 802)(See Fig. 8)) a mailbox manager executable by the processor circuitry ([0067 and 0082]: wherein element 835 executed using hardware circuits of element 505 facilitates communication between host and device (element 505) using mailbox, and thus manages the mailbox) to: determine that a ready value in a mailbox register identifies that a first message is written to a particular location in the mailbox register ([0069-0070 and 0082-0083]: wherein a Go bit (See Fig. 10I) in a mailbox register (extended capability register (element 870)) identifies that a first message is written to a write mailbox location in the mailbox register (See Fi. 10L) (See Figs. 9 and 11)) wherein the mailbox register is implemented in the memory (Fig. 8: wherein memory is interpreted to be combination of element 855 and 870, thus mailbox register (element 870 of Fig. 9) is implemented in memory) and the first message is written to the mailbox register by the host processor device ([0082-0083]: wherein message is written to the mailbox register by host processor (element 510)) read the first message from the particular location in the mailbox register ([0083-0084]: wherein device (element 505) reads message in order to consume or process message) wherein the processor circuitry is to execute the first message to generate a result ([0083-0084]: wherein processing engines of device (element 505) execute message to generate a result) and write an execution finished value to the mailbox register based on execution of the first message by the processor circuitry. ([0083]: wherein a response ready value is written to mailbox register based on execution of message (also see Fig. 10H))
Chen does not explicitly disclose a first executable is written to a particular location nor wherein the first executable is cryptographically authenticated by the host processor. Chen does disclose transferring messages or instructions from a host to a device, wherein the host has a crypto engine which performs cryptographical tasks in connection with authentication (see [0066]). However, Chen does not explicitly disclose a host authenticating a first message, which is then written by the host to a mailbox.
Pappachan discloses wherein the first message is cryptographically authenticated by the host processor ([0098-0105]: wherein the host processor provides cryptographic parameters and/or a key to allow a device to authenticate or verify the message sent by the processor (e.g. cryptographically securing a message) (note: limitation is interpreted as discussed above in 112(b) rejection section))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify host processor of the authentication architecture of Chen to cryptographically secure communication as the host processor of Pappachan. It would have been obvious to one of ordinary skill in the art because it would allow a secure communication channel to be set up between a host and a trusted device which would allow secrets to be provisioned to the trusted device (Pappachan [0047]). Thus, mutual authentication could be performed to protect data access between devices (e.g. preventing rogue devices from accessing secret data).
The combination of Chen and Pappachan does not explicitly disclose a first executable is written to a particular location. Chen does disclose transferring of messages or instructions from a host to a device using a mailbox (see [0069]). However, Chen does not explicitly disclose transferring of executables between a host and a device.
Wallach discloses a first executable is written to a particular location. ([0065-0066 and 0083-0084]: wherein an executable is written to a co-processor location (See Figs. 3 and 5))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Chen which transfers messages or instructions to a co-processor device to transfer executables as disclosed in Wallach. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (transferring executables to a co-processor as taught in Wallach) for another (transferring generic instructions/messages to a co-processor as taught in Chen) to yield predictable results (transferring executables to a co-processor device using a mailbox register) (MPEP 2143, Example B).
Claim 19 is similarly rejected on the same basis as claim 1 above as claim 19 is the system corresponding to the apparatus of claim 1 above. (Note: Chen [0066 and Fig. 8] discloses a system)
In regard to claim 2, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) wherein the mailbox register comprises a ready value field for the ready value, an execution finished value field for the execution finished value, and a received executables region, wherein the received executables region comprises the particular location. (Chen [0069-0070]: wherein the mailbox register comprises a Go bit field for the ready value, a response ready field for the response finished value and a write mailbox field for the messages/instructions (See Figs. 9, 10I, 10H and 10L) |Wallach: Figs. 3 and 5 for memories storing executables)
In regard to claim 3, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 2 (see rejection of claim 2 above) wherein the mailbox manager is to: write a result value associated with the result to an output region of the mailbox. (Chen [0081 and 0083-0084])
In regard to claim 4, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 2 (see rejection of claim 2 above) wherein the mailbox register further comprises an executable offset field to identify where executables are written within the received executables region, and an output offset field to identify where results are written within the output region. (Chen: See Fig. 9: wherein mailbox register structure comprises offset field including 2Ch to identify write mailbox region where messages are written and offset field 30h to identify where results are written within read mailbox (note the combination with Wallach discloses the executables and thus the combination discloses the above limitations))
In regard to claim 5, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) wherein the mailbox manager is implemented in firmware. (Chen [0067 and 0082])
In regard to claim 6, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) wherein the mailbox manager is implemented in hardware circuitry. (Chen [0067 and 0082])
In regards to claim 7, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) wherein the first executable comprises a portion of a program, and another portion of the program comprises a second executable to be executed by the host processor device (Wallach [0065-0066]: wherein a portion of an executable is processed by co-processor and another portion is a second executable executed by the host processor (See Figs. 3 and 5))
In regard to claim 8, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) further comprising a capability register to identify to the host processor device that a vendor-defined capability is supported, wherein the vendor-defined capability associated with use of mailbox registers to accept executables from the host processor device. (Chen [0070, 0072, 0087 and Fig. 9] (note the combination with Wallach discloses the executables and thus the combination discloses the above limitations))
In regard to claim 9, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 8 (see rejection of claim 8 above) wherein the vendor-defined capability comprises a vendor specific capability according to a Peripheral Component Interconnect Express (PCIe)-based protocol. (Chen [0072 and 0087])
In regard to claim 13, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) wherein the interconnect is compliant with a PCIe-based protocol (Chen [0066]) and the host processor device is to read from and write to the mailbox register based on the PCIe-based protocol. (Chen [0066, 0082 and Figs. 8 and 11])
Claims 24-25 are similarly rejected on the same basis as claim 13 above as claims 24-25 are the system corresponding to the apparatus of claim 13 above.
In regard to claim 15, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) wherein the processor circuitry comprises one of a graphics processing unit (GPU), network processing unit (NPU), tensor processing unit (TPU), infrastructure processing unit (IPU), or hardware accelerator. (Chen [0067, 0074 and 0083-0084]: wherein the processing circuitry is a hardware accelerator for cryptography/authentication (See Figs. 8 and 11))
In regards to claim 16, Chen discloses A method comprising: sending one or more first write requests, from a host processor to a processor device over an interconnect ([0082 and Figs. 8 and 11]: wherein host (element 510) sends write requests (element 1110) to processor device (element 505) over an interconnect (See element 802 of Fig. 8)) to: write a first binary message to a mailbox register of the processor device ([0082-0083]: wherein host writes a first message to a write mailbox location in the mailbox register (element 870 of Fig. 9 (see [0069-0070] for further details on mailbox register)) (See Figs. 8, 9 and 11)) wherein the mailbox register is in local memory of the processor device (Fig. 8: wherein memory is interpreted to be combination of element 855 and 870, thus mailbox register (element 870 of Fig. 9) is implemented in memory of device (element 505)) and write a value to an executable ready field in the mailbox register corresponding to writing the first binary message to the mailbox register ([0069-0070 and 0082-0083]: wherein a Go bit (See Fig. 10I) in a mailbox register (extended capability register (element 870)) is written to indicate that a first message is written to a write mailbox location in the mailbox register (See Fig. 10L) (See Figs. 9 and 11)) sending one or more first read request, from the host processor to the processor device over the interconnect ([0084 and Figs. 8 and 11]: wherein host (element 510) sends read requests (element 1140) to processor device (element 505) over an interconnect (See element 802 of Fig. 8)) to: identify from a value in an execution complete field of the mailbox register that the processor device completed execution of the first binary message ([0083-0084]: wherein a response ready value of the mailbox register (element 870) is identified to indicate that the processor device (element 505) has completed processing message) and access result data from a results region of the mailbox register ([0083-0084]) wherein the result data comprises a result generated by the processor device from completed execution of the first binary message ([0083-0084]) and using the result data, at the host processor, in association with a second portion executed using the host processor ([0083-0084]: wherein host uses results to execute further messages and/or policies)
Chen does not disclose a first binary executable is written, wherein the first binary executable is cryptographically authenticated by the host processor, nor the first binary executable comprises a portion of a program, a second portion of the program. Chen does disclose transferring messages or instructions from a host to a device, wherein the host has a crypto engine which performs cryptographical tasks in connection with authentication (see [0066]). However, Chen does not explicitly disclose a host authenticating a first message.
Pappachan discloses wherein the first message is cryptographically authenticated by the host processor ([0098-0105]: wherein the host processor provides cryptographic parameters and/or a key to allow a device to authenticate or verify the message sent by the processor (e.g. cryptographically securing a message) (note: limitation is interpreted as discussed above in 112(b) rejection section))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify host processor of the authentication architecture of Chen to cryptographically secure communication as the host processor of Pappachan. It would have been obvious to one of ordinary skill in the art because it would allow a secure communication channel to be set up between a host and a trusted device which would allow secrets to be provisioned to the trusted device (Pappachan [0047]). Thus, mutual authentication could be performed to protect data access between devices (e.g. preventing rogue devices from accessing secret data).
The combination of Chen and Pappachan does not explicitly disclose a first binary executable is written nor the first binary executable comprises a portion of a program, a second portion of the program. Chen does disclose transferring of messages or instructions from a host to a device using a mailbox (see [0069]). However, Chen does not explicitly disclose transferring of executables between a host and a device.
Wallach discloses a first binary executable is written to a particular location. ([0065-0066 and 0083-0084]: wherein an executable is written to a co-processor location (See Figs. 3 and 5)) the first binary executable comprises a portion of a program ([0065-0066 and 0083-0084]) a second portion of the program. ([0065-0066]: wherein a second portion of an executable program is disclosed)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Chen which transfers messages or instructions to a co-processor device to transfer executables as disclosed in Wallach. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (transferring executables to a co-processor as taught in Wallach) for another (transferring generic instructions/messages to a co-processor as taught in Chen) to yield predictable results (transferring executables to a co-processor device using a mailbox register) (MPEP 2143, Example B).
In regards to claim 17, the combination of Chen, Pappachan and Wallach discloses The method of Claim 16 (see rejection of claim 16 above) further comprising: determining from a value in a ready bit of the mailbox register that the processor device is ready to accept another executable at the mailbox register (Chen [0081]: wherein additional ready subfields include values that indicate new message portions are ready to be written such that contents of mailbox are not overwritten (Note: Wallach discloses executables and combination of reference would teach the above limitation)) sending one or more second write requests, from the host processor to the processor device over the interconnect, to write a different second binary executable to the mailbox register of the processor device, wherein the processor device is to execute the second binary executable. (Chen [0081-0085 and Figs. 8 and 11] (Note: Wallach discloses executables and combination of reference would teach the above limitation))
In regards to claim 20, the combination of Chen, Pappachan and Wallach discloses The system of Claim 19 (see rejection of claim 19 above) wherein first executable comprises a first portion of an application (Wallach ([0069-0070 and 0072]: wherein the executable comprises a first portion of an application) the host processor device comprises circuitry to: access the mailbox register over the interconnect to read a result value posted in the mailbox register by the first processor device based on execution of the first executable (Chen [0081-0085 and Figs. 8 and 11] (Note: Wallach discloses executables and combination of references would teach the above limitation)) use the result value in association with execution of a second portion of the application by the host processor device. (Chen [0083-0084]: wherein host uses results to execute further messages and/or policies (Note: Wallach discloses executable portions of an application and thus the combination of references would teach the above limitation))
In regards to claim 21, the combination of Chen, Pappachan and Wallach discloses The system of Claim 20 (see rejection of claim 20 above) wherein the mailbox register comprises: a header to identify the mailbox register in the local memory and identify attributes of the mailbox register (Chen [0070-0076]) a ready value field for the ready value; an execution finished value field for the execution finished value a received executables region to receive executables, wherein the received executables region comprises the particular location (Chen [0069-0070]: wherein the mailbox register comprises a Go bit field for the ready value, a response ready field for the response finished value and a write mailbox field for the messages/instructions (See Figs. 9, 10I, 10H and 10L) |Wallach: Figs. 3 and 5 for memories storing executables)) an executable offset field to identify where executables are written within the received executables region (Chen: See Fig. 9: wherein mailbox register structure comprises offset field including 2Ch to identify write mailbox region where messages are written (note the combination with Wallach discloses the executables and thus the combination discloses the above limitations)) a results region to receive the results value (Chen [0081 and 0083-0084]) and an output offset field to identify where results are written within the results region. (Chen: See Fig. 9: wherein mailbox register structure comprises offset field 30h to identify where results are written within read mailbox (note the combination with Wallach discloses the executables and thus the combination discloses the above limitations))
In regard to claim 23, the combination of Chen, Pappachan and Wallach discloses The system of Claim 19 (see rejection of claim 19 above) wherein the host processor device comprises a host central processing unit (CPU) (Chen [0066 and Fig. 8, element 805]) and the processor circuitry of the processor device comprises a different type of processing unit. (Chen [0067, 0074 and 0083-0084]: wherein the processing circuitry is a hardware accelerator for cryptography/authentication (See Figs. 8 and 11))
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Pappachan, Wallach, and further in view of Thyagaturu, PGPUB No. 2021/0149707.
In regard to claim 14, the combination of Chen, Pappachan and Wallach discloses The apparatus of Claim 1 (see rejection of claim 1 above) wherein the interconnect is compliant with a protocol (Chen [0066]) and the host processor device is to read from and write to the mailbox register based on the protocol. (Chen [0066, 0082 and Figs. 8 and 11]).
The combination of Chen, Pappachan and Wallach does not disclose an interconnect compliant with a Compute Express Link (CXL)-based protocol.
Thyagaturu discloses an interconnect compliant with a Compute Express Link (CXL)-based protocol. ([0013 and 0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the interconnect protocol of Chen to be a Compute Express Link protocol as the interconnect of Thyagaturu. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (an interconnect compliant with a Compute Express Link protocol as taught in Thyagaturu) for another (an interconnect compliant with a PCIe-based protocol as taught in Chen) to yield predictable results (an interconnect compliant with a Compute Express Link based protocol) (MPEP 2143, Example B). Furthermore, a Compute Express Link interconnect enables high speed, low latency and cache coherent connections between devices.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Pappachan, Wallach, and further in view of Ma, PGPUB No. 2014/0082120.
In regard to claim 22, the combination of Chen, Pappachan and Wallach discloses The system of Claim 19 (see rejection of claim 19 above) further comprising the processor device coupled to the host processor device by a interconnect, wherein the processor device comprises a mailbox register to accept executables from the host processor device over the interconnect. (Chen: See Figs. 8 and 11)
The combination of Chen, Pappachan and Wallach does not disclose a second processor device coupled to the host processor device by a second interconnect, wherein the second processor device comprises a second mailbox register to accept executables from the host processor device over the second interconnect. The combination of Chen and Wallach discloses a host device connected to a device by an interconnect, wherein the device comprises a mailbox to receive executables. However, Chen does not disclose the host connected to a second device comprising a mailbox.
Ma discloses a second processor device coupled to the host processor device by a second interconnect, wherein the second processor device comprises a second mailbox to accept message from the host processor device over the second interconnect. ([0018, 0044, and Fig. 1]: wherein any number of peer devices including a second processor peer device, comprising a mailbox, to receive messages from a host device over an interconnect is disclosed)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Chen to include a second processor device coupled to the host processor device as taught in Ma. It would have been obvious to one of ordinary skill in the art because it would have been a duplication of parts (i.e. duplicating a number of interconnects and processor devices) which the courts have deemed obvious (MPEP 2144.04(VI)(B) In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)). Furthermore, increasing a number of processor devices in a system can improve system performance by increasing processing speed and/or providing parallel processing.
Allowable Subject Matter
Claims 10-12 and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all the limitations of the base claim and any intervening claims. (See reasons for allowance regarding prior art considerations in non-final mailed on 3/9/2026).
Response to Arguments
Applicant’s arguments, see pages 1-2 of remarks filed on 6/9/2026 with respect to the rejection(s) of claim(s) 1, 16 and 19 under 35 USC 103 in view of Chen and Wallach have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 103 in view of Chen, Pappachan and Wallach. In addition, claims 1 and 16 are now rejected under 35 USC 112(b).
Claims 2-15, 17-18 and 21-26 are argued at least based on dependency and therefore remain rejected at least based upon their dependencies upon rejected claims.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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