Prosecution Insights
Last updated: May 04, 2026
Application No. 17/992,010

REDISTRIBUTION LAYERS IN A DIELECTRIC CAVITY TO ENABLE AN EMBEDDED COMPONENT

Non-Final OA §102§103
Filed
Nov 22, 2022
Examiner
ZARNEKE, DAVID A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
568 granted / 803 resolved
+2.7% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
33 currently pending
Career history
836
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
59.3%
+19.3% vs TC avg
§102
24.5%
-15.5% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 803 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions Applicant's election with traverse of Group I and Species 1a, 2a, 3a, 4a, and 5a, corresponding to claims 1-6, 11, 13, 14, and 25, in the reply filed on 2/23/26 is acknowledged. The traversal is on the ground(s) that the reasons for restriction are conclusory and do not adequately explain the restriction. Note that Species 2 is removed and therefore claims 7-9 are rejoined. The traversal is not found persuasive because: Species 1 clearly requires differently shaped and patentably distinct RDL’s in the cavity. Species 3 has different method steps, specifically at steps 1004 vs 1104, and 1012 vs 1112. Species 4 are clearly two different, and patentably distinct components. Species 5 are clearly two different, and patentably distinct shapes. The requirement is still deemed proper and is therefore made FINAL. As a result of the removal of Species 2, the examined claims are 1-9, 11, 13, 14, and 25. Rejection over Pietambaram et al., US 2022/189880 Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Pietambaram et al., US 2022/189880. The applied reference has a common assignee and one common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim 1, Pietambaram (see abbreviated & marked up figure 1 below) teaches an apparatus, comprising: a glass layer 114 having an upper surface and a lower surface, the glass layer comprising a plurality of through-glass vias (TGVs) 118; a first dielectric layer 112-1 comprising a first redistribution layer (RDL) 116 located adjacent to the upper surface; a second dielectric layer 112-2 comprising a second RDL 116 located adjacent to the lower surface; at least one electrically communicative path 1 from the first dielectric layer 112-1 through a TGV 118 to the second dielectric layer 112-2; a conductive layer 2 located on a portion of the first dielectric layer 112-1; and a third RDL 106 located on the conductive layer 2. PNG media_image1.png 378 652 media_image1.png Greyscale With respect to claim 6, wherein (paragraph 0021 at top of 2nd column teaches 350-550 microns) the glass layer 114 has a thickness in a range of about 20 microns to about 2 millimeter. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2-5, 7-9, and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram et al., US 2022/189880, as applied to claim 1 above, and further in view of Lee, US 9,406,658. As to claim 2, Pietambaram, which teaches depositing the dielectric around the embedded component (figures 7-9), fails to teach a cavity wall located external to a periphery of the conductive layer, and a third dielectric layer located in the cavity wall. Lee teaches both depositing the dielectric around the embedded component (figures 6E-G), as taught in Pietambaram, and a cavity wall located external to a periphery of the conductive layer, and a third dielectric layer located in the cavity wall (figure 7 & column 9, lines 1-22), as claimed. It would have been obvious to one of ordinary skill in the art at the time of the invention to use the cavity of Lee in place of the surrounded component in the invention of Pietambaram because Lee teaches both are known equivalent ways to achieve the same result. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). In re claim 3, though Pietambaram fails to teach the conductive layer has a thickness of about 5 microns, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the thickness through routine experimentation (MPEP 2144.05). Concerning claim 4, though Pietambaram fails to teach the conductive layer, the first RDL, the second RDL, and the third RDL comprise copper, it would have been obvious to one of ordinary skill in the art at the time of the invention to use copper for these maerials in the invention of Pietambaram because copper is a conventionally known and used material for these layers. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Pertaining to claim 5, though Pietambaram fails to teach the glass layer comprises silicon and oxygen, it would have been obvious to one of ordinary skill in the art at the time of the invention to use t silicon and oxygen containing glass in the invention of Pietambaram because they are conventionally known and used glass maerials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). In claim 7, Lee (figure 7) teaches an embedded component 202 located on the conductive layer 204 and attached to the third RDL 250/251/253/254. Regarding claim 8, though Lee fails to teach the embedded component is attached to the third RDL via solder, and further comprising underfill between the embedded component and a cavity floor, it would have been obvious to one of ordinary skill in the art at the time of the invention to replace the directly connected embedded component in the invention of Lee with a solder connection because they are conventionally known and used equivalents. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). With respect to claim 9, though Pietambaram and Lee fail to teach the embedded component is a photonic integrated circuit (PIC), it would have been obvious to one of ordinary skill in the art at the time of the invention to use a PIC in the invention of Pietambaram because a PIC is a conventionally known and used embedded component. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). As to claim 11, though Pietambaram fails to teach the third RDL located on the conductive layer is characterized by rounded walls, it would have been obvious to one of ordinary skill in the art at the time of the invention to use rounded sidewalls in the invention of Pietambaram because rounded sidewalls are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). In re claim 13, though Pietambaram and Lee fail to teach an epoxy layer between the glass layer and the second dielectric layer, it would have been obvious to one of ordinary skill in the art at the time of the invention to use an epoxy layer in the invention of Pietambaram because an epoxy layer is conventionally known and used to improve adhesion. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Concerning claim 14, though Pietambaram and Lee fail to teach an epoxy layer adjacent to the glass layer and located on the second dielectric layer, it would have been obvious to one of ordinary skill in the art at the time of the invention to use an epoxy layer in the invention of Pietambaram because an epoxy layer is conventionally known and used to improve adhesion. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram et al., US 2022/189880, as applied to claim 1 above, and further in view of Lee, US 9,406,658. Pertaining to claim 25, Pietambaram (see abbreviated & marked up figure 3 below) teaches a device, comprising: an integrated circuit (IC) die 102; and a substrate including a glass core 114, the substrate comprising: a conductive layer 3 overlaid on the glass core 114; a dielectric 112-1 having a redistribution layer (RDL) 116 therein; the redistribution layer 116 adjacent to the conductive layer 3; an embedded component 104 comprising a first side, a second side, and at least one electrically conductive path 4 from the first side to the second side, the embedded component 104 attached on the first side to the RDL 116, and in electrical communication with the IC die 102 on the second side; and a printed circuit board 122-2 attached to the substrate 114. PNG media_image2.png 378 652 media_image2.png Greyscale Pietambaram, which teaches a surrounded embedded component, fails to teach the embedded component in a dielectric cavity. Lee teaches both depositing the dielectric around the embedded component (figures 6E-G), as taught in Pietambaram, and a cavity wall located external to a periphery of the conductive layer, and a third dielectric layer located in the cavity wall (figure 7 & column 9, lines 1-22), as claimed. It would have been obvious to one of ordinary skill in the art at the time of the invention to use the cavity of Lee in place of the surrounded component in the invention of Pietambaram because Lee teaches both are known equivalent ways to achieve the same result. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). Rejection over Terui et al., US 2016/0020164 Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4, 6 and 7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Terui et al., US 2016/0020164. In claim 1, Terui (see marked up figure 1 below) teaches an apparatus, comprising: a glass (paragraph 0045) layer 11 having an upper surface and a lower surface, the glass layer comprising a plurality of through-glass vias (TGVs) 2; a first dielectric layer (upper 15) comprising a first redistribution layer (RDL) (upper 16) located adjacent to the upper surface; a second dielectric layer (lower 15) comprising a second RDL (lower 16) located adjacent to the lower surface; at least one electrically communicative path 1 from the first dielectric layer (upper 15) through a TGV 2 to the second dielectric layer lower 15); a conductive layer 31A located on a portion of the first dielectric layer (upper 15); and a third RDL 21/29F/23A/23B/25A located on the conductive layer 31A. PNG media_image3.png 574 868 media_image3.png Greyscale Regarding claim 4, Terui teaches wherein the conductive layer 31A (paragraph 0032), the first RDL (upper 16), the second RDL (lower 16), and the third RDL 21/29F/23A/23B/25A comprise copper (paragraph 0029). With respect to claim 6, Terui (paragraph 0029 teaches 700 um) the glass layer has a thickness in a range of about 20 microns to about 2 millimeter. As to claim 7, Terui teaches an embedded component 80 located on the conductive layer 31A and attached to the third RDL 21/29F/23A/23B/25A. Claim(s) 2, 3, 5-9, 11, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Terui et al., US 2016/0020164, as applied to claim 1 above, and further in view of Lee et al., US 9,406,658. In re claim 2, Terui fails to teach a cavity wall located external to a periphery of the conductive layer, and a third dielectric layer located in the cavity wall. Lee (figure 8) teaches a cavity wall 706 located external to a periphery of the conductive layer 840, and a third dielectric layer (unlabeled dielectric that fills cavity) located in the cavity wall 706. It would have been obvious to one of ordinary skill in the art at the time of the invention to use the cavity of Lee in the invention of Terui because it is a conventionally known and used equivalent way of embedding a component. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). Concerning claim 3, though Terui fails to teach the conductive layer has a thickness of about 5 microns, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the thickness through routine experimentation (MPEP 2144.05). Pertaining to claim 5, though Terui fails to teach the glass layer 11 comprises silicon and oxygen, it would have been obvious to one of ordinary skill in the art at the time of the invention to use silicon and oxygen glass in the invention of Terui because silicon and oxygen glass is a conventionally known and used glass. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). In claim 8, though Terui fails to teach the embedded component is attached to the third RDL via solder, and further comprising underfill between the embedded component and a cavity floor, it would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder and an underfill in the invention of Terui because they are both conventionally known and used equivalents. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). Regarding claim 9, though Terui fails to teach the embedded component is a photonic integrated circuit (PIC), it would have been obvious to one of ordinary skill in the art at the time of the invention to use a PIC in the invention of Terui because a PIC is a conventionally known and used embedded component. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). With respect to claim 11, though Terui fails to teach the third RDL located on the conductive layer is characterized by rounded walls, it would have been obvious to one of ordinary skill in the art at the time of the invention to use rounded sidewalls in the invention of Terui because rounded sidewalls are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). As to claim 13, though Terui fails to teach an epoxy layer between the glass layer and the second dielectric layer, it would have been obvious to one of ordinary skill in the art at the time of the invention to use an epoxy layer in the invention of Terui because an epoxy layer is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). In re claim 14, though Terui fails to teach an epoxy layer adjacent to the glass layer and located on the second dielectric layer, it would have been obvious to one of ordinary skill in the art at the time of the invention to use an epoxy layer in the invention of Terui because an epoxy layer is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Terui et al., US 2016/0020164, in view of Lee et a., US 9,406,658, and Pietambaram et al., US 2022/18988. Concerning claim 25. Terui (figure 1) teaches a device, comprising: an integrated circuit (IC) die 90/91; and a substrate 112-1/118/12-2 including a glass (paragraph 0045) core 11, the substrate comprising: a conductive layer 12 overlaid on the glass core 11; a dielectric cavity 30 having a redistribution layer (RDL) 21/29F/23A/23B/25A therein through ; the redistribution layer 21/29F/23A/23B/25A adjacent to the conductive layer 31A; and an embedded component 80 comprising a first side, a second side. Terui (figure 1) teaches the embedded component 80 located within the dielectric cavity 30, but fails to teach the embedded component has at least one electrically conductive path from the first side to the second side, attached on the first side to the RDL and in electrical communication with the IC die on the second side; and a printed circuit board attached to the substrate. Pietambaram (figure 1) teaches the embedded component 104 has at least one electrically conductive path (through vias) from the first side to the second side, attached on the first side to the RDL 116, and in electrical communication with the IC die 102 on the second side; and a printed circuit board 126 attached to the substrate 112-1/118/12-2. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 4/16/26
Read full office action

Prosecution Timeline

Nov 22, 2022
Application Filed
Jun 06, 2023
Response after Non-Final Action
Apr 16, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
81%
With Interview (+10.7%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 803 resolved cases by this examiner. Grant probability derived from career allowance rate.

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