DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I directing to claims 1-5, 7-11 and 13-19 in the reply filed on March 19, 2026 is acknowledged. The traversal is on the ground(s) that “there would be no excess examination burden to fully examine all claims.”. This is not found persuasive because the inventions require a different field of search (e.g., searching different CPC groups/subgroups or electronic resources, or employing different search strategies or search queries). They require different keyword searches. Furthermore, a search for the first contact contacts the first portion of the sub-fin from a backside of the sub-fin, and the second contact contacts the second portion of the sub-fin from the backside of the sub-fin is not likely to find art pertinent to the first contact extends within the first portion of the sub-fin and is in contact with the first diffusion region, and wherein the second contact extends within the second portion of the sub-fin and is in contact with a second diffusion region of a second device that is laterally adjacent to the first device.
The requirement is still deemed proper and is therefore made FINAL.
Claims 6, 12 and 20, are withdrawn. Currently claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/2022 and 04/15/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION. - The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 line 2-4 recited “the first diffusion region and the second diffusion region” without mentioning “a first diffusion region and a second diffusion region” earlier in the claim. There is insufficient antecedent basis for these limitations in the claim. Claim 5 is dependent on claim 2 and claim 2 does not recite a first diffusion region and a second diffusion region. Therefore, it is unclear and the scope of the claim is unclear. For examination purposes, claim 5 will be interpreted as dependent on claim 4.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8-10, 13-16 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by THOMSON, Nicholas (US 20200403007 A1) “THOMSON et al.”.
Regarding Independent Claim 1, THOMSON et al. Figs. 1-11 discloses an integrated circuit structure (“ICs with one or more transistor devices having a plurality of diodes” ¶ [0133]) comprising:
a sub-fin (“fin structure/segments, the region(s) (or the portion(s)) of the N-type/P-type fin regions 116 and 118 below the bottom surfaces of the N-type epi portions 126, P-type epi portions 128, and the gate electrodes 114 may be referred to as the subfin region(s) of the diode device 100” ¶ [0050]) having at least (i) a first portion that is doped with a first type of dopant (“the N-type fin region 116 may include any N-type (or N+) dopants/impurities known in the art, such as phosphorus, arsenic, antimony, bismuth, etc.” ¶ [0049]), and (ii) a second portion that is doped with a second type of dopant (“P-type fin region 118 may include any P-type (or P+) dopants/impurities known in the art, such as boron, BF2, aluminum, gallium, indium, etc.,” ¶ [0049]), with a PN junction between the first and second portions of the sub-fin (“ the resulting structure may implement the P/N junction of the diode device 100 that may be formed between either the P-type fin region 118 or the N-type fin region 116, or formed at the interface of the P-type fin region 118 and the N-type fin region 116” ¶ [0056]),
wherein the first type of dopant is one of a p-type or an n-type dopant (“the N-type fin region 116 may include any N-type (or N+) dopants/impurities known in the art, such as phosphorus, arsenic, antimony, bismuth, etc.” ¶ [0049]), and wherein the second type of dopant is the other of the p-type (“P-type fin region 118 may include any P-type (or P+) dopants/impurities known in the art, such as boron, BF2, aluminum, gallium, indium, etc.,” ¶ [0049]) or the n-type dopant; and
a first contact and a second contact (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106.” ¶ [0060]) comprising conductive material (“the backside vias 110 may be formed of a conductive material, such as Al, Cu, tungsten, metal alloys (e.g., an alloy of Al and Cu), and/or any other suitable electrical contact forming conductive material, to provide an electrical contact for the cathode and/or anode regions 104 and 106. In addition, each of the backside vias 110 may act as a conductive interconnect used to couple a first conductor, such as the cathode region 104 and/or the anode region 106” ¶ [0061]), the first contact and the second contact respectively in contact with the first portion and the second portion of the sub- fin (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106. The backside vias 110 may be positioned adjacent to the outer edges of the N-type/P-type fin regions 116 and 118” ¶ [0060]).
Regarding Claim 2, THOMSON et al. discloses the limitations of claim 1. THOMSON et al. Figs. 1-11 further discloses, further comprising: one or more devices (“the diode device 100 may be a diode unit implemented from a transistor device (or a transistor block/array) or part of a transistor device” ¶ [0044]) above the sub-fin, wherein at least one device of the one or more devices comprises a diffusion region (“N-type epi portions 126, P-type epi portions 128” ¶ [0050]), and a body of semiconductor material extending laterally from the diffusion region (“In one embodiment, the N-type/P-type epi portions 126 and 128 may be formed of a semiconductor material(s) which is/are the same as the semiconductor material(s) that is/are used to form the respective N-type/P-type fin regions 116 and 118. .. For example, the semiconductor material of the epi portions (e.g., the N-type/P-type epi portions 126 and 128) may include silicon Germanium (SiGe) and/or silicon carbon (SiC).” ¶ [0054]), the body of semiconductor material above the sub-fin (“fin structure/segments, the region(s) (or the portion(s)) of the N-type/P-type fin regions 116 and 118 below the bottom surfaces of the N-type epi portions 126, P-type epi portions 128, and the gate electrodes 114 may be referred to as the subfin region(s) of the diode device 100” ¶ [0050]).
Regarding Claim 3, THOMSON et al. discloses the limitations of claim 2. THOMSON et al. Figs. 1-11 further discloses, wherein the at least one device of the one or more devices comprises a gate structure at least in part wrapping around the body, the gate structure comprising a gate electrode (“gate electrodes 114” ¶ [0052]), and a gate dielectric between the gate electrode and the body (“a gate dielectric layer may be further disposed (or formed) between the gate electrodes 114 and the N-type/P-type fin regions 116 and 118” ¶ [0052]).
Regarding Claim 8, THOMSON et al. discloses the limitations of claim 2. THOMSON et al. Figs. 1-11 further discloses, wherein the body comprises one of a nanoribbon, a nanosheet, a nanowire, a fin (“FinFET diode devices” ¶ [0039]), or is arranged in a forksheet device configuration.
Regarding Claim 9, THOMSON et al. discloses the limitations of claim 2. THOMSON et al. Figs. 1-11 further discloses, wherein: the at least one device is a first device of the one or more devices, the diffusion region is a first diffusion region (“N-type epi portions 126,” ¶ [0050]), the body is a first body (“In one embodiment, the N-type/P-type epi portions 126 and 128 may be formed of a semiconductor material(s) which is/are the same as the semiconductor material(s) that is/are used to form the respective N-type/P-type fin regions 116 and 118. .. For example, the semiconductor material of the epi portions (e.g., the N-type/P-type epi portions 126 and 128) may include silicon Germanium (SiGe) and/or silicon carbon (SiC).” ¶ [0054]); and the one or more devices comprises a second device laterally adjacent to the first device, the second device comprising a second diffusion region (“P-type epi portions 128” ¶ [0050]), and a second body of semiconductor material extending from the second diffusion region, the second body of semiconductor material above the sub-fin (“In one embodiment, the N-type/P-type epi portions 126 and 128 may be formed of a semiconductor material(s) which is/are the same as the semiconductor material(s) that is/are used to form the respective N-type/P-type fin regions 116 and 118. .. For example, the semiconductor material of the epi portions (e.g., the N-type/P-type epi portions 126 and 128) may include silicon Germanium (SiGe) and/or silicon carbon (SiC).” ¶ [0054]).
Regarding Claim 10, THOMSON et al. discloses the limitations of claim 9. THOMSON et al. Figs. 1-11 further discloses, wherein the first diffusion region and the first body are above the first portion of the sub-fin (Fig. 1 shows the first diffusion region and the first body are above the first portion of the sub-fin), and the second diffusion region and the second body are above the second portion of the sub-fin (Fig. 1 shows the second diffusion region and the second body are above the second portion of the sub-fin).
Regarding Claim 13, THOMSON et al. discloses the limitations of claim 1. THOMSON et al. Figs. 1-11 further discloses, wherein the first contact contacts the first portion of the sub-fin from a backside of the sub-fin (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106. The backside vias 110 may be positioned adjacent to the outer edges of the N-type/P-type fin regions 116 and 118.” ¶ [0060]), and the second contact contacts the second portion of the sub-fin from the backside of the sub-fin (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106. The backside vias 110 may be positioned adjacent to the outer edges of the N-type/P-type fin regions 116 and 118.” ¶ [0060]), and wherein one or more devices are on a frontside of the sub-fin (“FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned” [0030]).
Regarding Claim 14, THOMSON et al. discloses the limitations of claim 1. THOMSON et al. Figs. 1-13 further discloses, further comprising: a backside interconnect structure below the sub-fin, the backside interconnect structure comprising one or more interconnect layers (“each of the backside vias 110 may act as a conductive interconnect used to couple a first conductor, such as the cathode region 104 and/or the anode region 106, to a second conductor, such as the conductive contacts 112, where the first and second conductors may be disposed on different interconnect levels, according to an embodiment.” ¶ [0061]), each interconnect layer comprising dielectric material and one or more interconnect features within the dielectric material (“multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias” ¶ [0139]), wherein the backside interconnect structure is to transmit signal and/or power to and/or from the first contact and/or the second contact (“Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers)” ¶ [0139]).
Regarding Claim 15, THOMSON et al. discloses the limitations of claim 1. THOMSON et al. Figs. 1-13 further discloses, wherein the sub-fin and the first and second contacts are a part of a diode structure (“a diode device 100” ¶ [0041]), and wherein the integrated circuit structure further comprises: a logic transistor laterally adjacent to the diode structure and above a dielectric material (“a FinFET diode” ¶ []0051]; “a gate dielectric layer may be further disposed (or formed) between the gate electrodes 114 and the N-type/P-type fin regions 116 and 118” ¶ [0052]), such that an imaginary horizontal line passes through the first and second portions of the sub-fin, the PN junction, and the dielectric material below the logic transistor (Fig. 1 shows an imaginary horizontal line passes through the first and second portions of the sub-fin, the PN junction, and the dielectric material below the logic transistor).
Regarding Independent Claim 16, THOMSON et al. Figs. 1-11 discloses a diode structure comprising:
a sub-fin (“fin structure/segments, the region(s) (or the portion(s)) of the N-type/P-type fin regions 116 and 118 below the bottom surfaces of the N-type epi portions 126, P-type epi portions 128, and the gate electrodes 114 may be referred to as the subfin region(s) of the diode device 100” ¶ [0050]) having (i) a first portion that is an anode region (“an anode region” ¶ [0041]), and (ii) a second portion that is a cathode region (“a cathode region” ¶ [0041]), with a PN junction (“the resulting structure may implement the P/N junction of the diode device 100 that may be formed between either the P-type fin region 118 or the N-type fin region 116, or formed at the interface of the P-type fin region 118 and the N-type fin region 116” ¶ [0056]) between the first and second portions (Fig. 1 shows the PN junction between the first and second portions); and a first backside contact that is in contact with the first portion of the sub-fin (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106.” ¶ [0060]), and a second backside contact that is in contact with the second portion of the sub-fin (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106.” ¶ [0060]).
Regarding Independent Claim 19, THOMSON et al. Figs. 1-11 discloses an integrated circuit structure comprising: a sub-fin (“fin structure/segments, the region(s) (or the portion(s)) of the N-type/P-type fin regions 116 and 118 below the bottom surfaces of the N-type epi portions 126, P-type epi portions 128, and the gate electrodes 114 may be referred to as the subfin region(s) of the diode device 100” ¶ [0050]) having a first portion (“the N-type fin region 116 may include any N-type (or N+) dopants/impurities known in the art, such as phosphorus, arsenic, antimony, bismuth, etc.” ¶ [0049]) and a second portion (“P-type fin region 118 may include any P-type (or P+) dopants/impurities known in the art, such as boron, BF2, aluminum, gallium, indium, etc.,” ¶ [0049]), with a PN junction at an interface between the first and second portions (“the resulting structure may implement the P/N junction of the diode device 100 that may be formed between either the P-type fin region 118 or the N-type fin region 116, or formed at the interface of the P-type fin region 118 and the N-type fin region 116” ¶ [0056]);
a first diffusion region (“N-type epi portions 126” ¶ [0050]) extending upward from the first portion of the sub-fin, and a second diffusion region (“P-type epi portions 128” ¶ [0050]) extending upward from the second portion of the sub-fin;
a first body of semiconductor material extending laterally from the first diffusion region, and a second body of semiconductor material extending laterally from the second diffusion region (“In one embodiment, the N-type/P-type epi portions 126 and 128 may be formed of a semiconductor material(s) which is/are the same as the semiconductor material(s) that is/are used to form the respective N-type/P-type fin regions 116 and 118. .. For example, the semiconductor material of the epi portions (e.g., the N-type/P-type epi portions 126 and 128) may include silicon Germanium (SiGe) and/or silicon carbon (SiC).” ¶ [0054]); and
a first conductive contact in contact with the first portion of the sub-fin (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106.” ¶ [0060]), and a second conductive contact in contact with the second portion of the sub-fin (“the backside vias 110 may be disposed vertically on the cathode region 104 and the anode region 106.” ¶ [0060]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over THOMSON, Nicholas (US 20200403007 A1) “THOMSON et al.” in view of FULFORD, H. Jim (US 20210104523 A1) “FULFORD et al.”.
Regarding Claim 4, THOMSON et al. discloses the limitations of claim 2. However, THOMSON et al. does not disclose, wherein: the at least one device is a first device of the one or more devices, the diffusion region is a first diffusion region, the body is a first body; and the one or more devices comprises a second device stacked above the first device, the second device comprising a second diffusion region, and a second body of semiconductor material extending from the second diffusion region, the second body of semiconductor material above the sub-fin.
In the similar field of endeavor of transistor devices, FULFORD et al. Fig 6 discloses the at least one device is a first device of the one or more devices, the diffusion region is a first diffusion region (“a plurality of bottom source/drain (S/D) regions 130-138” ¶ [0053]), the body is a first body; and the one or more devices comprises a second device stacked above the first device (“transistors are stacked on top of each other” ¶ [0002]), the second device comprising a second diffusion region (“a plurality of top source/drain (S/D) regions 126, 128, and 140-144” ¶ [0053]), and a second body of semiconductor material extending from the second diffusion region, the second body of semiconductor material above the sub-fin.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the diode structure of THOMSON et al. using the stacked transistor construction in order to obtain a better optimization of CFET's performance (FULFORD et al., ¶ [0024]).
Regarding Claim 5, THOMSON et al. discloses the limitations of claim 4. However, THOMSON et al. does not disclose, further comprising at least one of: an isolation structure comprising dielectric material between the first diffusion region and the second diffusion region; or a conductive via structure between the first diffusion region and the second diffusion region.
In the similar field of endeavor of transistor devices, FULFORD et al. Fig 6 discloses an isolation structure comprising dielectric material between the first diffusion region and the second diffusion region (“a plurality of middle oxide layers 150a-150e can be positioned between the bottom and top S/D regions to separate the bottom and top S/D regions from each other.” ¶ [0055]); or a conductive via structure between the first diffusion region and the second diffusion region.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the diode structure of THOMSON et al. using the stacked transistor construction with isolation between top and bottom S/D regions in order to separate the bottom and top S/D regions from each other (FULFORD et al., ¶ [0055]).
Claim 7, 11 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over THOMSON, Nicholas (US 20200403007 A1) “THOMSON et al.” in view of Yang, Szu-Chi (US 20210098305 A1) “Yang et al.”.
Regarding Claim 7, THOMSON et al. discloses the limitations of claim 2. However, THOMSON et al. does not disclose, further comprising: a structure comprising dielectric material above, and in contact with the PN junction of the sub-fin, wherein the body of semiconductor material extends laterally from the diffusion region to the structure comprising dielectric material.
In the similar field of endeavor of IC structures including diodes Yang et al. Figs. 1-12 discloses a structure comprising dielectric material above, and in contact with the PN junction of the sub-fin (“an isolation feature 220 between the first fin 216A and the second fin 218A. In some embodiments represented in FIG. 5, a dielectric material 219 is first blanketly deposited over the workpiece 200 to fill space between the p-type fins 216 and the n-type fins 218. The dielectric material 219 may include silicon oxide, silicon oxynitride, other suitable isolation material, or combinations thereof” ¶ [0018]), wherein the body of semiconductor material extends laterally from the diffusion region to the structure comprising dielectric material (“the first semiconductor material 206 and the second semiconductor material 204 in the first fin 216A and the second semiconductor material 204 in the second fin 218A are exposed and rise above the isolation structure 220” ¶ [0018]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the diode structure of THOMSON et al. with an isolation dielectric layer of Yang et al. in order to implement of isolation structure between the fins (Yang et al. ¶ [0018]).
Regarding Claim 11, THOMSON et al. discloses the limitations of claim 1. However, THOMSON et al. does not disclose, further comprising: a structure comprising dielectric material above, and in contact with the PN junction of the sub-fin.
In the similar field of endeavor of IC structures including diodes Yang et al. Figs. 1-12 discloses, a structure comprising dielectric material above (“an isolation feature 220 between the first fin 216A and the second fin 218A. In some embodiments represented in FIG. 5, a dielectric material 219 is first blanketly deposited over the workpiece 200 to fill space between the p-type fins 216 and the n-type fins 218. The dielectric material 219 may include silicon oxide, silicon oxynitride, other suitable isolation material, or combinations thereof” ¶ [0018]), and in contact with the PN junction of the sub-fin (Fig. 12 shows 220 in contact with the PN junction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the diode structure of THOMSON et al. with an isolation dielectric layer of Yang et al. in order to implement of isolation structure between the fins (Yang et al. ¶ [0018]).
Regarding Claim 17, THOMSON et al. discloses the limitations of claim 16. THOMSON et al. Figs. 1-13 further discloses, wherein: a first diffusion region (“N-type epi portions 126” ¶ [0050]), above the first portion of the sub-fin; a second diffusion region (“P-type epi portions 128” ¶ [0050]) above the second portion of the sub-fin;
However, THOMSON et al. does not disclose, a structure comprising dielectric material above and in contact with the PN junction.
In the similar field of endeavor of IC structures including diodes Yang et al. Figs. 1-12 discloses, a structure comprising dielectric material above (“an isolation feature 220 between the first fin 216A and the second fin 218A. In some embodiments represented in FIG. 5, a dielectric material 219 is first blanketly deposited over the workpiece 200 to fill space between the p-type fins 216 and the n-type fins 218. The dielectric material 219 may include silicon oxide, silicon oxynitride, other suitable isolation material, or combinations thereof” ¶ [0018]), and in contact with the PN junction of the sub-fin (Fig. 12 shows 220 in contact with the PN juction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the diode structure of THOMSON et al. with an isolation dielectric layer of Yang et al. in order to implement of isolation structure between the fins (Yang et al. ¶ [0018]).
Regarding Claim 18, THOMSON et al. as modified by Yang et al. discloses the limitations of claim 16. However, THOMSON et al. does not disclose, wherein: a first body of semiconductor material extending laterally from the first diffusion region to the structure comprising dielectric material; and a second body of semiconductor material extending laterally from the second diffusion region to the structure comprising dielectric material.
In the similar field of endeavor of IC structures including diodes Yang et al. Figs. 1-12 discloses, a first body of semiconductor material extending laterally from the first diffusion region to the structure comprising dielectric material; and a second body of semiconductor material extending laterally from the second diffusion region to the structure comprising dielectric material (“the first semiconductor material 206 and the second semiconductor material 204 in the first fin 216A and the second semiconductor material 204 in the second fin 218A are exposed and rise above the isolation structure 220” ¶ [0018]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the diode structure of THOMSON et al. with an isolation dielectric layer of Yang et al. in order to implement of isolation structure between the fins (Yang et al. ¶ [0018]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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