DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/2022 and 4/19/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Schutten et al. (US Publication No. 2018/0123476) in view of Tamada et al. (US Publication No. 2023/0197668).
Regarding claim 1, Schutten discloses a power semiconductor module (Figure 3), comprising:
a substrate (14) comprising an electrically insulative material (16), a first metallization layer (20) at a frontside of the electrically insulative material (16), and a second metallization layer (18) at a backside of the electrically insulative material (16)
a first power semiconductor die (22) of a power electronics circuit
wherein the first power semiconductor die (22) is attached to the first metallization layer (20) at the frontside of the electrically insulative material (16), or is embedded in the electrically insulative material
wherein the electrical conductor (12) enables a point of electrical contact (ground) for the second metallization layer (18) at the frontside of the electrically insulative material (16) (paragraph 23)
Schutten does not disclose an opening in the electrically insulative material that exposes part of the second metallization layer from the electrically insulative material and an electrical conductor disposed in the opening and connected to the part of the second metallization layer exposed by the opening. However, Tamada discloses an opening (66) in an insulative material (31) and an electrical conductor (66) disposed in the opening and connected to part of the second metallization layer (35). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Schutten to include a conductor from the die to the second metallization layer, as taught by Tamada, since it can help reduce or prevent oscillation of gate voltage (paragraphs 6-8).
Regarding claim 2, Tamada discloses the electrical conductor comprises an electrically conductive via (66) that extends through the electrically insulative material (31) and connects the part of the second metallization layer (35) exposed by the opening to a first island (25i) of the first metallization layer (53). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Schutten in view of Tamada.
Regarding claim 3, Schutten discloses the first power semiconductor die (23) is attached to a second island of the first metallization layer (20), wherein the power electronics circuit is a power converter that includes a half bridge, wherein the first power semiconductor die (23) forms a switch of the half bridge, wherein the second island of the first metallization layer forms a positive DC terminal or an AC terminal for the half bridge, and wherein a third island (20) of the first metallization layer forms a negative DC terminal for the half bridge (paragraph 24; Figure 3).
Regarding claim 4, Schutten discloses a Y-capacitor (52) connected between the first island and the third island of the first metallization layer (20).
Regarding claim 5, Schutten discloses a second power semiconductor die (24) of the power electronics circuit, the second power semiconductor die attached to a fourth island of the first metallization layer (20), wherein the first power semiconductor die (23) forms a high-side switch of the half bridge, wherein the second power semiconductor die (24) forms a low-side switch of the half bridge (paragraphs 27-30), wherein the second island of the first metallization layer forms the positive DC terminal for the half bridge, wherein the fourth island of the first metallization layer (20) forms the AC terminal for the half bridge (paragraph 24).
Regarding claim 6, Schutten discloses a Y-capacitor (52) connected between the first island and the third island of the first metallization layer (20).
Regarding claim 7, Schutten discloses a second Y-capacitor connected between the first island and the second island of the first metallization layer (paragraph 18).
Regarding claim 8, Schutten discloses a Y-capacitor (52) connected between the first island of the first metallization layer (20) and a second island of the first metallization layer, wherein the second island of the first metallization layer (20) is at a different potential than the first island (paragraph 24; Figure 3).
Regarding claim 9, Schutten discloses a pin (38) attached to the first island of the first metallization layer (20), wherein the pin (38) is configured for external attachment of one or more Y-capacitors (52) (paragraph 29).
Regarding claim 10, Tamada discloses the opening (68) in the electrically insulative material (31) is aligned with a gap (between 67 and 53) in the first metallization layer (53), and wherein the electrical conductor (68) comprises a metal structure that fills the opening in the electrically insulative material (16) and extends onto the frontside of the electrically insulative material in a region of the gap such that the metal structure does not contact the first metallization layer (Figure 20; paragraph 188). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Schutten in view of Tamada.
Regarding claim 11, Schutten discloses a pin (38) attached to a side of the metal structure that faces away from the electrically insulative material (16), wherein the pin (38) is configured for external attachment of one or more Y-capacitors (52) (paragraph 29).
Regarding claim 12, Schutten discloses a Y-capacitor (52) connected between the metal structure and an island of the first metallization layer (20), wherein the metal structure is at a different potential than the island of the first metallization layer (paragraph 24).
Regarding claim 13, Tamada discloses the opening (68) in the electrically insulative material (31) is aligned with a gap (between 67 and 53) in the first metallization layer (20), and wherein the electrical conductor (68) comprises a pin (62) that penetrates the second metallization layer (57) through the opening in the electrically insulative material (31) and juts out beyond the first metallization layer (20) in a region of the gap such that the pin does not contact the first metallization layer, and wherein the pin (62) is configured for external attachment of one or more Y-capacitors (Figure 27). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Schutten in view of Tamada.
Regarding claim 14, Schutten discloses the substrate is a direct bond copper (DBC) substrate, an active metal brazed (AMB) substrate, or an insulated metal (IMS) substrate, and wherein the first power semiconductor die (23) is attached to the first metallization layer (20) at the frontside of the electrically insulative material (16) (paragraph 20).
Regarding claim 15, Schutten discloses the substrate is a laminate (14), and wherein the first power semiconductor (23) is embedded in the electrically insulative material (34) of the laminate (14).
Regarding claim 16, Schutten discloses a power semiconductor module, comprising:
a substrate comprising an electrically insulative material (16), a first metallization layer (20) at a frontside of the electrically insulative material (16), and a second metallization layer (18) at a backside of the electrically insulative material (16)
a first power semiconductor die (23) of a half bridge
a second power semiconductor die (24) of the half bridge
wherein the first power semiconductor die (23) is attached to a second island of the first metallization layer (20) that forms a positive DC terminal for the half bridge, wherein a third island of the first metallization layer (20) forms a negative DC terminal for the half bridge, wherein the second power semiconductor die (24) is attached to a fourth island of the first metallization layer that forms the AC terminal for the half bridge (paragraph 24)
Schutten does not disclose an opening in the electrically insulative material that exposes part of the second metallization layer from the electrically insulative material and an electrical conductor disposed in the opening and connected to the part of the second metallization layer exposed by the opening, wherein the electrical conductor comprises an electrically conductive via that extends through the electrically insulative material and connects the part of the second metallization layer exposed by the opening to a first island of the first metallization layer. However, Tamada discloses an opening (66) in an insulative material (31) and an electrical conductor (66) disposed in the opening and connected to part of the second metallization layer (35), wherein the electrical conductor comprises an electrically conductive via (68) that extends through the electrically insulative material (31) and connects the part of the second metallization layer (35) exposed by the opening to a first island (15n) of the first metallization layer (33). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Schutten to include a conductor from the die to the second metallization layer, as taught by Tamada, since it can help reduce or prevent oscillation of gate voltage (paragraphs 6-8).
Regarding claim 17, Schutten discloses a Y-capacitor (52) connected between the first island and the third island of the first metallization layer (20).
Regarding claim 18, Schutten discloses a second Y-capacitor connected between the first island and the second island of the first metallization layer (paragraph 18).
Regarding claim 19, Schutten discloses a method of producing a power semiconductor module, the method comprising:
providing a substrate comprising an electrically insulative material (16), a first metallization layer (20) at a frontside of the electrically insulative material (16), and a second metallization layer (18) at a backside of the electrically insulative material (16)
attaching a first power semiconductor die (23) of a power electronics circuit to the first metallization layer (20) at the frontside of the electrically insulative material (16), or embedding the first power semiconductor die (23) in the electrically insulative material (16)
Schutten does not disclose forming an opening in the electrically insulative material that exposes part of the second metallization layer from the electrically insulative material; and forming an electrical conductor in the opening and that is connected to the part of the second metallization layer exposed by the opening, the electrical conductor enabling a point of electrical contact for the second metallization layer at the frontside of the electrically insulative material. However, Tamada discloses forming an opening (66) in an insulative material (31) and an electrical conductor (66) disposed in the opening and connected to part of the second metallization layer (35) enabling a point of electrical contact for the second metallization layer (35) at the frontside of the electrically insulative material (16). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Schutten to include a conductor from the die to the second metallization layer, as taught by Tamada, since it can help reduce or prevent oscillation of gate voltage (paragraphs 6-8).
Regarding claim 21, Schutten discloses a pin (38) attached to the first island of the first metallization layer (20), wherein the pin (38) is configured for external attachment of one or more Y-capacitors (52) (paragraph 29).
Regarding claim 22, Tamada discloses the opening (68) in the electrically insulative material (31) is aligned with a gap (between 67 and 53) in the first metallization layer (53), and wherein forming the electrical conductor (68) comprises depositing copper in the opening and onto the frontside of the electrically insulative material (31) in a region of the gap such that the deposited copper does not contact the first metallization layer (53) (Figure 20; paragraph 188). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Schutten in view of Tamada.
Regarding claim 11, Schutten discloses a pin (38) attached to a side of the metal structure that faces away from the electrically insulative material (16), wherein the pin is configured for external attachment of one or more Y-capacitors (52) (paragraph 29).
Regarding claim 23, Schutten discloses attaching a pin (38) to a side of the deposited copper that faces away from the electrically insulative material (16), wherein the pin (38) is configured for external attachment of one or more Y-capacitors (52) (paragraphs 29 and 39-40).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Schutten et al. (US Publication No. 2018/0123476) in view of Tamada et al. (US Publication No. 2023/0197668), and further in view of Ong et al. (US Publication No. 2018/0366423).
Regarding claim 20, Schutten/Tamada discloses the limitations as discussed in the rejection of claim 19 above. Schutten/Tamada does not disclose forming the opening in the electrically insulative material comprises laser drilling a hole that extends through a first island of the first metallization layer, the electrically insulative material, and the second metallization layer, and wherein forming the electrical conductor comprises depositing copper on a sidewall of the hole. However, Ong discloses laser drilling through insulation and metal layers (Figure 8). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the hole formation method of Schutten to include laser drilling the hole, as taught by Tamada, since it can improve precision of the via diameter for optimal connectivity and conductivity (paragraph 33).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Perrin et al. (US Publication No. 2025/0294680) discloses a via (221) through a first metallization (21), and insulation layer (200), and a second metallization (32) for a power semiconductor device. Ahmed et al. (US Publication No. 2004/0228094) discloses a power semiconductor device on a laminated insulation layer with metallization layers and a gap in the die (Figure 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 3/30/2026 Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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