DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 04/08/2026 amendments of claims 1, 4-5 and 9 have been noted and entered.
The 04/08/2026 cancellation of claims 3, 14 and 16-20 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks page 6, filed 04/08/2026, with respect to the objection to the specification for minor informalities have been fully considered and are persuasive in light of the newly added amendments. The objections of record have been withdrawn.
Applicant's arguments filed 04/08/2026 regarding the rejection of claims 1, 3-5, 7-9, 11-12 and 14 under 35 U.S.C. 102, see Remarks pages 6-8, have been fully considered but they are not persuasive.
The applicant’s arguments do not include any specific details to explain how Mochizuki cannot be used as prior art to reject claim 1 under 35 U.S.C. 102. Thus, the examiner maintains the previously presented rejections. Additionally, the examiner details more rejections for the newly added amendments in the rejections appearing below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-9, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by S. Mochizuki et al., "Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 2.3.1-2.3.4, doi: 10.1109/IEDM13553.2020.9372041, Mochizuki.
Regarding claim 1; Mochizuki teaches a semiconductor structure, comprising:
a field-effect transistor region (Mochizuki: Annotated Fig (1) shared in this OA: Field-Effect Transistor) comprising a strained channel (SiGe Channel, see also the Abstract section: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”);
wherein the strained channel (SiGe Channel, see also the Abstract section of Mochizuki: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”) comprises a silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki) and
a silicon cladding layer (Silicon Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) disposed on the silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki),
wherein the silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki) comprises a middle portion (Middle Portion of SiGe Channel) having a first thickness and
outer portions (Outer Portion of SiGe Channel) having a second thickness greater than the first thickness; and
wherein the strained channel (SiGe Channel) further comprises inner spacers (Inner Spacer) disposed on a sidewall of the outer portions (Outer Portion of SiGe Channel) of the silicon germanium core layer (SiGe Channel) and a sidewall spacer (Sidewall Spacer) disposed on the inner spacers (Inner Spacer).
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Regarding claim 4; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the silicon cladding layer (Mochizuki: Annotated Fig (1) shared in this OA: Si Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) is disposed on the middle portion (Middle Portion of SiGe Channel).
Regarding claim 5; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the first thickness is less than about 1 nanometer (nm) (Mochizuki: See Section II: Device Fabrication and Characterization: Page 1: Right Column: lines 2-7: “A series of SiGe layers were epitaxially grown on trimmed Si NSs where Ge fractions and thicknesses of epitaxial SiGe layers were systematically changed from 0.2 to 0.35 and from 1 to 4 nm, respectively.”).
Regarding claim 7; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the silicon germanium core layer (Mochizuki: Annotated Fig (1) shared in this OA: SiGe Channel) comprises SiGex% where the atomic percent % for x ranges from about 5 to about 25% atomic percent (see the section titled Section I: Introduction: Page 1: Left Column: lines 33-35: “In this paper, we fabricate strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET through Si channel trimming and selective Si1-xGex epitaxial growth”).
Regarding claim 8; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the strained channel (Mochizuki: Annotated Fig (1) shared in this OA: SiGe Channel) further comprises a gate structure (Gate Structure).
Regarding claim 9; Mochizuki teaches a semiconductor structure, comprising:
a nanosheet field-effect transistor region (Mochizuki: Annotated Fig (1) shared in this OA: Field-Effect Transistor) comprising a strained nanosheet channel comprising a plurality of nanosheet layers (SiGe Channel, see also the Abstract section: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”);
wherein each nanosheet layer comprises a silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”) comprising a middle portion (Middle Portion of SiGe Channel) having a first thickness (thickness of Middle Portion of SiGe Channel) and outer portions (Outer Portion of SiGe Channel) having a second thickness (thickness of Outer Portion of SiGe Channel) greater than the first thickness (thickness of Middle Portion of SiGe Channel), and
a silicon cladding layer (Silicon Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) disposed on the middle portion (Middle Portion of SiGe Channel) of the silicon germanium core layer (SiGe Channel).
wherein the strained channel (SiGe Channel) further comprises inner spacers (Inner Spacer) disposed on a sidewall of the outer portions (Outer Portion of SiGe Channel) of the silicon germanium core layer (SiGe Channel) and a sidewall spacer (Sidewall Spacer) disposed on the inner spacers (Inner Spacer).
Regarding claim 11; Mochizuki teaches all the limitations of the semiconductor structure of claim 9.
Further, Mochizuki teaches wherein a top surface of the silicon cladding layer (Mochizuki: Annotated Fig (1): Silicon Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) is aligned with a top surface of the outer portions of the silicon germanium core layer (Outer Portion of SiGe Channel).
Regarding claim 12; Mochizuki teaches all the limitations of the semiconductor structure of claim 9.
Further, Mochizuki teaches wherein the first thickness is less than about 1 nanometer (nm) (Mochizuki: See Section II: Device Fabrication and Characterization: Page 1: Right Column: lines 2-7: “A series of SiGe layers were epitaxially grown on trimmed Si NSs where Ge fractions and thicknesses of epitaxial SiGe layers were systematically changed from 0.2 to 0.35 and from 1 to 4 nm, respectively.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over S. Mochizuki et al., "Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 2.3.1-2.3.4, doi: 10.1109/IEDM13553.2020.9372041, Mochizuki in view of Obradovic et al, US 20150295084 A1 (Obradovic).
Regarding claim 2; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
However, Mochizuki does not teach wherein the field-effect transistor region is an n-type field-effect transistor region.
Obradovic teaches wherein the field-effect transistor (Obradovic: Fig (3B): 100) region (105) is an n-type field-effect transistor region ([0008] and [0011]: “In some embodiments, the field effect transistor may be an n-type device”).
Mochizuki and Obradovic are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki by making the field-effect transistor region an n-type region as disclosed in Obradovic to lower the conduction losses and gate currents thus improving the device efficiency.
Regarding claim 10; Mochizuki teaches all the limitations of the semiconductor structure of claim 9.
Mochizuki does not teach wherein the nanosheet field-effect transistor region is an n-type nanosheet field-effect transistor region.
However, Obradovic teaches wherein the nanosheet field-effect transistor (Obradovic: Fig (3B): 100) region (105) is an n-type nanosheet field-effect transistor region ([0008] and [0011]: “In some embodiments, the field effect transistor may be an n-type device”).
Mochizuki and Obradovic are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki by making the nanosheet field-effect transistor region an n-type nanosheet field-effect transistor region as disclosed in Obradovic to lower the conduction losses and gate currents thus improving the device efficiency.
Regarding claim 15; Mochizuki teaches all the limitations of the semiconductor structure of claim 10.
Further, Mochizuki teaches wherein the n-type nanosheet field-effect transistor region further comprises a source/drain region (Mochizuki: Annotated Fig (1) shared in this OA: Source/Drain Regions) and a gate structure (Gate Structure).
Mochizuki does not teach an n-type nanosheet field effect transistor.
However, Obradovic teaches an n-type nanosheet field effect transistor (Obradovic: Fig (3B): 100, [0008] and [0011]: “In some embodiments, the field effect transistor may be an n-type device”).
Mochizuki and Obradovic are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki by making the nanosheet field-effect transistor region an n-type nanosheet field-effect transistor region as disclosed in Obradovic to lower the conduction losses and gate currents thus improving the device efficiency.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over S. Mochizuki et al., "Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 2.3.1-2.3.4, doi: 10.1109/IEDM13553.2020.9372041, Mochizuki in view of Huang et al, CN 114256336 A (Huang).
Regarding claim 6; Mochizuki teaches all the limitations of the semiconductor structure of claim 5.
However, Mochizuki does not teach wherein the second thickness is from about 5 nm to about 15 nm.
Huang teaches wherein the second thickness is from about 5 nm to about 15 nm (Huang: see the translation of Huang attached to this OA page 10 lines 3-5: “The thickness of the channel layer may be 3-30 nm”).
Mochizuki and Huang are considered analogous art. Thus, it would have obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki by making the second thickness in the range disclosed in Huang to lower the impedance of the channel and improve conductivity leading to a more efficient device.
Regarding claim 13; Mochizuki teaches all the limitations of the semiconductor structure of claim 12.
However, Mochizuki does not teach wherein the second thickness is from about 5 nm to about 15 nm.
Huang teaches wherein the second thickness is from about 5 nm to about 15 nm (Huang: see the translation of Huang attached to this OA page 10 lines 3-5: “The thickness of the channel layer may be 3-30 nm”).
Mochizuki and Huang are considered analogous art. Thus, it would have obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki by making the second thickness in the range disclosed in Huang to lower the impedance of the channel and improve conductivity leading to a more efficient device.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Shih et al, US 20230031490 A1 (Shih); discloses a transistor containing stacked strained nanosheet channels.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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