DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/19/2026 has been entered.
Remarks
The 08/06/2026 amendments of claims 1 and 9 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 5-8, filed 08/06/2026, with respect to the rejection(s) of claim(s) 1-2, 4-13 and 15 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Greene et al, US 20220310602 A1 (Greene).
New Grounds of Rejection
New grounds of rejection, prior art reference Greene et al, US 20220310602 A1 (Greene) appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1, 4-5, 7-9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over S. Mochizuki et al., "Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 2.3.1-2.3.4, doi: 10.1109/IEDM13553.2020.9372041, Mochizuki in view of Greene et al, US 20220310602 A1 (Greene).
Regarding claim 1; Mochizuki teaches a semiconductor structure, comprising:
a field-effect transistor region (Mochizuki: Annotated Fig (1) shared in this OA: Field-Effect Transistor) comprising a strained channel (SiGe Channel, see also the Abstract section: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”) disposed on a dielectric layer;
wherein the strained channel (SiGe Channel, see also the Abstract section of Mochizuki: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”) comprises a silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki) and
a silicon cladding layer (Silicon Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) disposed on the silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki),
wherein the silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki) comprises a middle portion (Middle Portion of SiGe Channel) having a first thickness and
outer portions (Outer Portion of SiGe Channel) having a second thickness greater than the first thickness;
wherein the strained channel (SiGe Channel) further comprises inner spacers (Inner Spacer) disposed on the outer portions (Outer Portion of SiGe Channel) of the silicon germanium core layer (SiGe Channel) and a sidewall spacer (Sidewall Spacer) disposed on a top surface of a topmost inner spacer (Inner Spacer); and
wherein a vertical sidewall of the dielectric layer is aligned with a vertical sidewall of each of the outer portions of the silicon germanium core layer, the inner spacers and the sidewall spacer.
PNG
media_image1.png
913
1408
media_image1.png
Greyscale
Mochizuki does not teach the field effect transistor disposed on a dielectric layer; and wherein a vertical sidewall of the dielectric layer is aligned with a vertical sidewall of each of the outer portions of the silicon germanium core layer, the inner spacers and the sidewall spacer.
Greene teaches disposed on a dielectric layer (Greene: Fig (16): 104); and wherein a vertical sidewall of the dielectric layer (vertical side wall of 104) is aligned with a vertical sidewall of each of the outer portions of the silicon germanium core layer (108; and while the channel 108 in Greene is made of silicon rather than silicon germanium, Greene is introduced to teach the dielectric layer at the bottom of the structure and the upper sidewall pacer and thus the composition of the channel material is irrelevant), the inner spacers (118) and the sidewall spacer (116).
Mochizuki and Greene are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art, to modify Mochizuki by introducing the dielectric layer at the bottom of the stack of nanosheets and support layers and the sidewall spacers to improve the isolation of the device against noise or short circuiting any of its components leading to a more reliable and better performing device.
PNG
media_image2.png
828
645
media_image2.png
Greyscale
Regarding claim 4; Mochizuki in view of Greene teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the silicon cladding layer (Mochizuki: Annotated Fig (1) shared in this OA: Si Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) is disposed on the middle portion (Middle Portion of SiGe Channel).
Regarding claim 5; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the first thickness is less than about 1 nanometer (nm) (Mochizuki: See Section II: Device Fabrication and Characterization: Page 1: Right Column: lines 2-7: “A series of SiGe layers were epitaxially grown on trimmed Si NSs where Ge fractions and thicknesses of epitaxial SiGe layers were systematically changed from 0.2 to 0.35 and from 1 to 4 nm, respectively.”).
Regarding claim 7; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the silicon germanium core layer (Mochizuki: Annotated Fig (1) shared in this OA: SiGe Channel) comprises SiGex% where the atomic percent % for x ranges from about 5 to about 25% atomic percent (see the section titled Section I: Introduction: Page 1: Left Column: lines 33-35: “In this paper, we fabricate strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET through Si channel trimming and selective Si1-xGex epitaxial growth”).
Regarding claim 8; Mochizuki teaches all the limitations of the semiconductor structure of claim 1.
Further, Mochizuki teaches wherein the strained channel (Mochizuki: Annotated Fig (1) shared in this OA: SiGe Channel) further comprises a gate structure (Gate Structure).
Regarding claim 9; Mochizuki teaches a semiconductor structure, comprising:
a nanosheet field-effect transistor region (Mochizuki: Annotated Fig (1) shared in this OA: Field-Effect Transistor) comprising a strained nanosheet channel disposed on a dielectric layer and comprising a plurality of nanosheet layers (SiGe Channel, see also the Abstract section: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”);
wherein each nanosheet layer comprises a silicon germanium core layer (SiGe Channel, see also the Abstract section of Mochizuki: “Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated”) comprising a middle portion (Middle Portion of SiGe Channel) having a first thickness (thickness of Middle Portion of SiGe Channel) and outer portions (Outer Portion of SiGe Channel) having a second thickness (thickness of Outer Portion of SiGe Channel) greater than the first thickness (thickness of Middle Portion of SiGe Channel), and
a silicon cladding layer (Silicon Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) disposed on the middle portion (Middle Portion of SiGe Channel) of the silicon germanium core layer (SiGe Channel);
wherein the strained nanosheet channel (SiGe Channel) further comprises inner spacers (Inner Spacer) disposed the outer portions (Outer Portion of SiGe Channel) of the silicon germanium core layer (SiGe Channel) and a sidewall spacer (Sidewall Spacer) disposed on a top surface of a topmost inner spacer (Inner Spacer); and
wherein a vertical sidewall of the dielectric layer is aligned with a vertical sidewall of each of the outer portions of the silicon germanium core layer, the inner spacers and the sidewall spacer.
Mochizuki does not teach the field effect transistor disposed on a dielectric layer; and wherein a vertical sidewall of the dielectric layer is aligned with a vertical sidewall of each of the outer portions of the silicon germanium core layer, the inner spacers and the sidewall spacer.
Greene teaches disposed on a dielectric layer (Greene: Fig (16): 104); and wherein a vertical sidewall of the dielectric layer (vertical side wall of 104) is aligned with a vertical sidewall of each of the outer portions of the silicon germanium core layer (108; and while the channel 108 in Greene is made of silicon rather than silicon germanium, Greene is introduced to teach the dielectric layer at the bottom of the structure and the upper sidewall pacer and thus the composition of the channel material is irrelevant), the inner spacers (118) and the sidewall spacer (116).
Mochizuki and Greene are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art, to modify Mochizuki by introducing the dielectric layer at the bottom of the stack of nanosheets and support layers and the sidewall spacers to improve the isolation of the device against noise or short circuiting any of its components leading to a more reliable and better performing device.
Regarding claim 11; Mochizuki teaches all the limitations of the semiconductor structure of claim 9.
Further, Mochizuki teaches wherein a top surface of the silicon cladding layer (Mochizuki: Annotated Fig (1): Silicon Cladding, see also Section II: Device Fabrication and Characterization of Mochizuki: page: 1 right column lines: 6-8: “Furthermore, the growth of Si cap on SiGe layers was evaluated as a method to improve channel interface characteristic.”) is aligned with a top surface of the outer portions of the silicon germanium core layer (Outer Portion of SiGe Channel).
Regarding claim 12; Mochizuki teaches all the limitations of the semiconductor structure of claim 9.
Further, Mochizuki teaches wherein the first thickness is less than about 1 nanometer (nm) (Mochizuki: See Section II: Device Fabrication and Characterization: Page 1: Right Column: lines 2-7: “A series of SiGe layers were epitaxially grown on trimmed Si NSs where Ge fractions and thicknesses of epitaxial SiGe layers were systematically changed from 0.2 to 0.35 and from 1 to 4 nm, respectively.”).
Claims 2, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over S. Mochizuki et al., "Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 2.3.1-2.3.4, doi: 10.1109/IEDM13553.2020.9372041, Mochizuki in view of Greene et al, US 20220310602 A1 (Greene) in further view of Obradovic et al, US 20150295084 A1 (Obradovic).
Regarding claim 2; Mochizuki in view of Greene teaches all the limitations of the semiconductor structure of claim 1.
However, Mochizuki in view of Greene does not teach wherein the field-effect transistor region is an n-type field-effect transistor region.
Obradovic teaches wherein the field-effect transistor (Obradovic: Fig (3B): 100) region (105) is an n-type field-effect transistor region ([0008] and [0011]: “In some embodiments, the field effect transistor may be an n-type device”).
Mochizuki in view of Greene and Obradovic are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki in view of Greene by making the field-effect transistor region an n-type region as disclosed in Obradovic to lower the conduction losses and gate currents thus improving the device efficiency.
Regarding claim 10; Mochizuki in view of Greene teaches all the limitations of the semiconductor structure of claim 9.
Mochizuki in view of Greene does not teach wherein the nanosheet field-effect transistor region is an n-type nanosheet field-effect transistor region.
However, Obradovic teaches wherein the nanosheet field-effect transistor (Obradovic: Fig (3B): 100) region (105) is an n-type nanosheet field-effect transistor region ([0008] and [0011]: “In some embodiments, the field effect transistor may be an n-type device”).
Mochizuki in view of Greene and Obradovic are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki in view of Greene by making the nanosheet field-effect transistor region an n-type nanosheet field-effect transistor region as disclosed in Obradovic to lower the conduction losses and gate currents thus improving the device efficiency.
Regarding claim 15; Mochizuki in view of Greene teaches all the limitations of the semiconductor structure of claim 10.
Further, Mochizuki teaches wherein the n-type nanosheet field-effect transistor region further comprises a source/drain region (Mochizuki: Annotated Fig (1) shared in this OA: Source/Drain Regions) and a gate structure (Gate Structure).
Mochizuki in view of Greene does not teach an n-type nanosheet field effect transistor.
However, Obradovic teaches an n-type nanosheet field effect transistor (Obradovic: Fig (3B): 100, [0008] and [0011]: “In some embodiments, the field effect transistor may be an n-type device”).
Mochizuki in view of Greene and Obradovic are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki by making the nanosheet field-effect transistor region an n-type nanosheet field-effect transistor region as disclosed in Obradovic to lower the conduction losses and gate currents thus improving the device efficiency.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over S. Mochizuki et al., "Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 2.3.1-2.3.4, doi: 10.1109/IEDM13553.2020.9372041, Mochizuki in view of Greene et al, US 20220310602 A1 (Greene) in further view of Huang et al, CN 114256336 A (Huang).
Regarding claim 6; Mochizuki in view of Greene teaches all the limitations of the semiconductor structure of claim 5.
However, Mochizuki in view of Greene does not teach wherein the second thickness is from about 5 nm to about 15 nm.
Huang teaches wherein the second thickness is from about 5 nm to about 15 nm (Huang: see the translation of Huang attached to this OA page 10 lines 3-5: “The thickness of the channel layer may be 3-30 nm”).
Mochizuki in view of Greene and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki in view of Greene by making the second thickness in the range disclosed in Huang to lower the impedance of the channel and improve conductivity leading to a more efficient device.
Regarding claim 13; Mochizuki in view of Greene teaches all the limitations of the semiconductor structure of claim 12.
However, Mochizuki does not teach wherein the second thickness is from about 5 nm to about 15 nm.
Huang teaches wherein the second thickness is from about 5 nm to about 15 nm (Huang: see the translation of Huang attached to this OA page 10 lines 3-5: “The thickness of the channel layer may be 3-30 nm”).
Mochizuki in view of Greene and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Mochizuki by making the second thickness in the range disclosed in Huang to lower the impedance of the channel and improve conductivity leading to a more efficient device.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Hasan et al, US 20230197855 A1 (Hasan); discloses a nanosheet transistor with sidewall spacer on top of the inner spacers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights