DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 and 15-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US PGPUB 2019/0147134 in view of Tien et al., US Patent No. 11,204,897.
In reference to claim 1, Wang teaches a method for editing an integrated circuit (IC) design layout, the method comprising:
receiving the design layout produced by a first set of design edit operations (Figure 2, and Paragraph 0031, 204 receiving corrected mask layout from 202), the design layout representing a circuit design of the IC (abstract, IC design layout) and comprising a plurality shapes that represent parts if the IC components including (1) circuit components of the IC or (2) wires of the IC that connect the circuit components (Paragraph [0021] main features, such as active region, gate electrode, source and drain, metal lines or via of the interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate are considered circuit components or wires);
using a machine-trained network (Paragraph 0045 machine learning such as a neural network) to produce a plurality of contours for each of a set of two or more IC components that represent a plurality of predicted manufactured shapes of the IC component (Paragraph [0030-1] determining contours for main features, each main feature being considered a component), the plurality of contours for each IC component comprising a first contour representing a first predicted shape of the IC component for a first variation of a manufacturing process parameter (Paragraph [0048] print-out probabilities of the contours at one of the exposure doses) and a second contour representing a second predicted shape of the IC component for a second variation of the manufacturing process parameter (Paragraph [0048] print-out probabilities of the contours at a second one of the exposure doses), the manufacturing process parameter associated with a manufacturing process that will be used to manufacture an IC from the design layout (paragraph 0013 manufacturing data associated with an IC manufacturer to be implemented to fabricate the IC device such as, for example, lithography processing data (e.g., statistical data of focus and/or energy or exposure dose); and
using the first and second produced contours that represent the first and second predicted shapes of at least one particular IC component to perform a second set of design edit operations (Paragraph 0017 and 0019 pointing out risks and highlight areas that may not properly print on the wafer).
Wang does not teach, wherein at least one edit operation in at least one set of design edit operations comprises modifying a position of a particular shape representing the particular IC component in the design layout. Tien teaches performing at least one edit operation in at least one set of design edit operations comprising modifying a position of a particular shape representing the particular IC component in the design layout (Column 4, lines 9-22, a logic operation (LOP) to modify the IC design layout according to manufacturing rules, a retarget process (RET) to modify the IC design layout to compensate for limitations in lithographic processes used by IC manufacturer 150, and a mask rule check (MRC) to modify the IC design layout to compensate for limitations during mask fabrication 144). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the teachings Tien for modifying a position of a particular shape representing the particular IC component in the design layout into the method of Wang because it would correct positioning errors of the components is the IC layout thus improving the IC manufacturing process.
In reference to claim 2, Wang in view of Tien teaches wherein using the machine-trained network comprises using the machine-trained network to produce a set of images representing the IC manufactured using a manufacturing process based on the design layout, wherein the manufacturing process is part of an overall process used to manufacture a semiconductor die based on the design layout (Wang - Paragraphs 0034-35 image based machine learning on the image of the IC design layout when it is transferred from the corresponding photomask to an IC substrate, such as a semiconductor wafer).
In reference to claim 3, Wang in view of Tien teaches performing image analysis on the set of images produced by the machine-trained network to generate the plurality of contours for each of the set of IC components(Wang - Paragraph 0035 a convolutional neural network (CNN, or ConvNet) is a class of deep, feed-forward artificial neural network that have successfully been applied to analyzing visual imagery and Paragraph 0048 performing simulations at different exposure doses to determine the print-out probability based on contour and intensity).
In reference to claim 4, Wang in view of Tien teaches wherein the machine-trained network is a neural network (Wang - Paragraph 0035).
In reference to claim 5, Wang in view of Tien teaches wherein the machine-trained network serves as a digital twin of a manufacturing process used to manufacture a semiconductor die based on the design layout and the manufacturing process parameter is a parameter associated with the manufacturing process (Wang - Paragraph 0034 OPC processes provide an image of the IC design layout when it is transferred from the corresponding photomask to an IC substrate, such as a semiconductor wafer and paragraph 0013 manufacturing data associated with an IC manufacturer to be implemented to fabricate the IC device such as, for example, lithography processing data (e.g., statistical data of focus and/or energy or exposure dose).
In reference to claim 6, Wang in view of Tien teaches wherein the design layout is a first design layout and the machine-trained network produces a second design layout that is a digital twin of a design that is produced after performing the manufacturing process on the first design layout (Wang - Paragraph 0034 OPC processes provide an image of the IC design layout when it is transferred from the corresponding photomask to an IC substrate and Paragraph 0018 OPC verification techniques provided herein may be used to verify (e.g., evaluate or predict) the design image).
In reference to claim 7, Wang in view of Tien teaches wherein the manufacturing process is a mask making process and the parameter relates to dosage used during mask making process (Wang - Paragraph 0013 exposure dose).
In reference to claim 8, Wang in view of Tien teaches wherein the manufacturing process is a wafer simulation process and the parameter relates to at least one of depth of focus and strength of exposure used during the wafer production process (Wang - Paragraph 0013 focus and/or energy).
In reference to claim 9, Wang in view of Tien teaches wherein the plurality of contours for each IC component in the set comprises a first contour relating to a maximum variation of the manufacturing process parameter and a second contour relating to a minimum variation of the manufacturing process parameter (Wang - Paragraph 0033 the dose can be increased or decreased within a range near nominal conditions the top and bottom of the range being the maximum and minimum variations).
In reference to claim 10, Wang in view of Tien teaches wherein the plurality of contours for each IC component in the set further comprises a third contour relating to a nominal variation of the manufacturing process parameter (Wang - Paragraph 0033 nominal condition and Paragraph 0048 different exposure doses could be a third simulation at the nominal condition).
In reference to claim 11, Wang in view of Tien teaches wherein the plurality of contours for each IC component in the set comprises a first contour relating to a maximum variation of the manufacturing process parameter and a second contour relating to a nominal variation of the manufacturing process parameter (Wang - Paragraph 0033 the dose can be increased or decreased within a range near nominal conditions, including the top of the range and the nominal condition).
In reference to claim 15, Wang in view of Tien teaches wherein the predicted shapes comprise shapes of the IC components after a wafer simulation operation (Wang - Paragraph 0013 lithography simulation to predict the image of the photomask created on the wafer).
In reference to claim 16, Wang in view of Tien teaches wherein the predicted shapes comprise shapes of the IC component after an IC has been manufactured using the design layout (Wang - Paragraph 0013 The simulation will generate virtual fabricated features corresponding to the IC design layout).
In reference to claim 22, Wang in view of Tien teaches iteratively, until a designer of the IC is satisfied with the design layout: using the machine-trained network to produce, based on a current design layout, pluralities of contours for sets of IC components that represent pluralities of predicted manufactured shapes of the IC components; and using the produced contours to perform a set of design edit operations that modify positions of shapes representing IC components in the design layout; and based on the design layout, generating a set of masks to use to fabricate the IC components on a semiconductor wafer through a set of lithographic operations, to reproduce the shapes of design layout on the semiconductor wafer (Wang – Paragraph [0031] The contour of the IC design layout is an image of the IC design layout when it is transferred from the corresponding photomask to an IC substrate, such as a semiconductor wafer. Based on the difference of the contour and expected IC design layout, this process may be iterated many times until the difference is within a tolerable range. The simulation is based on the manufacturing data. The simulation includes simulating the lithography process to transfer the IC design layout from the photomask to the IC substrate according to manufacturing data that includes lithography optical imaging data and may further include resist reaction data. In another example, the manufacturing data may further include etch data such as etching bias).
In reference to claims 17-20 drawn to a non-transitory machine readable medium containing all of the same functional limitations as found in claim 1 and 7-10, the same rejections apply.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US PGPUB 2019/0147134 in view of Tien et al., US Patent No. 11,204,897, Chan et al., US PGPUB 2009/0193369 and Phan et al., US Patent No 6,510,730.
In reference to claim 12, Wang in view of Tien teaches claim 1 as described above. They do not teach generating a display that superimposes the plurality of contoured shapes for each component on the design layout along with the components. Chan teaches displaying superimposed nominal, min and max contoured shapes for components (Figures 3A-1 and 3A-2). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate displaying the superimposed nominal, min and max contoured shapes for components as taught by Chan into the method of Wang to display the simulations at different exposure doses to determine the print-out probability based on contour and intensity because it would help in the visualization of the pointing out risks and highlight areas that may not properly print on the wafer.
Wang in view of Tien and Chan do not teach wherein the superimposed display includes the components. Phan teaches a display superimposing a contour of a component with the component (Figure 9a). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the teaching of Phan for superimposing a contour of a component with the component into the teaching of Wang in view of Tien and Chan for claim 1 and displaying the superimposed nominal, min and max contoured shapes for components to generate a display that superimposes the plurality of contoured shapes for each component on the design layout along with the components because it would further help in the visualization of the pointing out risks and highlight areas that may not properly print on the wafer by showing the contours and the components together.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US PGPUB 2019/0147134 in view of Tien et al., US Patent No. 11,204,897 and Miwa, US Patent No. 5,079,717.
In reference to claim 13, Wang in view of Tien teaches claim 1 as described above. They do not teach wherein at least of edit operation in at least one set of the design edit operations is a compaction operation. Miwa teaches a method for compaction processing of mask pattern data (abstract). Accordingly, it would it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the teachings of Miwa to perform compaction processing of mask pattern data as at least of edit operation in at least one set of the design edit operations claim 1 because it would prepare the mask pattern of a semiconductor integrated circuit device of different design standards (dimension standards), and in particular, to a method and a system for obtaining mask pattern data for LSIs of small size design standards.
In reference to claim 14, Wang in view of Tien teaches claim 1 as described above. They do not teach wherein at least of edit operation in at least one set of the design edit operations is a routing operation. Miwa teaches editing mask pattern data including changing wiring lines (abstract). Accordingly, it would it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the teachings of Miwa to perform a routing operation of mask pattern data including changing wiring lines at least of edit operation in at least one set of the design edit operations of claim 1 because it would prepare the mask pattern of a semiconductor integrated circuit device of different design standards (dimension standards), and in particular, to a method and a system for obtaining mask pattern data for LSIs of small size design standards.
Conclusion
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/B.B/Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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