DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 8/7/2025. Claims 1-20 are pending in this application. Claims 1 and 11 are amended. Claims 12-17 are previously withdrawn. Claims 18-20 are new.
Claims 1-11 and 18-20 are presented in this Office Action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, 10-11, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Morosawa (US 2012/0001167) in view of Yamazaki et al. (US 2016/0260839; hereinafter ‘Yamazaki’), and further in view of Konishi et al. (US 4746961; hereinafter ‘Konishi’).
Regarding claim 1, Morosawa teaches a semiconductor device (1A, FIG. 10, [0124]) comprising:
a substrate (11, [0125]);
a semiconductor structure (20, [0130]), disposed above the substrate and comprising two portions and one portion located between the two portions (20 disposed above 11 and comprises 20S, 20D and 20A);
a gate dielectric layer (30, [0125]), disposed on the semiconductor structure (30 disposed on 20); and
a gate (40, [0125]), disposed on the gate dielectric layer (40 disposed on 30), wherein a thickness of the gate electrode is larger than the thickness of the thin portion (40 is thicker than 20, since 40 has a thickness of 200 nm, while 20 has a thickness of 10 to 50 nm, [0049-0050, 0127]),
wherein a resistivity of at least a part of the two portions gradually increases with proximity to the substrate (the resistivity of 20 gradually increases with proximity to 11, FIG. 4, [0131]).
Morosawa does not teach the semiconductor device comprising: a semiconductor structure comprising two thick portions and a thin portion located between the two thick portions, wherein a thickness of the two thick portions is larger than a thickness of the thin portion to form a concave above the thin portion; wherein at least a portion of the gate dielectric layer is located in the concave; and wherein a width of the gate is larger than a width of the thin portion, and the gate is disposed to overlap with one part of the two thick portions and the thin portion in a normal direction of a top surface of the substrate to define a channel region having a first channel region and two second channel regions respectively, wherein the first channel region is directly connected between the two second channel regions, and wherein at least a portion of the gate is located within the concave of the semiconductor structure.
Yamazaki teaches a semiconductor device (FIGS. 4A-4E, [0114]) comprising:
a semiconductor structure (104, [0116]) comprising two thick portions and a thin portion located between the two thick portions (104 disposed above 100 and comprises left and right thick portions, hereinafter ‘LP1’ and ‘RP1’ respectively, and one central thin portion, hereinafter ‘P2’), wherein a thickness of the two thick portions is larger than a thickness of the thin portion (LP1 and RP1 are thicker than P2) to form a concave above the thin portion (104 forms a concave);
wherein at least a portion of the gate dielectric layer (110, [0119]) is located in the concave (110 is located in the concave of 104); and
the gate (116, [0120, 0124]) is disposed to overlap with one part of the two thick portions and the thin portion in a normal direction of a top surface of the substrate (116 overlaps with one part of LP1, RP1, and P2) to define a channel region (a region of 104) having a first channel region (a region of P2; hereinafter ‘FCR’) and two second channel regions (a region of LP1 and RP1; hereinafter ‘SCR’) respectively, wherein the first channel region is directly connected between the two second channel regions (FCR is directly connected between SCR).
As taught by Yamazaki, one of ordinary skill in the art would utilize and modify the above teaching into Morosawa to obtain and achieve the semiconductor device comprising: a semiconductor structure comprising two thick portions and a thin portion located between the two thick portions, wherein a thickness of the two thick portions is larger than a thickness of the thin portion to form a concave above the thin portion; wherein at least a portion of the gate dielectric layer is located in the concave; and the gate is disposed to overlap with one part of the two thick portions and the thin portion in a normal direction of a top surface of the substrate to define a channel region having a first channel region and two second channel regions respectively, wherein the first channel region is directly connected between the two second channel regions as claimed, because it is a well-established design principle in the field of metal oxide semiconductor layer-based thin film transistors that the channel region is formed thinner than the source/drain regions to enhance gate control, reduce leakage current, and improve switching performance. Furthermore, overlapping the gate electrode with both the thin channel region and adjacent thick regions is a routine layout strategy to optimize electrostatic coupling and carrier injection, and would have been readily adopted through standard design iteration.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yamazaki in combination with Morosawa due to above reason.
Morosawa in view of Yamazaki does not teach the semiconductor device comprising: wherein a width of the gate is larger than a width of the thin portion, and wherein at least a portion of the gate is located within the concave of the semiconductor structure.
Konishi teaches a semiconductor device (FIG. 6, Embodiment 2) comprising: wherein a width of the gate (a width of 6, col. 1, line 30) is larger (shown in FIG. 6) than a width of the thin portion (a width of the thin portion of 20, FIGS. 5C and 6, col. 3, line 27 and col. 5, line 2), and wherein at least a portion of the gate (a central portion of 6) is located within the concave of the semiconductor structure (20 forms a concave, shown in FIG. 6).
As taught by Konishi, one of ordinary skill in the art would utilize and modify the above teaching into Morosawa in view of Yamazaki to obtain and achieve the semiconductor device comprising: wherein a width of the gate is larger than a width of the thin portion, and wherein at least a portion of the gate is located within the concave of the semiconductor structure as claimed, because the mesa-shaped semiconductor layer inherently defines a concave channel region between the elevated source and drain portions, which enhances gate-to-channel coupling and reduces contact resistance by increasing the exposed surface area (col. 5, lines 1-5).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Konishi in combination with Morosawa in view of Yamazaki due to above reason.
Regarding claim 2, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 1, wherein the semiconductor structure comprises a first metal oxide semiconductor layer (Morosawa: 22, FIG. 10, [0130]) and a second metal oxide semiconductor layer (21), the first metal oxide semiconductor layer is located between the substrate and the second metal oxide semiconductor layer (22 is located between 11 and 21), and the first metal oxide semiconductor layer and the second metal oxide semiconductor layer are stacked to form the two thick portions (22 and 21 are stacked to form 20S and 20D).
Regarding claim 3, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 2, wherein the second metal oxide semiconductor layer comprises a first island structure and a second island structure separated from each other (Morosawa: 21 comprises a left 21 and a right 21 separated from each other, FIG. 10), the first island structure and the first metal oxide semiconductor layer are stacked to form one of the thick portions (L21 and 22 are stacked to form 20S), and the second island structure and the first metal oxide semiconductor layer are stacked to form the other of the thick portions (R21 and 22 are stacked to form 20D).
Regarding claim 4, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 3, wherein the thin portion comprises a part of the first metal oxide semiconductor layer between the two thick portions (Morosawa: 20A comprises 22 between 20S and 20D, FIG. 10), and a thickness of the first metal oxide semiconductor layer is smaller than a thickness of the second metal oxide semiconductor layer (22 is thinner than 21, [0130]).
Regarding claim 7, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 2, the first metal oxide semiconductor layer and the second metal oxide semiconductor layer comprise identical metal elements (Morosawa: 22 and 21 comprise identical metal elements, such as zinc, indium and zinc, or indium and gallium, since 22 is formed of IGZO and 21 is formed of a different oxide semiconductor such as zinc oxide, IZO, or IGO, [0127-0128]).
Regarding claim 8, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 2, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer comprise different metal elements (Morosawa: 22 and 21 include different metal elements, since 22 is formed of IGZO and 21 is formed of a different oxide semiconductor such as zinc oxide, IZO, or IGO, [0127-0128]).
Regarding claim 10, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 2, wherein an oxygen concentration of the first metal oxide semiconductor layer is higher than an oxygen concentration of the second metal oxide semiconductor layer (Morosawa: 22 has higher oxygen concentration than 21, FIG. 4), and an indium concentration of the first metal oxide semiconductor layer is lower than an indium concentration of the second metal oxide semiconductor layer (22 has lower indium concentration than 21, since 22 is formed of IGZO and 21 is formed of a different oxide semiconductor such as zinc oxide, [0127-0128]).
Regarding claim 11, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 1, wherein a hydrogen concentration of the one part of the two thick portions close to the thin portion is lower than a hydrogen concentration of the other part of the two thick portions away from the thin portion (Morosawa: 20S and 20D have a higher hydrogen concentration than 20A since 40 blocks plasma, which introduces hydrogen, FIG. 8A, [0111]).
Regarding claim 18, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 1, but Morosawa in view of Yamazaki does not teach the semiconductor device wherein the at least a portion of the gate dielectric layer completely covers and contacts an entire inner surface of the concave.
Konishi, however, provides the semiconductor device wherein the at least a portion of the gate dielectric layer completely covers and contacts an entire inner surface of the concave (a portion of 5 completely covers and contacts an entire inner surface of the concave of 20, FIG. 6, col. 4, line 66).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Konishi to obtain and achieve the semiconductor device wherein the at least a portion of the gate dielectric layer completely covers and contacts an entire inner surface of the concave as claimed, because the gate dielectric layer is conformally formed by CVD right above the channel region so as to ensure effective field coupling and electrical insulation (col. 1, lines 29-32, col. 4, lines 18-21).
Regarding claim 19, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 1, but Morosawa in view of Yamazaki does not teach the semiconductor device wherein an entire top surface of the thin portion is covered by the at least a portion of the gate dielectric layer.
Konishi, however, provides the semiconductor device wherein an entire top surface of the thin portion is covered by the at least a portion of the gate dielectric layer (an entire top surface of the thin portion of 20 is covered by the at least a portion of 5, FIG. 6, col. 4, line 66).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Konishi to obtain and achieve the semiconductor device wherein an entire top surface of the thin portion is covered by the at least a portion of the gate dielectric layer as claimed, because the gate dielectric layer is conformally formed by CVD right above the channel region so as to ensure effective field coupling and electrical insulation (col. 1, lines 29-32, col. 4, lines 18-21).
Regarding claim 20, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 1, wherein the thin portion of the semiconductor structure constitutes the first channel region (Morosawa: 20A constitutes the first channel region, FIG. 8C, [0111]), each of the two thick portions has a doped region (20S and 20D has 21) and one of the two second channel regions (20S and 20D has 20), a hydrogen concentration of each of the two second channel regions is lower than a hydrogen concentration of each of the doped regions (a hydrogen concentration of 21 is higher than that in the underlying region 20 of 20A and 20 of 20D, since hydrogen comes from the top, FIG. 8A), the hydrogen concentration of each of the doped regions gradually decreases with proximity to the substrate (since hydrogen introduced from the top and diffuses downward, resulting in a gradient where the lower part of 21 closer to 11 becomes more hydrogen-poor).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Morosawa (US 2012/0001167) in view of Yamazaki (US 2016/0260839) and Konishi et al. (US 4746961), and further in view of Chou (US 2015/0214248).
Regarding claim 5, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 2, but does not teach the semiconductor device wherein the first metal oxide semiconductor layer comprises a first island structure and a second island structure separated from each other, the first island structure and the second metal oxide semiconductor layer are stacked to form one of the thick portions, and the second island structure and the second metal oxide semiconductor layer are stacked to form the other of the thick portions.
Chou teaches a semiconductor device (60’, FIG. 10, [0036]) wherein the first metal oxide semiconductor layer comprises a first island structure and a second island structure separated from each other (14 comprises 142 and 141 separated from each other, [0019]), the first island structure and the second metal oxide semiconductor layer are stacked to form one of the thick portions (142 and 16 are stacked to form the part of the left side of the thick region, [0020]), and the second island structure and the second metal oxide semiconductor layer are stacked to form the other of the thick portions (142 and 16 are stacked to form the part of the left side of the thick region).
Although Chou does not teach that the second metal oxide layers fully overlap the first and second island structures, Chou nevertheless recognizes that the degree of overlap is a design variable that can be optimized to achieve desired electrical characteristics, such as reduced contact resistance or improved device symmetry [0020, 0027].
As taught by Chou, one of ordinary skill in the art would utilize and modify the above teaching into Morosawa in view of Yamazaki and Konishi to obtain and achieve the semiconductor device wherein the first metal oxide semiconductor layer comprises a first island structure and a second island structure separated from each other, the first island structure and the second metal oxide semiconductor layer are stacked to form one of the thick portions, and the second island structure and the second metal oxide semiconductor layer are stacked to form the other of the thick portions as claimed, because the metal oxide semiconductor channel layer is electrically coupled to source/drain structures using an intermediate connection electrode. The use of a metal oxide semiconductor material as such an intermediate electrode is a well-known technique in the art, intended to reduce contact resistance and protect the oxide channel during subsequent fabrication steps [0027, 0029]. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chou in combination with Morosawa in view of Yamazaki and Konishi due to above reason.
Regarding claim 6, Morosawa in view of Yamazaki, Konishi, and Chu teaches the semiconductor device according to claim 5, wherein the thin portion comprises a part of the second metal oxide semiconductor layer between the two thick portions (Morosawa: 20A comprises 22 between 20S and 20D, FIG. 10), and a thickness of the first metal oxide semiconductor layer is larger than a thickness of the second metal oxide semiconductor layer (22 is thicker than 21, [0130]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Morosawa (US 2012/0001167) in view of Yamazaki (US 2016/0260839) and Konishi et al. (US 4746961), and further in view of Yoon et al. (KR 2011/0021632; hereinafter ‘Yoon’).
Regarding claim 9, Morosawa in view of Yamazaki and Konishi teaches the semiconductor device according to claim 1, wherein the thickness of the two thick portions is within a range from 7 nm to 120 nm (Morosawa: 20 has a thickness of around 50 nm, [0049]), and the thickness of the thin portion is within a range from 2 nm to 60 nm.
Morosawa in view of Yamazaki and Konishi does not teach the semiconductor device wherein the thickness of the thin portion is within a range from 2 nm to 60 nm.
Yoon teaches a semiconductor device (Fig. 1b, [0032]) wherein the thickness of the thin portion is within a range from 2 nm to 60 nm (104 has a thickness of 5 to 50 nm, [0076]).
As taught by Yoon, one of ordinary skill in the art would utilize and modify the above teaching into Morosawa in view of Yamazaki and Konishi to obtain and achieve the semiconductor device wherein the thickness of the thin portion is within a range from 2 nm to 60 nm as claimed, because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yoon in combination with Morosawa in view of Yamazaki and Konishi due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 10/14/25