DETAILED ACTION
This action is responsive to the application No. 17/993,473 filed on November 23, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/08/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1, 2, 6-12, and 14-21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2018/0331111).
Regarding Claim 21, Lee (see, e.g., Figs. 1-3), teaches a semiconductor device 100 comprising:
a substrate 102 including a gate trench 108 (see, e.g., pars. 0037, 0040);
a gate dielectric layer 120 formed along a sidewall surface and a bottom surface of the gate trench 108 (see, e.g., par. 0042);
a bottom gate electrode 132 filling a bottom part of the gate trench 108 over the gate dielectric layer 120 and formed of a first metal nitride (see, e.g., pars. 0045, 0047-0048);
a top gate electrode 134 filling a part of the gate trench 108 over the bottom gate electrode 132 and formed of a second metal nitride (see, e.g., pars. 0049-0054); and
a capping layer 136 gap-filling the reminder of the gate trench 108 over the top gate electrode 134 (see, e.g., par. 0043),
wherein:
the first metal nitride includes titanium nitride containing silicon (see, e.g., par. 0047), and
the second metal nitride includes titanium nitride containing, as a dopant, silicon-free low work function control element (see, e.g., pars. 0049-0054).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 12, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0082767) in view of Jang (US 2011/0260242).
Regarding Claim 11, Kim (see, e.g., Figs. 1, 2A-2B), teaches a semiconductor device 100 comprising:
a substrate 101 including a gate trench 105 (see, e.g., pars. 0027, 0030);
a gate dielectric layer 110 formed along a sidewall surface and a bottom surface of the gate trench 105 (see, e.g., par. 0036);
a lower gate electrode 121 filling a lower portion of the gate trench 105 over the gate dielectric layer 110 and formed of a first metal nitride, the first metal nitride having a first grain size and containing silicon, the first metal nitride including titanium nitride (see, e.g., pars. 0036, 0040);
an upper gate electrode 122 partially filling the gate trench 105 over the lower gate electrode 121 and formed of a second metal nitride, the second metal nitride having a lower silicon content (i.e., 0%) than a silicon content of the first metal nitride, the second metal nitride including titanium nitride (see, e.g., par. 0042); and
a capping layer 130 gap-filling the remainder of the gate trench 105 over the upper gate electrode 122 (see, e.g., par. 0036).
Kim is silent with respect to the claim limitation that the second metal nitride contains, as a dopant, a low work function control element.
Jang (see, e.g., Fig. 2), on the other hand, teaches that the second metal nitride 27 contains, as a dopant, a low work function control element, to reduce the work function of the gate electrode material, thereby preventing the occurrence of the GIDL current in the region where the gate electrode and the junction region 11 contact each other (see, e.g., pars. 0023-0024).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kim’s device, the second metal nitride containing, as a dopant, a low work function control element, as taught by Jang, to reduce the work function of the gate electrode material, thereby preventing the occurrence of the GIDL current in the region where the gate electrode and the junction region contact each other.
Regarding Claim 12, Kim and Jang teach all aspects of claim 11. Kim (see, e.g., Figs. 1, 2A-2B), teaches that the first and second metal nitrides include a same metallic material (i.e., TiN) (see, e.g., pars. 0036, 0042).
Regarding Claim 18, Kim and Jang teach all aspects of claim 11. Kim (see, e.g., Figs. 1, 2A-2B), teaches a source/drain region 107/108 formed on the substrate 101 disposed on both sides of the gate trench 105 (see, e.g., par. 0032).
Regarding Claim 19, Kim and Jang teach all aspects of claim 11. Jang (see, e.g., Fig. 2), teaches that an upper surface of the lower gate electrode 26 is disposed at a lower level than a bottom surface of the source/drain region 11 (see, e.g., pars. 0018, 0023).
Regarding Claim 20, Kim and Jang teach all aspects of claim 11. Kim (see, e.g., Figs. 1, 2A-2B), teaches that the source/drain region 107/108 horizontally overlaps part or all of the upper gate electrode 122 (see, e.g., Fig. 2A).
Regarding Claim 21, Kim (see, e.g., Figs. 1, 2A-2B3), teaches a semiconductor device 100 comprising:
a substrate 101 including a gate trench 105 (see, e.g., pars. 0027, 0030);
a gate dielectric layer 110 formed along a sidewall surface and a bottom surface of the gate trench 105 (see, e.g., par. 0036);
a bottom gate electrode 121 filling a bottom part of the gate trench 105 over the gate dielectric layer 110 and formed of a first metal nitride (see, e.g., pars. 0036, 0040);
a top gate electrode 122 filling a part of the gate trench 105 over the bottom gate electrode 121 and formed of a second metal nitride (see, e.g., par. 0042); and
a capping layer 130 gap-filling the reminder of the gate trench 105 over the top gate electrode 122 (see, e.g., par. 0036),
wherein:
the first metal nitride includes titanium nitride containing silicon (see, e.g., pars. 0036, 0040), and
the second metal nitride includes titanium nitride (see, e.g., par. 0042).
Kim is silent with respect to the claim limitation that the second metal nitride contains, as a dopant, silicon-free low work function control element.
Jang (see, e.g., Fig. 2), on the other hand, teaches that the second metal nitride 27 contains, as a dopant, silicon-free low work function control element, to reduce the work function of the gate electrode material, thereby preventing the occurrence of the GIDL current in the region where the gate electrode and the junction region 11 contact each other (see, e.g., pars. 0023-0024).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kim’s device, the second metal nitride containing, as a dopant, silicon-free low work function control element, as taught by Jang, to reduce the work function of the gate electrode material, thereby preventing the occurrence of the GIDL current in the region where the gate electrode and the junction region contact each other.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0082767) in view of Jang (US 2011/0260242) and further in view of Hsu (US 2022/0005697).
Regarding Claim 14, Kim and Jang teach all aspects of claim 11. They do not teach that the low work function control element includes phosphorus.
Kim and Jang disclose the claimed invention except for the use of TiN doped with N, O As, Al, H instead of TiN doped with phosphorus. Hsu, on the other hand, teaches that phosphorus and N, As, Al are equivalent materials known in the art (see, e.g., par. 0040). Therefore, because these work function control elements were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute phosphorus for N, As, Al, since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0082767) in view of Jang (US 2011/0260242) and further in view of Tae-Su Jang (US 2018/0174845).
Regarding Claim 15, Kim and Jang teach all aspects of claim 11. They do not teach a diffusion barrier layer disposed between the lower gate electrode and the upper gate electrode.
Tae-Su Jang (see, e.g., Fig. 5A), in similar semiconductor devices to Kim and Jang, on the other hand, teaches a diffusion barrier layer 113 disposed between the lower gate electrode 108 and the upper gate electrode 114, to prevent a diffusion between the low work function layer 114 and the gate conductive layer 108 (see, e.g., par. 0119).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kim’s/Jang’s device, a diffusion barrier layer disposed between the lower gate electrode and the upper gate electrode, as taught by Tae-Su Jang, to prevent a diffusion between the low work function layer and the gate conductive layer.
Allowable Subject Matter
Claims 1, 2, and 6-10 are allowed.
Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments filed on 01/08/2026 with respect to the rejection of claims 11 and 21 have been fully considered but are moot in view of the new grounds of rejection.25
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
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/Nelson Garces/
Primary Examiner, Art Unit 2814