DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 11/25/25.
Applicant’s amendment to claims 1 and 4 is acknowledged.
Applicant’s cancellation of claims 2, 3, 5 and 8-13 is acknowledged.
Applicant’s addition of new claim 14 is acknowledged.
Claims 1, 4, 6, 7 and 14 are pending and subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda, US Publication No. 2017/0208254 A1 (of record) in view of Yamaguchi, Japanese Publication No. JP 2013-222772A (of record, see attached English machine translation) and Roh et al., US Patent No. 6,521,990.
Ikeda teaches:
1. A packaging module comprising (see fig. 48):
a circuit board (811 or 811+890);
a light conducting member (821) arranged on the circuit board, the light conducting member and the circuit board cooperatively enclosing a chamber (e.g. chamber surrounding chip 851);
a chip (851) arranged in the chamber; and
wherein the light conducting member (821), the chip (851),…are arranged on a same surface of the circuit board (811),
the circuit board (811 or 811+890) comprises a substrate layer (e.g. material of 811), a first conductive wiring layer (861+890), and a second conductive wiring layer (841), the substrate layer is sandwiched between the first conductive wiring layer and the second conductive wiring layer, the first conductive wiring layer (861+890) comprises a chip pad (890) and a connection pad (861), the chip (851) is supported on and fixed to the chip pad (890) and is electrically connected with the connection pad (861) through a bonding wire (871), a conductor structure (e.g. vertical via between 861 and 841) is arranged in the substrate layer (e.g. material of 811), the conductor structure is connected to the connection pad (890) and the second conductive wiring layer (841),… See Ikeda at para. [0526] – [0530].
Ikeda does not expressly teach a radiation fin.
In an analogous art, Yamaguchi teaches:
(see figs. 1 and 3) a radiation fin (330) located outside the chamber (339; “cavity”), surrounding the chip (200), and being in contact with the light conducting member (500);
wherein the light conducting member (500), the chip (200), and the radiation fin (330) are arranged on a same surface of the circuit board (100). See Yamaguchi at English machine translation pages 2-4.
Ikeda does not expressly teach:
the circuit board further comprises a first through hole extending in a thickness direction of the circuit board and spaced from the conductor structure, the first through hole is correspondingly positioned relative to the chip, a portion of the chip pad is exposed to the first through hole, and a portion of the second conductive wiring layer is exposed to the first through hole.
In an analogous art, Roh teaches:
(see fig. 2) a circuit board (20+27) comprises a substrate layer (21+27), a first conductive wiring layer (30, 34, 35, 36), and a second conductive wiring layer (33, 37, 39), the substrate layer is sandwiched between the first conductive wiring layer and the second conductive wiring layer, the first conductive wiring layer (30, 34, 35, 36) comprises a chip pad (34) and a connection pad (30, 35, 36), the chip (10) is supported on and fixed to the chip pad (34) and is electrically connected with the connection pad (30, 35) through a bonding wire (50), a conductor structure (40, 40a) is arranged in the substrate layer (21+27), the conductor structure is connected to the connection pad (30, 35) and the second conductive wiring layer (33),
the circuit board further comprises a first through hole (41, 42) extending in a thickness direction of the circuit board (20+27) and spaced from the conductor structure (40,40a), the first through hole (41, 42) is correspondingly positioned relative to the chip (10), a portion of the chip pad (34) is exposed to the first through hole (41, 42), and a portion of the second conductive wiring layer (37) is exposed to the first through hole (41, 42). See Roh at col 2-3, ln 1–67.
Ikeda further teaches:
6. The packaging module of claim 1, wherein a surface of the light conducting member (821) facing the circuit board (811 or 811+890) defines a groove, the circuit board (811 or 811+890) covers the groove to form the chamber (e.g. chamber surrounding chip 851), the light conducting plate (821) defines a second through hole (e.g. opening occupied by 835) communicating with the chamber, the second through hole is correspondingly positioned relative to the chip (851), fig. 48.
Yamaguchi further teaches:
7. The packaging module of claim 1, wherein a thermally conductive adhesive layer (302) is sandwiched between the radiation fin (330) and the circuit board (100). See Yamaguchi at page 5.
Regarding claim 14:
Ikeda further teaches:
14. The packaging module of claim 1, wherein the first conductive wiring layer (861) and the second conductive wiring layer (841) are located in the substrate layer (e.g. material of 811) which surrounds the first conductive wiring layer and the second conductive wiring layer, the first conductive wiring layer (861) is exposed from an upper surface of the substrate layer (e.g. material of 811), and the second conductive wiring layer (841) is exposed from a lower surface of the substrate layer (e.g. material of 811), fig. 48.
Roh also teaches:
14. The packaging module of claim 1, wherein the first conductive wiring layer (30, 34, 35, 36) and the second conductive wiring layer (33, 37, 39) are located in the substrate layer (21+27) which surrounds the first conductive wiring layer and the second conductive wiring layer, the first conductive wiring layer (30, 34, 35, 36) is exposed from an upper surface of the substrate layer (21+27), and the second conductive wiring layer (33, 37, 39) is exposed from a lower surface of the substrate layer (21+27), fig. 2
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Ikeda with the teachings of Yamaguchi because “Further, according to the first embodiment, by providing the frame 300 with the metal plate 330, the heat inside the imaging device package can be radiated to the lens holder 500 via the metal plate 330. In this manner, by conducting heat radiation to the outside of the image pickup device package in various ways, the conductivity of the generated heat can be improved and the heat release performance of the image pickup device 200 can be improved.” See Yamaguchi at English machine translation page 5.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Ikeda with the teachings of Roh because forming a first through hole (spaced from the conductor structure) in the circuit board provides for heat dissipation. See Roh at col 3, ln 20–43.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda in view of Yamaguchi and Roh, as applied to claim 1 above, in further view of Jang, US Publication No. 2009/0121362 A1 (of record).
Regarding claim 4:
Ikeda, Yamaguchi and Roh teach all the limitations of claim 1 above, but do not expressly teach wherein the chip is fixed to the chip pad through a thermally conductive adhesive layer.
In an analogous art, Jang teaches:
(see fig. 2D) wherein a chip (120) is fixed to the chip pad (310 directly below 120) through a thermally conductive adhesive layer (200),para. [0030] – [0036].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Ikeda with the teachings of Jang because applying, melting and hardening a thermally conductive adhesive layer such as solder the chip may be adhered to the circuit board. See Jang at para. [0033] – [0034].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michele Fan/
Primary Examiner, Art Unit 2818
29 January 2026