Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 11/20/2025. Claims 1-2, 6-12 and 14-21 are pending in this application. Claims 1 and 9 are amended. Claims 20 and 21 are previously presented.
Claim Objections
The claims are objected because of the following reasons:
Re claims 20-21: delete “(New”), insert --(Previously Presented)--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over DeLyon et al. (US 10720456; hereinafter ‘DeLyon’).
Regarding claim 1, DeLyon teaches a focal plane array (FIG. 2, col 3, lines 21-27), comprising:
a substrate wafer (201, col 7, line 3);
an n-type indium arsenide layer (205 is n-type and comprises InAs, col. 6, lines 49-51, col 7, lines 25-26, 30-31) disposed atop the substrate wafer (shown in FIG. 2);
a barrier layer (207, col 7, lines 36-37) disposed atop the substrate wafer (shown in FIG. 2); and
a doped n-type layer (209 is doped with the n-type dopant, col 7, line 47, 51-54) disposed atop the barrier layer (shown in FIG. 2).
Delyon does not explicitly teach the focal plane array wherein a thickness of the n-type indium arsenide layer is greater than 4 microns and less than or equal to 8 microns.
Delyon, however discloses the focal plane array wherein a thickness of the n-type indium arsenide layer (205) is 3 µm to 5 µm (col. 9, lines 7 and 11).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the thickness of the n-type indium arsenide layer of Delyon to obtain the focal plane array wherein a thickness of the n-type indium arsenide layer is greater than 4 microns and less than or equal to 8 microns as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 7, DeLyon teaches the focal plane array of claim 1, wherein the n-type indium arsenide layer detects wavelengths in the range of 400 nm to 3 microns (the spectral response of the polycrystalline InAs barrier detector has a cutoff wavelength of 3.03 µm, FIG. 5B, col 13, lines 52-57).
Regarding claim 8, DeLyon teaches the focal plane array of claim 1, wherein the barrier layer is a Group III-V compound semiconducting material (207 is a third Group III-V compound semiconductor material, col 7, lines 36-39).
Claims 2, 6, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over DeLyon (US 10720456) in view of Dixon (US 9111830).
Regarding claim 2, DeLyon teaches the focal plane array of claim 1, but does not teach the focal plane array wherein the substrate wafer is gallium antimony.
Dixon teaches a focal plane array (col 1, lines 9-10) comprising the substrate wafer, wherein the substrate wafer is gallium antimony (substrate comprising GaSb, col 5, line 62).
As taught by Dixon, one of ordinary skill in the art would utilize and modify the above teaching into DeLyon to obtain and achieve the focal plane array comprising the substrate wafer, wherein the substrate wafer comprises gallium antimony as claimed, because GaSb are well-known material and widely used as a substrate material in the art and is suitable for achieving the desired electro-optical performance (col 5, line 60~col 6, line 2). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dixon in combination with DeLyon due to above reason.
Regarding claim 6, DeLyon teaches the focal plane array of claim 1, but does not teach the focal plane array wherein a metal layer is disposed atop the doped n-type layer.
Dixon teaches a focal plane array (col 1, lines 9-10) wherein a metal layer (6, FIG. 3C, col 7, lines 14-15, 18) is disposed atop the doped n-type layer (6 is disposed atop 5).
As taught by Dixon, one of ordinary skill in the art would utilize and modify the above teaching into DeLyon to obtain and achieve the focal plane array wherein a metal layer is disposed atop the doped n-type layer as claimed, because the metal contact atop the diode junction provides low contact resistance or ohmic conditions, which are crucial for the efficient transmission of electrical signals and the functional completion of the focal plane array (col 7, lines 13-29).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dixon in combination with DeLyon due to above reason.
Regarding claim 20, DeLyon teaches the focal plane array of claim 1, but does not teach the focal plane array wherein the substrate wafer is indium arsenide.
Dixon teaches a focal plane array (col 1, lines 9-10) wherein the substrate wafer is indium arsenide (substrate comprising InAs, col 5, lines 62-63).
As taught by Dixon, one of ordinary skill in the art would utilize and modify the above teaching into DeLyon to obtain and achieve the focal plane array wherein the substrate wafer is indium arsenide as claimed, because InAs is well-known material and widely used as a substrate material in the art and is suitable for achieving the desired electro-optical performance (col 5, line 60~col 6, line 2). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dixon in combination with DeLyon due to above reason.
Regarding claim 21, DeLyon teaches the focal plane array of claim 1, but does not teach the focal plane array wherein the substrate wafer is gallium arsenide.
Dixon teaches a focal plane array (col 1, lines 9-10) wherein the substrate wafer is gallium arsenide (substrate comprising GaAs, col 5, lines 62-63).
As taught by Dixon, one of ordinary skill in the art would utilize and modify the above teaching into DeLyon to obtain and achieve the focal plane array wherein the substrate wafer is gallium arsenide as claimed, because GaAs is well-known material and widely used as a substrate material in the art and is suitable for achieving the desired electro-optical performance (col 5, line 60~col 6, line 2). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dixon in combination with DeLyon due to above reason.
Claims 9, 11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wicks (US 2010/0230720) in view of DeLyon (US 10720456).
Regarding claim 9, Wicks teaches a focal plane array (10, FIGURE 9, [0054]), comprising:
a substrate wafer (18);
an n-type indium arsenide layer (12) disposed atop the substrate wafer (shown in FIGURE 9); and
a p-type indium arsenide layer (14) positioned at a first surface of the n-type indium arsenide layer opposite an interface surface of the n-type indium arsenide and the substrate wafer (shown in FIGURE 9).
Wicks does not teach the focal plane array comprising the p-type indium arsenide layer implanted into the first surface of an n-type indium arsenide layer, wherein a thickness of the n-type indium arsenide layer is greater than 4 microns and less than or equal to 8 microns.
DeLyon teaches a focal plane array (col 3, lines 21-22) comprising the p-type indium arsenide layer implanted into the first surface of an n-type indium arsenide layer (a portion of the doping is performed after deposition of the Group III-V compound semiconductor material using ion implantation of dopant materials (col 5, lines 4-6), wherein a thickness of the n-type indium arsenide layer is greater than 4 microns and less than or equal to 8 microns (the thickness of 205 is 3 µm to 5 µm, col. 9, lines 7 and 11).
As taught by DeLyon, one of ordinary skill in the art would utilize and modify the above teaching into Wicks to obtain and achieve the focal plane array comprising the p-type indium arsenide layer implanted into the first surface of an n-type indium arsenide layer, wherein a thickness of the n-type indium arsenide layer is greater than 4 microns and less than or equal to 8 microns as claimed, because ion implantation is a common technique to form p-type regions with controlled depth and doping concentration. Further it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by DeLyon in combination with Wicks due to above reason.
Regarding claim 11, Wicks in view of DeLyon teaches the focal plane array of claim 9, wherein the substrate wafer comprises indium arsenide (Wicks: 18 is InAs, Figure 9, [0054]).
Regarding claim 14, Wicks in view of DeLyon teaches the focal plane array of claim 9, but Wicks does not teach the focal plane array wherein the n-type indium arsenide layer detects wavelengths in the range of 400 nm to 3 microns.
DeLyon teaches the focal plane array wherein the n-type indium arsenide layer detects wavelengths in the range of 400 nm to 3 microns (203 is n-type and comprises InAsSb and the spectral response of the polycrystalline InAs barrier detector has a cutoff wavelength of 3.03 µm, FIGS. 2 and 5B, col 7, lines 6-7, 27, Col 8, lines 49-52, col 13, lines 52-57).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in DeLyon to include the focal plane array wherein the n-type indium arsenide layer detects wavelengths in the range of 400 nm to 3 microns as claimed, because this modification allows for an expanded detection range from visible light to near-infrared and provides consistent performance across a wide range of operating temperatures (col 13, lines 45-60).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wicks (US 2010/0230720) in view of DeLyon (US 10720456), and further in view of Dixon (US 9111830).
Regarding claim 10, Wicks in view of DeLyon teaches the focal plane array of claim 9, but does not teach the focal plane array wherein the substrate wafer comprises gallium antimony.
Dixon teaches a focal plane array (col 1, lines 9-10), wherein the substrate wafer is gallium antimony (substrate comprising GaSb, col 5, line 62).
As taught by Dixon, one of ordinary skill in the art would utilize and modify the above teaching into Wicks in view of DeLyon to obtain and achieve the focal plane array wherein the substrate wafer comprises gallium antimony as claimed, because GaSb are well-known material and widely used as a substrate material in the art and is suitable for achieving the desired electro-optical performance (col 5, line 60~col 6, line 2). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dixon in combination with Wicks in view of DeLyon due to above reason.
Regarding claim 12, Wicks in view of DeLyon teaches the focal plane array of claim 9, but does not teach the focal plane array wherein the substrate wafer comprises gallium arsenide.
Dixon teaches a focal plane array (col 1, lines 9-10), wherein the substrate wafer is gallium arsenide (substrate comprising GaAs, col 5, line 63).
As taught by Dixon, one of ordinary skill in the art would utilize and modify the above teaching into Wicks in view of DeLyon to obtain and achieve the focal plane array wherein the substrate wafer comprises gallium arsenide as claimed, because GaAs are well-known material and widely used as a substrate material in the art and is suitable for achieving the desired electro-optical performance (col 5, line 60~col 6, line 2). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dixon in combination with Wicks in view of DeLyon due to above reason.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over DeLyon (US 10720456) in view of Wicks (US 2010/0230720).
Regarding claim 15, DeLyon teaches the focal plane array of claim 1, but does not teach the focal plane array comprising an absorber layer disposed directly atop the substrate wafer, wherein the absorber layer comprises the n-type indium arsenide layer.
Wicks teaches a focal plane array (10, FIGURE 7, [0047, 0054]) comprising an absorber layer disposed directly atop the substrate wafer, wherein the absorber layer comprises the n-type indium arsenide layer (n-InAs 12 disposed directly atop 18 as an absorber layer).
Although Wicks does not explicitly teach that the n-InAs layer is the absorber layer is designated as an “absorber layer”.
Wicks, however, discloses that the n-InAs serves as the photon absorbing layer of the photodiode, generating photocurrent in response to incident light. The photodiode operates by optical creation of electron-hole pair by band-to-band transitions, and the n-InAs is the primary layer where optical absorption and photocurrent generation occur [0048].
As taught by Wicks, one of ordinary skill in the art would utilize and modify the above teaching into DeLyon to obtain and achieve the focal plane array comprising an absorber layer disposed directly atop the substrate wafer, wherein the absorber layer comprises the n-type indium arsenide layer as claimed, because it is well known that focal plane arrays require an absorber layer to generate photocurrent and the-n-InAs layer absorbs incident light to generate photocurrent [0048]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wicks in combination with DeLyon due to above reason.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over DeLyon (US 10720456) in view of Ting et al. (US 2012/0145996 hereinafter ‘Ting’).
Regarding claim 16, DeLyon teaches the focal plane array of claim 1, further comprising a trench through the doped n- type layer and the barrier layer (multiple depositions of Group III-V materials with masking and etching between depositions to define pixels isolated from one another, col. 11, lines 27-32).
DeLyon does not teach the focal plane array further comprising a trench, wherein a bottom end of the trench is defined by the n-type indium arsenide layer.
Ting teaches a focal plane array (1, FIG. 2, [0089]) further comprising a trench, wherein a bottom end of the trench is defined by the n-type indium arsenide layer (the bottom end of the trench is defined by 6).
As taught by Ting, one of ordinary skill in the art would utilize and modify the above teaching into DeLyon to obtain and achieve the focal plane array further comprising a trench, wherein a bottom end of the trench is defined by the n-type indium arsenide layer as claimed, because focal plane arrays require trench formation to electrically isolate pixels and reduce crosstalk [0154]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ting in combination with DeLyon due to above reason.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wicks (US 2010/0230720) in view of DeLyon (US 10720456), and further in view of White (Journal of Lightwave Technology, Vol. 34, Issue. 11).
Regarding claim 17, Wicks in view of DeLyon teaches the focal plane array of claim 9, but does not teach the focal plane array wherein the p-type indium arsenide layer is implanted into the first surface of the n-type indium arsenide layer to a depth of at least 0.5 micron.
White teaches a focal plane array (Fig. 2, II. FABRICATION) wherein the p-type indium arsenide layer is implanted into the first surface of the layer to a depth of at least 0.5 micron (1 µm deep P+ InAs in i InAs)
Although White does not explicitly teach that the p-type indium arsenide layer is implanted into the first surface of the n-type indium arsenide layer.
White, however, discloses the use of ion implantation to achieve a p-type region with a depth of at least 1 µm, further enhanced to 2 µm through thermal annealing. The resulting junction depth and profile is readily tailored by adjusting implantation parameters such as temperature, time, ion species, and equipment settings (Fig. 7, III. RESULTS).
As taught by White, one of ordinary skill in the art would utilize and modify the above teaching into Wicks in view of DeLyon to obtain and achieve the focal plane array wherein the p-type indium arsenide layer is implanted into the first surface of the n-type indium arsenide layer to a depth of at least 0.5 micron as claimed, because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by White in combination with Wicks in view of DeLyon due to above reason.
Regarding claim 18, Wicks in view of DeLyon teaches the focal plane array of claim 9, but does not teach the focal plane array wherein the p-type indium arsenide layer is implanted into the first surface of the n-type indium arsenide layer to a depth of at least 1 micron.
White teaches a focal plane array (Fig. 2, II. FABRICATION) wherein the p-type indium arsenide layer is implanted into the first surface of the layer to a depth of at least 1 micron (1 µm deep P+ InAs in i InAs)
Although White does not explicitly teach that the p-type indium arsenide layer is implanted into the first surface of the n-type indium arsenide layer.
White, however, discloses the use of ion implantation to achieve a p-type region with a depth of at least 1 µm, further enhanced to 2 µm through thermal annealing. The resulting junction depth and profile is readily tailored by adjusting implantation parameters such as temperature, time, ion species, and equipment settings (Fig. 7, III. RESULTS).
As taught by White, one of ordinary skill in the art would utilize and modify the above teaching into Wicks in view of DeLyon to obtain and achieve the focal plane array wherein the p-type indium arsenide layer is implanted into the first surface of the n-type indium arsenide layer to a depth of at least 1 micron as claimed, because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by White in combination with Wicks in view of DeLyon due to above reason.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wicks (US 2010/0230720) in view of DeLyon (US 10720456), and further in view of Ting (US 2012/0145996).
Regarding claim 19, Wicks in view of DeLyon teaches the focal plane array of claim 9, but Wicks does not teach the focal plane array further comprising a trench through the p-type indium arsenide layer, wherein a bottom end of the trench is defined by the n-type indium arsenide layer.
DeLyon teaches the focal plane array further comprising a trench through the p-type indium arsenide layer (multiple depositions of Group III-V materials with masking and etching between depositions to define pixels isolated from one another, col. 11, lines 27-32).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in DeLyon to include the focal plane array further comprising a trench through the p-type indium arsenide layer as claimed, because forming isolated pixels and electrical pathways requires etching through the upper semiconductor layers, which necessarily includes the p-type contact layer to expose the barrier or absorber beneath.
Wicks in view of DeLyon does not teach the focal plane array further comprising a trench, wherein a bottom end of the trench is defined by the n-type indium arsenide layer.
Ting teaches a focal plane array (1, FIG. 2, [0089]) further comprising a trench, wherein a bottom end of the trench is defined by the n-type indium arsenide layer (the bottom end of the trench is defined by 6).
As taught by Ting, one of ordinary skill in the art would utilize and modify the above teaching into Wicks in view of DeLyon to obtain and achieve the focal plane array further comprising a trench, wherein a bottom end of the trench is defined by the n-type indium arsenide layer as claimed, because focal plane arrays require trench formation to electrically isolate pixels and reduce crosstalk [0154]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ting in combination with Wicks in view of DeLyon due to above reason.
Response to Arguments
Applicant's arguments filed on 11/20/2025 have been fully considered.
Applicant submits “Applicant notes that the Office Action cites US 10720465 to DeLyon et al. Office action, p. 3. However, US 10720465 is attributable to Matsumoto et al., which is reflected in error in the List of References Cited by the Examiner of September 2, 2025.” in pages 5-6.
Examiner acknowledges that the citation to “US 10720465” on page 3 of the 09/02/2025 Non-Final Office Action was a typographical error. The correct reference is US 10720456 (DeLyon), as consistently cited throughout the Office Action and throughout the prosecution history.
As noted, DeLyon was correctly cited seven additional times in the same 09/02/2025 Non-Final Office Action (pp. 4, 6, 8, 9, 11, and 13), and all prior Office Actions—including the 01/15/2025 Non-Final Office Action and the 06/16/2025 Final Office Action—also cited US10720456.
Accordingly, this typographical error did not affect the understanding of the applied prior art or the substance of the rejection.
Applicant submits “Notwithstanding, the Office rejects independent claim 1 under 35 U.S.C. 102(a)(1) over DeLyon. Office Action, p. 3. However, underpinning the rejection under 102(a)(1) is obviousness- type logic … Based on the Office's reasoning, it appears that the Office intended to reject this claim under 35 U.S.C. § 103 as obvious over DeLyon to cure the deficiencies of an anticipation rejection under 35 U.S.C. § 102(a)(1).” in pages 6-7.
Examiner acknowledges that the rejection of claim 1 is based on 35 U.S.C. §103. This is clear from the section heading of the Non-Final Office Action dated 09/02/2025, as well as from the subsequent obviousness analysis set forth therein.
The reference to 35 U.S.C. §102(a)(1) appearing in one location of the Office Action was a typographical error and does not reflect the actual statutory basis of the rejection.
The applied rejection has consistently been an obviousness rejection under 35 U.S.C. §103, as supported by the cited statutory provisions, the Graham-factor analysis, and the discussion regarding optimization of a result-effective variable.
Applicant's arguments with respect to claims 1 and 9 have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 12/8/25
Prosecution Insights