DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on February 6, 2026. Claims 1, 14, and 19 have been amended. No new claims have been added. Claims 2 and 15 have been canceled. Claims 3-5, 13, and 16-18 were withdrawn. Currently, claims 1, 6-12, 14, and 19-20 are pending.
Applicant’s amendment to claim 14 successfully overcomes the 112(b) rejection of claim 14 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to amended claims 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by You et al. (US 20200163216).
Regarding claim 1, You teaches, in Figs. 1-3 (annotated below),
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an array substrate ([0049]), comprising a display region (DA, [0050]) and a non-display region (PA, [0050], non-display because it does not have display layer 110), wherein the array substrate comprises:
a base substrate (100, [0062]);
a plurality of extension wires (LK1, [0056], plurality shown in Fig. 3), disposed on a front side (top side) of the base substrate (100) and located in the non-display region (PA) of the array substrate;
a bonding member (121, [0055]), comprising a plurality of bonding pins (121, plurality shown in Fig. 3) disposed in the non-display region (PA) of the array substrate; and
a flexible circuit board (300, [0065]), disposed on a back side (bottom side) of the base substrate (100) (see Fig. 2);
wherein a plurality of first through holes (first group of 122 filled by 123 as marked in Fig. 1, plurality shown in Figs. 1 and 3, [0058]) is defined in the base substrate (100) (see Fig. 2);
a first conductive layer (123, [0058]) is disposed in each of the plurality of first through holes (first group of 122 as marked in Fig. 1) (see Figs. 2-3);
wherein one end (right end) of each of the plurality of extension wires (LK1) adjacent to the respective first through hole (122) is electrically connected to one end (furthest end in marked +D1 direction in Fig. 1) of the flexible circuit board (300) through the first conductive layer (123) disposed in the respective first through hole (122) (see Fig. 2, [0059]-[0060]), and wherein the other end (left end) of the each of the plurality of extension wires (LK1) is connected to a respective data line or scan line (data line) disposed on the array substrate ([0055]); and
wherein the base substrate (100) is a glass base substrate ([0062]);
the plurality of bonding pins (121) are arranged on the front side (top side) of the base substrate (100) (see Fig. 2);
a plurality of second through holes (second group of 122 filled by 123 as marked in Fig. 1, plurality shown in Figs. 1 and 3, [0058]) are further defined in the base substrate (100) (see Fig. 2), and a second conductive layer (123, [0058]) is disposed in each of the plurality of second through holes (second group of 122 as marked in Fig. 1), wherein the other end of the flexible circuit board (closest end in marked –D1 direction in Fig. 1) is electrically connected to the bonding member (121) through the respective second conductive layers (123) disposed in the plurality of second through holes (second group of 122 as marked in Fig. 1) (see Fig. 2, [0059]-[0060]);
the plurality of first through holes (first group of 122) extend through the base substrate (100) from the front side (top side) to the back side (bottom side) thereof (see Fig. 2); and a plurality of first conductive layers (123) are respectively filled in the plurality of first through holes (first group of 122) (see Figs. 2-3), each of the first conductive layers (123) electrically connecting the flexible circuit board (300) on the back side to a corresponding extension wire (LK1) on the front side of the base substrate (see Fig. 2, [0059]-[0060]);
the plurality of second through holes (second group of 122) extend through the base substrate (100) from the front side (top side) to the back side (bottom side) thereof (see Fig. 2); and a plurality of second conductive layers (123) are respectively filled in the plurality of second through holes (second group of 122), each of the second conductive layers (123) electrically connecting the flexible circuit board (300) on the back side to a corresponding bonding pin (121) on the front side (top side) of the base substrate (100) (see Fig. 2, [0059]-[0060]).
Regarding claim 6, You further teaches, in Fig. 3, that a distance between the bonding member (121) and the plurality of extension wires (LK1) is less than a length of the flexible circuit board (300) (see Fig. 3, the distance between 121 and LK1 is zero).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20200163216) in view of Li et al. (WO 2022134013 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025).
Regarding claim 7, You teaches the limitations of claim 1. You does not explicitly teach that a plurality of signal traces are disposed in the flexible circuit board and have equal wire resistances.
In a similar field of endeavor, Li teaches, in Fig. 9A, that a plurality of signal traces (L1) are disposed in the flexible circuit board (4) and have equal wire resistances (L1 have equal wire resistances because their lengths are equal) ([0090]), for the purpose of “facilitating the arrangement of various wirings and allowing various wirings to be distributed on different layers, thereby reducing mutual interference between different types of wirings” ([0072]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array substrate of You with the signal traces of Li, for the purpose of facilitating the arrangement of various wirings and allowing various wirings to be distributed on different layers, thereby reducing mutual interference between different types of wirings ([0072]).
Regarding claim 9, You teaches the limitations of claim 1. You further teaches that no fan-out traces are disposed on the front side of the base substrate (You Fig. 1 does not show fan-out traces).
You does not explicitly teach that the flexible circuit board is bendably disposed on the base substrate, and that each trace disposed on the flexible circuit board has an equal resistance.
In a similar field of endeavor, Li teaches that the flexible circuit board (4) is bendably disposed on the base substrate ([0139]), and that each trace (L1) disposed on the flexible circuit board has an equal resistance (L1 have equal wire resistances because their lengths are equal) ([0090]), for the purpose of “facilitating the arrangement of various wirings and allowing various wirings to be distributed on different layers, thereby reducing mutual interference between different types of wirings” ([0072]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array substrate of You with the flexible circuit board bending and traces of Li, for the purpose of facilitating the arrangement of various wirings and allowing various wirings to be distributed on different layers, thereby reducing mutual interference between different types of wirings ([0072]).
Regarding claim 10, You in view of Li teaches the limitations of claim 9. You further teaches, in Fig. 3, that a distance between the bonding member (121) and the plurality of extension wires (LK1) is less than a length of the flexible circuit board (300) (see Fig. 3, the distance between 121 and LK1 is zero).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20200163216) in view of Lu et al. (CN 112086015 A, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025).
Regarding claim 8, You teaches the limitations of claim 1. You does not explicitly teach that in a wire width direction of the plurality of extension wires, every two adjacent first through holes are staggered.
In a similar field of endeavor, Lu teaches, in Fig. 4, that in a wire width direction (horizontal direction) of the plurality of extension wires (20, [0047]), every two adjacent first through holes (34) are staggered ([0060]), for the purpose of “reducing the operating power consumption and production materials of the display panel” ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of You with the staggering of Lu, for the purpose of reducing the operating power consumption and production materials of the display panel ([0062]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20200163216) in view of Li et al. (WO 2022134013 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025), and further in view of Lu et al. (CN 112086015 A, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025).
Regarding claim 11, You in view of Li teaches the limitations of claim 9. You in view of Li does not explicitly teach that in a wire width direction of the plurality of extension wires, every two adjacent first through holes are staggered.
In a similar field of endeavor, Lu teaches, in Fig. 4, that in a wire width direction (horizontal direction) of the plurality of extension wires (20, [0047]), every two adjacent first through holes (34) are staggered ([0060]), for the purpose of “reducing the operating power consumption and production materials of the display panel” ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of You in view of Li with the staggering of Lu, for the purpose of reducing the operating power consumption and production materials of the display panel ([0062]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20200163216) in view of Wang et al. (US 20240164022).
Regarding claim 12, You teaches the limitations of claim 1. You does not explicitly teach that widths of both ends of the flexible circuit board match a width of the region where the plurality of extension wires are located and a width of a region where the bonding member is located, respectively; and that the front side of the flexible circuit board has a shape of an isosceles trapezoid.
In a similar field of endeavor, Wang teaches, in Figs. 6-8, that widths of both ends (top end and bottom end) of the flexible circuit board (6n, [0112]) match a width of the region where the plurality of extension wires (62, [0113])) are located (bottom end of 6n) and a width of a region where the bonding member (11aa, which 61b connects to, [0124]) is located (top end of 6n), respectively; and that the front side of the flexible circuit board (6n) has a shape of an isosceles trapezoid (Fig. 8), “[i]n order to solve the problem that the flexible circuit board with the large length and high density of conductive contact pieces 1b cannot meet the bonding requirements” ([0106])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array substrate of You with the flexible circuit board of Wang, in order to solve the problem that the flexible circuit board with the large length and high density of conductive contact pieces 1b cannot meet the bonding requirements ([0106]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20200163216) in view of Ge et al. (WO 2020082501 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025) and Chang et al. (WO 2023065302 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025).
Regarding claim 14, You teaches, in Figs. 1-3 (annotated below),
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an array substrate ([0049]), comprising a display region (DA, [0050]) and a non-display region (PA, [0050], non-display because it does not have display layer 110), wherein the array substrate comprises:
a base substrate (100, [0062]);
a plurality of extension wires (LK1, [0056], plurality shown in Fig. 3), disposed on a front side (top side) of the base substrate (100) and located in the non-display region (PA) of the array substrate;
a bonding member (121, [0055]), comprising a plurality of bonding pins (121, plurality shown in Fig. 3) disposed in the non-display region (PA) of the array substrate; and
a flexible circuit board (300, [0065]), disposed on a back side (bottom side) of the base substrate (100) (see Fig. 2);
wherein a plurality of first through holes (first group of 122 filled by 123 as marked in Fig. 1, plurality shown in Figs. 1 and 3, [0058]) is defined in the base substrate (100) (see Fig. 2);
a first conductive layer (123, [0058]) is disposed in each of the plurality of first through holes (first group of 122 as marked in Fig. 1) (see Figs. 2-3);
wherein one end (right end) of each of the plurality of extension wires (LK1) adjacent to the respective first through hole (122) is electrically connected to one end (furthest end in marked +D1 direction in Fig. 1) of the flexible circuit board (300) through the first conductive layer (123) disposed in the respective first through hole (122) (see Fig. 2, [0059]-[0060]), and wherein the other end (left end) of the each of the plurality of extension wires (LK1) is connected to a respective data line or scan line (data line) disposed on the array substrate ([0055]); and
wherein the base substrate (100) is a glass base substrate ([0062]);
the plurality of bonding pins (121) are arranged on the front side (top side) of the base substrate (100) (see Fig. 2);
a plurality of second through holes (second group of 122 filled by 123 as marked in Fig. 1, plurality shown in Figs. 1 and 3, [0058]) are further defined in the base substrate (100) (see Fig. 2), and a second conductive layer (123, [0058]) is disposed in each of the plurality of second through holes (second group of 122 as marked in Fig. 1), wherein the other end of the flexible circuit board (closest end in marked –D1 direction in Fig. 1) is electrically connected to the bonding member (121) through the respective second conductive layers (123) disposed in the plurality of second through holes (second group of 122 as marked in Fig. 1) (see Fig. 2, [0059]-[0060]);
the plurality of first through holes (first group of 122) extend through the base substrate (100) from the front side (top side) to the back side (bottom side) thereof (see Fig. 2); and a plurality of first conductive layers (123) are respectively filled in the plurality of first through holes (first group of 122) (see Figs. 2-3), each of the first conductive layers (123) electrically connecting the flexible circuit board (300) on the back side to a corresponding extension wire (LK1) on the front side of the base substrate (see Fig. 2, [0059]-[0060]);
the plurality of second through holes (second group of 122) extend through the base substrate (100) from the front side (top side) to the back side (bottom side) thereof (see Fig. 2); and a plurality of second conductive layers (123) are respectively filled in the plurality of second through holes (second group of 122), each of the second conductive layers (123) electrically connecting the flexible circuit board (300) on the back side to a corresponding bonding pin (121) on the front side (top side) of the base substrate (100) (see Fig. 2, [0059]-[0060]).
You does not teach that the display device comprises a backlight module, that the display panel comprises a counter substrate, wherein the counter substrate and the array substrate are aligned and bonded together to form a cell; and that the backlight module comprises a back plate, and a groove is defined in the back plate and corresponding to the flexible circuit board, and wherein the flexible circuit board is accommodated in the groove.
In a similar field of endeavor, Ge teaches, in Fig. 12, that the display device (500) comprises a backlight module (400, [0085]), that the display panel comprises a counter substrate (200, [0085]), and that the counter substrate and the array substrate (100, [0085]) are aligned and bonded together to form a cell ([0085]), for the purpose of “reducing the light leakage current and ensuring the stability of the pixel voltage and the stability of the displayed image” ([0085]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of You with the backlight module and counter substrate configuration of Ge, for the purpose of reducing the light leakage current and ensuring the stability of the pixel voltage and the stability of the displayed image ([0085]).
You in view of Ge does not explicitly teach that the backlight module comprises a back plate, and a groove is defined in the back plate and corresponding to the flexible circuit board, and wherein the flexible circuit board is accommodated in the groove.
In a similar field of endeavor, Chang teaches that the backlight module (300, Fig. 8, [0031]) comprises a back plate (100, Figs. 3 and 7-8, [0031]), and a groove (130, Fig. 3, [0033]) is defined in the back plate and corresponding to the flexible circuit board (210, [0033]), and wherein the flexible circuit board (210) is accommodated in the groove (see Figs. 7-8, [0033]), so that “the entire light source module 200 does not require adhesive for positioning during the assembly process, which can shorten the assembly or rework time, increase the product production yield, reduce costs, and improve the overall value of the backlight module” ([0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of You in view of Ge with the backlight module configuration of Chang, so that the flexible circuit board does not require adhesive for positioning during the assembly process, which can shorten the assembly or rework time, increase the product production yield, reduce costs, and improve the overall value of the backlight module ([0033]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20200163216) in view of Ge et al. (WO 2020082501 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025) and Chang et al. (WO 2023065302 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025), and further in view of Li et al. (WO 2022134013 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025).
Regarding claim 19, You in view of Ge and Chang teaches the limitations of claim 14. You in view of Ge and Chang further teaches that no fan-out traces are disposed on the front side of the base substrate (for example, You Fig. 1 does not show fan-out traces), and that the plurality of bonding pins (121) are arranged on the front side (top side) of the base substrate (100).
You in view of Ge and Chang does not explicitly teach that the flexible circuit board is bendably disposed on the base substrate, and that each trace disposed on the flexible circuit board has an equal resistance.
In a similar field of endeavor, Li teaches that the flexible circuit board (4) is bendably disposed on the base substrate ([0139]), and that each trace (L1) disposed on the flexible circuit board has an equal resistance (L1 have equal wire resistances because their lengths are equal) ([0090]), for the purpose of “facilitating the arrangement of various wirings and allowing various wirings to be distributed on different layers, thereby reducing mutual interference between different types of wirings” ([0072]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array substrate of You in view of Ge and Chang with the flexible circuit board bending and traces of Li, for the purpose of facilitating the arrangement of various wirings and allowing various wirings to be distributed on different layers, thereby reducing mutual interference between different types of wirings ([0072]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20200163216) in view of Ge et al. (WO 2020082501 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025) and Chang et al. (WO 2023065302 A1, citations made hereinafter to the English machine translation attached to the Office Action mailed on December 2, 2025), and further in view of Zhang et al. (US2023207542).
Regarding claim 20, You in view of Ge and Chang teaches the limitations of claim 14. You in view of Ge and Chang does not explicitly teach a driving circuit board bonded with the plurality of bonding pins.
In a similar field of endeavor, Zhang teaches a driving circuit board bonded with the plurality of bonding pins (230, Fig. 1-2) ([0105]), in order to “avoid the binding pad from being damaged” (Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array substrate of You in view of Ge and Chang with the driving circuit board arrangement of Zhang, in order to avoid the bonding from being damaged (Abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 11:30-8:30 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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